JPH03212729A - Data buffer division control system - Google Patents

Abstract

PURPOSE:To shorten a transfer processing time by dividing a data buffer into two areas, and when data transfer using one area is repeated, using the other area in the data buffer for the other data transfer by a repeating processing means. CONSTITUTION:Data buffers (#0, #1) 210, 211 are obtained by dividing the buffer area into two areas. Leading addresses corresponding to respective buffer areas are set up from a control system not shown in figure in a writing address register(WADR) 23 and a reading address register(RADR) 25 through respective AND gates 27, 29 and respective addresses to be updated up to buffer areas specified by respective incrementors '+1' 31, 33 are supplied to the buffer 21. On the other hand, the contents of the registers 23, 25 are saved in respectively corresponding storage registers (SWADR, SRADR) 39, 41 through respective AND gates 35, 37. The contents of respective registers 39, 41 are set up in respective registers 23, 25 through AND gates 43, 45.

Description

[Detailed Description of the Invention] [Summary] Regarding a data buffer division control method that divides and controls a large-capacity data buffer provided for speeding up data transfer, the present invention guarantees that data is taken in advance when data transfer is interrupted. death,
In a data buffer control circuit that uses a data buffer to buffer transferred data with the aim of reducing data transfer time when restarting, the data buffer has a configuration in which its area is divided into two. , when the data transfer with the first medium using one area of the data buffer is interrupted, the buffer address at that time is stored, and when the data is transferred with the second medium thereafter, the other area of the data buffer is used. an interruption processing means for instructing data transfer using one area of the data buffer, and a restart processing for instructing data transfer using one area of the data buffer by resetting the buffer address at the time of interruption when data transfer between the first medium and the first medium is resumed; and means.

[Industrial application field]

The present invention relates to a data buffer division control method for dividing and controlling a large-capacity data buffer provided for speeding up data transfer.

[Prior Art] In a configuration for transferring a large amount of data, a large-capacity data buffer is arranged between devices that transfer data, and data transfer speed is increased by controlling a data buffer control circuit.

Here, FIG. 4 shows the configuration of a channel device that performs data transfer.

In FIG. 4, the channel device 70 includes an input/output bus 61
The input/output hash control circuit 71 and each input/output device 6 connected to
The input/output device control circuit 73, the input/output bus control circuit 71, and the input/output device control circuit 73 connected to Ru.

FIG. 5 is a diagram illustrating the operation of a conventional data buffer.

In the figure, write address register (WADR) 8
1 and read address register (RADR) 83
A predetermined start address is set in each of the addresses according to writing or reading of transfer data.

Data input to the data buffer 75 is sequentially written in accordance with the write address output by the write address register 81. Furthermore, the data output from the data buffer 75 is sequentially read out according to the read address output from the read address register 83. Note that the addresses output by the write address register 81 and the read address register 83 are updated via incrementers (+1) 85 and 87, respectively.

[Problem to be solved by the invention]

By the way, in the conventional configuration, when data transfer is temporarily interrupted due to, for example, disconnection of an input/output device, the data buffer prefetches the transferred data.
There is still valid data that has not been transferred.

On the other hand, if data transfer is interrupted, it is necessary to immediately shift to control for data transfer with other input/output devices in terms of efficiency. Therefore, I had no choice but to invalidate all remaining data.

Therefore, in order to resume the data transfer before the interruption, it was necessary to re-acquire the data from where it was interrupted.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data buffer division control method that can guarantee data that has been fetched in advance when data transfer is interrupted and can reduce data transfer time when data transfer is restarted.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the data buffer 11 has a configuration in which its area is divided into two parts.

The interruption processing means 13 stores the buffer address at that time when data transfer with the first medium using one area of the data buffer 11 is interrupted, and stores the data at the time of data transfer with the second medium thereafter. This configuration instructs data transfer using the other area of the buffer 11.

The restart processing means 15 is configured to reset the buffer address at the time of interruption and instruct data transfer using one area of the data buffer 11 when data transfer with the first medium is resumed.

[For production]

The present invention divides the area of the data buffer 11 into two, and when data transfer using one area is interrupted, the interruption processing means 13 handles the data transfer using the data buffer 11.
By instructing the use of other areas, it is possible to save prefetched data until the transfer is interrupted.

Therefore, when restarting the transfer, the restart processing means 15 again specifies the area of the data buffer 11 that was being used at the time of interruption, and performs data transfer from the prefetched data.
It is possible to reduce the transfer time of restarted data transfer.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

In this embodiment, a data buffer in a channel device that controls data transfer of a plurality of input/output devices will be described.

In the figure, data buffers (#0, #1) 21°, 2
1, the buffer area is divided into two. The write address register (WADR) 23 and the read address register (RADR) 25 are set with the start address corresponding to each buffer area from the supination control system via AND gates 27 and 29, and the incrementer (+1) 31 .33, the data buffer 21 is supplied with an address that is updated up to the designated buffer area.

Furthermore, the contents of the write address register 23 and the read address register 25 are stored in the AND gate 35.37.
via the respective store registers (SWADR
, 5RADR) Safe at 39.41. Also,
The contents of each store register 39.41 are stored in the AND gate 4
3.45 to the write address register 23 and read address register 25.

The flip-flops 47 and 49 have logic "1" between the input of the disconnect signal R and the input of the connect signal R.
”, and this interruption control signal SUS is generated by the datum 7 fa (#1) 21.
．． data buffer (#0) 21. through the enable terminal and inverters 51.53. Connected to the enable terminal of the

Further, the NOR gate 55 and the AND gate 57 take the NOR and AND of the interruption control signal SUS and the inverted output d of the flip-flop 47, respectively, and output the save control signal CHI and the return control signal CH2, respectively. Note that this save control signal CHI is applied to the AND gate 2
7.29.35.37, and the return control signal CH2 is used to control the AND gate 43.45.

Here, FIG. 3 shows a time chart of the logic levels of each signal.

With this configuration, until the disconnect signal R is input and after the reconnect signal R is input, the interrupt control signal SUS is at logic "O", so the data buffer (#0) 21° is disabled. Since the interruption control signal SUS is logic "1" from the input of the disconnect signal R to the input of the connect signal R, the data buffer (#1) 21+ is enabled and data is alternately input. It can function as a buffer.

Therefore, when the data buffer (#0) 21°, which is normally used for data transfer with the input/output device A, receives a disconnect signal from the input/output device, the save control signal CHI changes to logic "1". ” and is disabled, and the contents of the write address register 23 or read address register 25 are changed to the AND gate 35.37.
are saved in store registers 39 and 41, respectively.

On the other hand, the write address register 23 or the read address register 25 contains an address (starting address of the data buffer (#1) 21) necessary for data transfer from another input/output device B via the AND gates 27 and 29.
is set, and thereafter the data buffer (#1) 21. Data transfer takes place via.

Here, when the data transfer of the input/output device B is completed, the reconnect signal R is notified from the input/output device A, the return control signal CH2 becomes logic "1", and the store register 39.
The contents of 1 are set in the write address register 23 or the read address register 25 through AND gates 43 and 45, respectively. Therefore, data buffer (#0) 21. The interrupted data transfer with the input/output device A can be resumed from the data read ahead and held.

In other words, the data that was previously fetched at the time when the data transfer with input/output device A was interrupted is transferred to the data buffer (#
0) 21°, and by resetting the address at the time of interruption when data transfer is resumed, the data buffer (
#0) Data transfer using 21° can be restarted, and efficient data transfer processing can be performed without wasting prefetched data.

〔Effect of the invention〕

As described above, according to the present invention, when data transfer is interrupted, by guaranteeing the data that was previously fetched at that time, it is possible to reduce the transfer processing time after data transfer is resumed. .

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing the configuration of an embodiment of the invention, Fig. 3 is a time chart showing the status of each signal, and Fig. 4 is a channel device for data transfer. FIG. 5 is a diagram illustrating the operation of a conventional data buffer. In the figure, 11 is a data buffer, 13 is an interruption processing means, 15 is a restart processing means, 21 is a data buffer, 23 is a write address register (WADR), 25 is a read address register (RADR), 27.29.
35.37.43.45.57 is an AND gate, 3L33 is an incrementer (+1), 9.41 is a store register (SWADR7, 49 are flip-flops, l, 53 is an inverter, 5 is a NOR gate. 5RADR), Data Block diagram of the principles of the present invention Figure 3 Clock signal CLK Disc signal Time chart showing the status of each signal Figure 3 First address First address Block diagram showing the configuration of the embodiment of the present invention Channel device for data transfer Mouth diagram data showing the composition of

Claims (1)

[Claims] (1) In a data buffer control circuit that buffers transfer data using a data buffer, the data buffer (11) has a configuration in which its area is divided into two parts, and one of the data buffers (11) When data transfer using the area is interrupted with the first medium, the buffer address at that time is stored, and the other area of the data buffer (11) is used for subsequent data transfer with the second medium. An interruption processing means (13) for instructing data transfer, and when resuming data transfer with the first medium, the buffer address at the time of the interruption is reset and one area of the data buffer (11) is used. 1. A data buffer division control system comprising: a restart processing means (15) for instructing data transfer.