JPH03212960A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03212960A
JPH03212960A JP2008810A JP881090A JPH03212960A JP H03212960 A JPH03212960 A JP H03212960A JP 2008810 A JP2008810 A JP 2008810A JP 881090 A JP881090 A JP 881090A JP H03212960 A JPH03212960 A JP H03212960A
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor device
layer
resin
sealing layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008810A
Other languages
Japanese (ja)
Inventor
Kazuhiko Tokumaru
徳丸 和彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Chemical Corp
Original Assignee
Toshiba Chemical Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Chemical Corp filed Critical Toshiba Chemical Corp
Priority to JP2008810A priority Critical patent/JPH03212960A/en
Publication of JPH03212960A publication Critical patent/JPH03212960A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent a resin from flowing into a through hole by a method wherein the opening end part of the through hole is blocked up by using a coating hardened layer of an organic compound resist. CONSTITUTION:A coating hardened layer 17 of a resist ink is formed on a circuit board 10 around a semiconductor chip 13. The opening end on the surface side of through holes 12 is blocked up completely. Thereby, it is possible to prevent that an epoxy-resin sealing layer 18 formed at the upper part flows into the holes 12. Since the layer 18 is formed by a transfer molding method, pads 14 of an inserted semiconductor chip 13 and connecting wires 16 are not carried away by a pressed-into resin and are not destroyed and a good characteristic can be obtained.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、回路基板上に半導体素子が実装され、かつそ
の外側が絶縁性樹脂によって封止された半導体装置に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device in which a semiconductor element is mounted on a circuit board and the outside thereof is sealed with an insulating resin.

(従来の技術) 近年電子機器の分野では、小型化、薄型化がますます進
められ、これが商品としての付加価値を高めるための重
要な要素になっている。そのため、回路基板上に半導体
チップのような半導体素子が実装され、かつその外側が
絶縁性樹脂で封止された半導体装置においても、全体の
厚さをできるだけ薄くすることが要求されている。
(Prior Art) In recent years, in the field of electronic devices, miniaturization and thinning have been progressing more and more, and this has become an important element for increasing the added value of products. Therefore, even in a semiconductor device in which a semiconductor element such as a semiconductor chip is mounted on a circuit board and the outside thereof is sealed with an insulating resin, the overall thickness is required to be as thin as possible.

従来からこのような半導体装置としては、第2図に示す
ように、表面または内部に導電回路1が形成され、かつ
表裏を貫通する複数のスルーホール2が形成された回路
基板3上の所定の位置に、導電性接着剤等を用いて半導
体チップ4を直接ダイボンドするとともに、この半導体
チップ4のバッド5と回路基板3上に形成されたリード
フレーム6とを、金線等のワイヤ7によって接続し、さ
らにこれらの外側に、エポキシ樹脂やシリコーン樹脂の
ような液状の絶縁性樹脂をポツティング(注型)し、半
導体チップ4を気密に封止した構造の装置が使用されて
いる。
Conventionally, as shown in FIG. 2, such a semiconductor device has a predetermined structure on a circuit board 3 on which a conductive circuit 1 is formed on the surface or inside and a plurality of through holes 2 passing through the front and back sides. The semiconductor chip 4 is directly die-bonded to the position using a conductive adhesive or the like, and the pads 5 of the semiconductor chip 4 and the lead frame 6 formed on the circuit board 3 are connected using wires 7 such as gold wires. Furthermore, a device is used in which a liquid insulating resin such as epoxy resin or silicone resin is potted (cast) on the outside of these, and the semiconductor chip 4 is hermetically sealed.

そしてこのような半導体装置においては、装置全体の厚
さをできるだけ薄くするために、絶縁性樹脂の封止層8
の厚さをできるだけ薄くすることが重要な課題となって
いる。
In such a semiconductor device, in order to make the overall thickness of the device as thin as possible, a sealing layer 8 of insulating resin is used.
An important issue is to make the thickness as thin as possible.

そのため液状絶縁性樹脂として低粘度のものを使用し、
かつポツティングの際に半導体チップ4の周りの回路基
板3上に、丁度底部でスルーホール2を塞ぐように枠体
9を設け、液状絶縁性樹脂の周囲への流出を防止すると
ともに、スルーホール2への流入を防止することが行わ
れている。
Therefore, we use a low viscosity liquid insulating resin,
In addition, during potting, a frame 9 is provided on the circuit board 3 around the semiconductor chip 4 so as to close the through hole 2 at the bottom to prevent the liquid insulating resin from flowing out around the through hole 2. Efforts are being taken to prevent the influx.

(発明が解決しようとする課題) しかしながらこのように構成される従来の半導体装置に
おいては、液状絶縁性樹脂の粘度と注入量の調節とを行
うことが難しいばかりでなく、封止層8の上面が平滑に
ならず、外観上好ましくないという問題があった。
(Problem to be Solved by the Invention) However, in the conventional semiconductor device configured as described above, it is not only difficult to adjust the viscosity and injection amount of the liquid insulating resin, but also the upper surface of the sealing layer 8 There was a problem in that the surface was not smooth and had an unfavorable appearance.

本発明はこれらの問題を解決するためになされたもので
、薄くて下側の回路基板との密着性が良く、かつ外観と
特性の良好な絶縁性樹脂層によって、半導体素子が封止
されており、しかもその封止層を構成する絶縁性樹脂の
スルーホールへの流入等が防止された半導体装置を提供
することを目的とする。
The present invention was made to solve these problems, and semiconductor elements are encapsulated with an insulating resin layer that is thin and has good adhesion to the underlying circuit board, and has good appearance and characteristics. An object of the present invention is to provide a semiconductor device in which an insulating resin constituting a sealing layer is prevented from flowing into a through hole.

[発明の構成] (課題を解決するための手段) 本発明の半導体装置は、表面に導電回路が形成され、か
つ表裏を貫通して複数のスルーホールが形成された回路
基板上の所定の位置に、半導体素子を実装するとともに
、前記半導体素子の外側を絶縁性樹脂によって封止して
なる半導体装置において、前記半導体素子の実装部の周
囲の回路基板上に、有機化合物系レジストの塗布硬化層
を設けられ、かつ前記絶縁性樹脂からなる封止層が、熱
−硬化性樹脂のトランスファー成形によって形成された
ものであることを特徴としている。
[Structure of the Invention] (Means for Solving the Problems) A semiconductor device of the present invention is provided at a predetermined position on a circuit board on which a conductive circuit is formed and a plurality of through holes are formed through the front and back sides. In a semiconductor device in which a semiconductor element is mounted and the outside of the semiconductor element is sealed with an insulating resin, a coated hardened layer of an organic compound resist is provided on the circuit board around the mounting part of the semiconductor element. The sealing layer made of the insulating resin is formed by transfer molding of a thermosetting resin.

(作用) 本発明の半導体装置においては、半導体素子が実装され
た部分の周囲の回路基板上に、有機化合物系レジストの
塗布硬化層が設けられており、この塗布硬化層がスルー
ホールの少なくとも表面側の開口端部に埋入された状態
になっているので、これによってスルーホールが完全に
閉塞されている。
(Function) In the semiconductor device of the present invention, a hardened coating layer of an organic compound resist is provided on the circuit board around the portion where the semiconductor element is mounted, and this hardened coating layer is applied to at least the surface of the through hole. Since it is embedded in the open end of the side, the through hole is completely closed.

したがって、実装された半導体素子の上からトランスフ
ァー成形される流動状態の熱硬化性樹脂が、スルーホー
ルの内部まで流入することがない。
Therefore, the thermosetting resin in a fluid state that is transfer-molded from above the mounted semiconductor element does not flow into the through hole.

また絶縁性樹脂からなる封止層が、熱硬化性樹脂のトラ
ンスファー成形によって形成されているので、この層が
ボッティングによって形成された従来からの半導体装置
に比べて、封止層の厚さを薄くすることができ、装置全
体の小型化、薄型化を図ることができる。
In addition, since the sealing layer made of insulating resin is formed by transfer molding of thermosetting resin, the thickness of the sealing layer can be reduced compared to conventional semiconductor devices in which this layer is formed by botting. It can be made thinner, and the entire device can be made smaller and thinner.

さらに封止層の大部分が、有機化合物系レジストの塗布
硬化層の上に設けられているので、封止層と回路基板と
の密着性が改善されている。
Furthermore, since most of the sealing layer is provided on the coated and cured layer of organic compound resist, the adhesion between the sealing layer and the circuit board is improved.

(実施例) 以下、本発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described below based on the drawings.

第1図は本発明の半導体装置の一実施例を示す横断面図
である。
FIG. 1 is a cross-sectional view showing an embodiment of the semiconductor device of the present invention.

図において符号10は、表面に銅箔のエツチング等によ
って導電回路11が形成され、かつ表裏を貫通して複数
のスルーホール12が設けられた回路基板を示し、この
回路基板10上の所定の位置には、半導体チップ13が
導電性接着剤(図示を省略。)によってダイボンドされ
ている。
In the figure, reference numeral 10 indicates a circuit board on which a conductive circuit 11 is formed by etching copper foil or the like, and a plurality of through holes 12 are provided through the front and back sides. A semiconductor chip 13 is die-bonded with a conductive adhesive (not shown).

そしてこの半導体チップ13のバッド14と回路基板1
0上のリードフレーム15とは、金線等のワイヤ16に
よって電気的に接続されている。
And the pad 14 of this semiconductor chip 13 and the circuit board 1
The lead frame 15 on the top of the lead frame 15 is electrically connected by a wire 16 such as a gold wire.

またこのように回路基板10上の半導体チップ13の周
囲領域、すなわちチップのダイボンド部分とリードフレ
ーム15を除いた回路基板10上には、熱硬化性あるい
はUV(紫外線)硬化性の有機化合物系レジストインク
の塗布硬化層17が設けられている。そしてこの塗布硬
化層17の下部は、スルーホール12の開口端からその
内部へ埋入し、スルーホール12の表面側の開口端部は
この塗布硬化層17によって完全に閉塞されている。
Further, in this way, a thermosetting or UV (ultraviolet) curing organic compound resist is applied to the area around the semiconductor chip 13 on the circuit board 10, that is, on the circuit board 10 excluding the die-bonding part of the chip and the lead frame 15. A coating hardening layer 17 of ink is provided. The lower part of the cured coating layer 17 is embedded into the through hole 12 from its open end, and the open end of the through hole 12 on the surface side is completely closed by the cured coating layer 17.

さらに半導体チップ13の外側には、周囲に設けられた
レジストインクの塗布硬化層17に跨がって、エポキシ
樹脂からなる封止層18が、以下に示すようなトランス
ファー成形法によって形成されている。
Further, on the outside of the semiconductor chip 13, a sealing layer 18 made of epoxy resin is formed by a transfer molding method as shown below, spanning over a coated and cured layer 17 of resist ink provided around the semiconductor chip 13. .

すなわち半導体チップ13の周囲のレジストインクの塗
布硬化層17の上に、加熱手段を備えた矩形の型枠を配
置し、予めチャンバ(ポット)内で加熱され可塑化され
たエポキシ樹脂を、この型枠のキャビティ内にプランジ
ャーで圧入移送し、次いでこれを加熱硬化させることに
よって、封止層18が形成されている。
That is, a rectangular formwork equipped with heating means is placed on the coated and cured layer 17 of resist ink around the semiconductor chip 13, and the epoxy resin, which has been heated and plasticized in a chamber (pot) in advance, is placed in this form. The sealing layer 18 is formed by press-fitting and transferring it into the cavity of the frame using a plunger, and then heating and curing it.

このように構成される実施例の半導体装置においては、
半導体チップ13の周囲の回路基板10上に、レジスト
インクの塗布硬化層17が設けられており、この塗布硬
化層17によってスルーホール12の表面側開口端が完
全に閉塞されているので、その上に形成されたエポキシ
樹脂からなる封止層18が、スルーホール12の内部へ
流入することがない。
In the semiconductor device of the embodiment configured in this way,
A cured coating layer 17 of resist ink is provided on the circuit board 10 around the semiconductor chip 13, and the cured coating layer 17 completely closes the opening end of the through hole 12 on the surface side. The sealing layer 18 formed of epoxy resin does not flow into the through hole 12.

またこのエポキシ樹脂からなる封止層18が、トランス
ファー成形法によって形成されているので、インサート
されている半導体チップ13のバッド14や、これを回
路基板10と接続するワイヤ16等が、圧入される樹脂
によって抑流されて壊れるようなことがない。また均一
な品質を有する成形体が形成されるので、特性の良好な
半導体装置が得られる。
Furthermore, since the sealing layer 18 made of epoxy resin is formed by a transfer molding method, the pad 14 of the inserted semiconductor chip 13 and the wires 16 connecting it to the circuit board 10 are press-fitted. There is no chance of it being suppressed by the resin and breaking. Further, since a molded body having uniform quality is formed, a semiconductor device with good characteristics can be obtained.

さらにこのような封止層18を、ポツティングによって
直接回路基板10上に設けた従来の半導体装置に比べて
、封止層18と回路基板10との密着性に優れ、装置全
体の機械的強度が向上している。
Furthermore, compared to conventional semiconductor devices in which such a sealing layer 18 is provided directly on the circuit board 10 by potting, the adhesiveness between the sealing layer 18 and the circuit board 10 is excellent, and the mechanical strength of the entire device is improved. It's improving.

また封止層18の厚さをできるだけ薄くすることができ
るので、半導体装置全体の小型化、薄型化を図ることが
できる。
Furthermore, since the thickness of the sealing layer 18 can be made as thin as possible, the entire semiconductor device can be made smaller and thinner.

[発明の効果] 以上説明したように本発明の半導体装置においては、実
装された半導体素子の周囲の回路基板上に、有機化合物
系レジストの塗布硬化層が設けられており、この塗布硬
化層によってスルーホールの開口端部が閉塞されている
ので、スルーホール内部への封止用絶縁性樹脂の流入が
防止される。
[Effects of the Invention] As explained above, in the semiconductor device of the present invention, a coated hardened layer of an organic compound resist is provided on the circuit board around the mounted semiconductor element, and this coated hardened layer Since the opening end of the through hole is closed, the sealing insulating resin is prevented from flowing into the through hole.

またこのような絶縁性樹脂からなる封止層の大部分が、
この塗布硬化層の上に設けられているので、封止層と回
路基板との密着性が良好であり、装置全体の機械的強度
が向上している。
In addition, most of the sealing layer made of such insulating resin is
Since it is provided on the cured coating layer, the adhesiveness between the sealing layer and the circuit board is good, and the mechanical strength of the entire device is improved.

さらに封止層がトランスファー成形によって形成されて
いるので、封止層の厚さを薄くすることができ、半導体
装置全体の小型薄型化を図ることができる。
Furthermore, since the sealing layer is formed by transfer molding, the thickness of the sealing layer can be reduced, and the entire semiconductor device can be made smaller and thinner.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の半導体装置の一実施例を示す横断面図
、第2図は従来の半導体装置を説明するための横断面図
である。 10・・・・・・・・・回路基板 11・・・・・・・・・導電回路 12・・・・・・・・・スルーホール 13・・・・・・・・・半導体チップ 16・・・・・・・・・ワイヤ
FIG. 1 is a cross-sectional view showing an embodiment of the semiconductor device of the present invention, and FIG. 2 is a cross-sectional view illustrating a conventional semiconductor device. 10......Circuit board 11...Conductive circuit 12...Through hole 13...Semiconductor chip 16.・・・・・・Wire

Claims (1)

【特許請求の範囲】[Claims] (1)表面に導電回路が形成され、かつ表裏を貫通して
複数のスルーホールが形成された回路基板上の所定の位
置に、半導体素子を実装するとともに、前記半導体素子
の外側を絶縁性樹脂によって封止してなる半導体装置に
おいて、前記半導体素子の実装部の周囲の回路基板上に
、有機化合物系レジストの塗布硬化層が設けられ、かつ
前記絶縁性樹脂からなる封止層が、熱硬化性樹脂のトラ
ンスファー成形によって形成されたものであることを特
徴とする半導体装置
(1) A semiconductor element is mounted at a predetermined position on a circuit board on which a conductive circuit is formed on the front surface and a plurality of through holes are formed passing through the front and back sides, and the outside of the semiconductor element is covered with an insulating resin. In the semiconductor device sealed by the semiconductor device, a coated and cured layer of an organic compound resist is provided on the circuit board around the mounting portion of the semiconductor element, and the sealing layer made of the insulating resin is heat-cured. A semiconductor device characterized in that it is formed by transfer molding of a synthetic resin.
JP2008810A 1990-01-18 1990-01-18 Semiconductor device Pending JPH03212960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008810A JPH03212960A (en) 1990-01-18 1990-01-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008810A JPH03212960A (en) 1990-01-18 1990-01-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03212960A true JPH03212960A (en) 1991-09-18

Family

ID=11703191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008810A Pending JPH03212960A (en) 1990-01-18 1990-01-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03212960A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0566996U (en) * 1992-02-07 1993-09-03 ソニー株式会社 Semiconductor device
US5729437A (en) * 1994-06-22 1998-03-17 Seiko Epson Corporation Electronic part including a thin body of molding resin
US5832600A (en) * 1995-06-06 1998-11-10 Seiko Epson Corporation Method of mounting electronic parts
DE102014201945B4 (en) * 2014-02-04 2025-09-18 Zf Friedrichshafen Ag Electronic unit with short-circuit protection, control device and method therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0566996U (en) * 1992-02-07 1993-09-03 ソニー株式会社 Semiconductor device
US5729437A (en) * 1994-06-22 1998-03-17 Seiko Epson Corporation Electronic part including a thin body of molding resin
US5832600A (en) * 1995-06-06 1998-11-10 Seiko Epson Corporation Method of mounting electronic parts
DE102014201945B4 (en) * 2014-02-04 2025-09-18 Zf Friedrichshafen Ag Electronic unit with short-circuit protection, control device and method therefor

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