JPH03214193A - Liquid crystal panel driving circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption by converting digital image data in one horizontal scanning period into pulses with pulse width corresponding to the respective digital image data in liquid crystal cell units and holding a reference voltage which varies with time in a capacitor for the sample hold with these pulses. CONSTITUTION:The respective latched data are outputted as pulses PW1-PWN which have maximum pulse width a little bit shorter than one horizontal scanning period and are processed by the pulse-width modulation of respective decoders 31-3N to pulse width corresponding to the respective data according clock pulses CKD for decoding. Switch circuits S1-SN close switched only when the pulses PW1-PWN which are modulated by the decoders 31-3N with pulse width have a high level, and the reference voltage having the level corresponding to the pulse width is held by capacitors C1-CN, and amplified and outputted by output buffer amplifiers A1-AN. Consequently, the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal panel drive circuit, and particularly to a liquid crystal panel drive circuit that receives digitally processed image data as input.

[Conventional technology]

Conventionally, this type of liquid crystal panel drive circuit has a configuration as shown in FIG. 4, as an example.

First, digital image data DT is input to the DA converter 6 and converted into an analog signal Vv.

The converted analog signal Vv is transferred to sample-and-hold capacitors C1 to CN corresponding to the number of liquid crystal cells for one horizontal scanning line of the liquid crystal panel and a sample-and-hold switch circuit S! ~Kept under the control of SN.

The switch circuits 81 to Ss are controlled by shift pulses SP1 to SPN that move through each stage of the shift register 7.

The analog signal Vv sampled and held in the capacitors C1 to Cs is amplified by the output buffer amplifiers A1 to AN, and outputs V. 1 to VON to drive each liquid crystal cell of an active matrix type liquid crystal panel.

FIG. 5 shows a timing diagram of this liquid crystal panel drive circuit.

As can be seen from FIG. 5, the digital image data DT for one input horizontal scanning line is sampled and output within each horizontal scanning period.

[Problem to be solved by the invention]

The above-mentioned conventional liquid crystal panel drive circuit has a configuration in which: 1. digital image data DT for one horizontal scanning line of the liquid crystal panel is sequentially sampled and output during the horizontal scanning period; Since a very fast settling time is required, such a -A converter is generally difficult to implement and has the drawbacks of high power consumption.

In addition, since the analog signal (1) to be converted is sampled and held as is with a shift pulse of a constant pulse width and outputted, there is a drawback that it is not possible to deal with cases where the characteristics of liquid crystal panels differ.

The purpose of the present invention is to require a very fast settling time, which is difficult to achieve; it eliminates the need for an A converter;
Therefore, it is an object of the present invention to provide a liquid crystal panel drive circuit that can reduce power consumption and can be used for liquid crystal panels with different characteristics.

[Means to solve the problem]

The liquid crystal panel driving circuit of the present invention includes a plurality of shift register stages provided corresponding to each liquid crystal cell of one horizontal scanning line of a liquid crystal panel, and sequentially shifts input digital image data to each of the shift registers. A shift register unit is provided corresponding to each shift register stage of the shift register unit, and output data of each shift register stage is provided at a predetermined timing. a latch section provided with a plurality of latch circuits that respectively latch and output, and a latch section provided corresponding to each latch circuit of the latch section,
A decoder unit includes a plurality of decoders that respectively output pulses with pulse widths corresponding to the output data of each of these latch circuits at a predetermined timing, and a reference voltage whose voltage changes over time for each horizontal scanning period. a reference voltage generation circuit that generates a reference voltage, and a plurality of switch circuits that are provided corresponding to each decoder of the decoder section and that output the reference voltage correspondingly for a period of a pulse width of a pulse output from each of these decoders. , a plurality of sample-and-hold capacitors that respectively hold the output voltages of these switch circuits, and a plurality of output buffer amplifiers that respectively amplify and output the holding voltages of these capacitors. There is.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, a plurality of shift register stages 11 to IN are provided corresponding to each liquid crystal cell of one horizontal scanning line of a liquid crystal panel.
a shift register section 1 which sequentially shifts the input digital image data DT in accordance with a shift clock pulse CKs and takes in and outputs the digital image data DT corresponding to each liquid crystal cell to each shift register stage 11 to IN; Each shift register stage 1 of shift register section 1
A plurality of latch circuits 2 are provided corresponding to the shift register stages 11 to IN and respectively latch and output the output data of the shift register stages 11 to IN in accordance with the latch pulse LP.
1 to 2N, and each of the latch circuits 21 to 2N of this latch part 2 is provided correspondingly to the clock pulse CK o for decoding.
Pulse PW1 with a pulse width corresponding to output data of ~2N
A decoder section 3 includes a plurality of decoders 31 to 3N that respectively output .about.PWN, and a reference voltage VR whose voltage changes over time according to a reference voltage clock pulse CKR for each horizontal scanning period. It is provided corresponding to the reference voltage generating circuit 4 to be generated and each decoder of the decoder section 3, and the reference voltage VR is applied only for the period of the pulse width of the pulses PWl to PWN output from each of these decoders 31 to 3N. A plurality of switch circuits 81 to SN that output correspondingly, a plurality of capacitors C1 to CN for sample and hold that respectively hold the output voltages of these switch circuits Sl to SN, and a holding voltage of each of these capacitors. The configuration includes a plurality of output buffer amplifiers A1 to AN that respectively amplify and output.

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing chart of signals of various parts for explaining the operation of this embodiment.

The digital image data DT is transferred to the shift register section 1 by a shift clock pulse CKs during one horizontal scanning period.
After being transferred in each of the shift register stages 11 to IN, this data is held in each latch circuit 21 to 2N by a latch pulse LP for one horizontal scanning period following the latch.

Each latched data is processed by a decoding clock pulse CK o by each corresponding decoder 31 to 3N.
Accordingly, the maximum pulse width is slightly shorter than one horizontal scanning period, and the pulses are output as pulse width modulated pulses PW, .about.PWN having pulse widths corresponding to the respective data.

On the other hand, the reference voltage generating circuit 4 generates a reference voltage VR whose voltage gradually increases in a stepwise manner with time within one horizontal scanning period using a reference voltage chronobulse CKR, and this reference voltage VR It is applied to the input terminal of each switch circuit 81 to SN.

The switch circuits 81 to SN close the switches only when the pulse width modulated pulses PWI to PWN by the decodes 31 to 3N are at a high level, and a reference voltage at a level corresponding to the pulse width is held in the capacitors 01 to CN. It is amplified and outputted by the output buffer amplifiers A1 to AN.

Each output voltage Vo1-V of the output buffer amplifier A1-AN
oN is applied to each liquid crystal cell of the liquid crystal panel, and the liquid crystal panel is driven.

Usually, each liquid crystal cell of a liquid crystal panel is equipped with a sampling transistor, and by turning on this transistor just before the end of one horizontal scanning period, the output voltage V is completely determined. Each liquid crystal cell can be driven with 1 to VON.

In this way, since all of the output voltages VH to VON are sampled simultaneously, there is no need to use a D-A converter with a fast settling time as in the prior art.

The reference voltage VR in the reference voltage circuit 4 may be generated based on external data, or may be generated internally and generated based on this data. This is an example in which a ROM 41 is provided that stores data corresponding to the reference voltage VR, and the reference voltage VR is generated by reading the data from the ROM 41.

In either case, it is possible to generate the reference voltage (8) that matches the transmittance characteristics of the liquid crystal panel.

〔Effect of the invention〕

As explained above, the present invention converts digital image data within one horizontal scanning period and each liquid crystal cell into pulses having a pulse width corresponding to each digital image data,
By using a configuration in which a sample-and-hold capacitor holds a reference voltage that changes over time due to these pulses, a fast settling time is required, which is difficult to achieve. This has the effect of reducing power consumption and being able to accommodate liquid crystal panels with different characteristics.

[Brief explanation of drawings]

1 and 2 are a block diagram of an embodiment of the present invention and a timing diagram of each part signal for explaining this embodiment, and FIG. 3 is a reference voltage generation diagram of the embodiment shown in FIG. 1. FIGS. 4 and 5 are a block diagram showing a specific example of the circuit, and FIGS. 4 and 5 are respectively a block diagram showing an example of a conventional liquid crystal panel drive circuit and a timing chart of signals of each part for explaining the operation of this example. 1...Shift register section, 2...Latch section, 3...
・Decoder section, 4...Reference voltage generation circuit, 6...D
-A converter, 7...shift register, 11~IN...
・Shift register stage, 21 to 2N...Latch circuit, 3
1 to 3N...Decoder, 41...ROM, 42.-
・Reference voltage output circuit, A, ~AN...output buffer amplifier, C1~CN...capacitor, 81~SN...
switch circuit.

Claims (1)

[Scope of Claims] 1. A plurality of shift register stages are provided corresponding to each liquid crystal cell of one horizontal scanning line of the liquid crystal panel, and input digital image data is sequentially shifted and transferred to each of the shift register stages. is provided with a shift register section for taking in and outputting the digital image data corresponding to each of the liquid crystal cells, and corresponding to each shift register stage of this shift register section, and outputting data of each shift register stage at a predetermined timing. A latch section is provided with a plurality of latch circuits that latch and output data in correspondence with each other, and a latch section is provided corresponding to each latch circuit of this latch section, and a pulse width corresponding to the output data of each of these latch circuits is provided at a predetermined timing. A decoder section including a plurality of decoders that respectively output pulses, a reference voltage generation circuit that generates a reference voltage whose voltage changes over time for each horizontal scanning period, and a corresponding decoder of the decoder section. a plurality of switch circuits that respectively output the reference voltages for a period corresponding to the pulse width of the pulse output from each of these decoders; and a sample that holds the output voltages of each of these switch circuits in a corresponding manner. A liquid crystal panel drive circuit comprising a plurality of holding capacitors and a plurality of output buffer amplifiers that respectively amplify and output the holding voltage of each of these capacitors. 2. The reference voltage generation circuit is provided with a storage section that stores data corresponding to a reference voltage whose voltage changes over time during one horizontal scanning period, and the data in this storage section is read out to generate the reference voltage for each horizontal scanning period. Claim 1 that causes
The liquid crystal panel drive circuit described.