JPH03214231A - Dynamic pla device - Google Patents

Abstract

PURPOSE:To secure the sampling time by an amount equal to 1.5 clocks by providing a mask control circuit to input a precharging clock and a mask signal and masking the precharge operation by an extent equal to one cycle. CONSTITUTION:The contents of a register 1 are held as they are until the sampling operation of a programmable logic array PLA part is through, i.e., until an output strobe signal becomes once active and then turned inactive. Meanwhile the precharging operation is carried out for a period, the inverse of phi1 when no precharge mask signal is transmitted. The precharge mask signal kept an an active low level, i.e., a waveform obtained at a point (a) is turned into that of a point (b) after passing through a half clock delay circuit 7. Therefore an output waveform that secures an AND between the precharge mask signal and a precharging clock phi1 is turned into a waveform of a point (c). Thus, a high level period by 1.5 clocks of the waveform of the point (c) is secured as the sampling time of the part 3 after the input data is decided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a dynamic PLA device for integrated circuits, and in particular has registers for holding data at input and output, and performs precharging and sampling in synchronization with a dynamic clock. The present invention relates to a dynamic PLA device that performs dynamic PLA.

[Conventional technology]

A conventional dynamic type PLA (programmable logic array) device is precharged in advance using a clock and performs sampling at the next timing. Generally, precharging is performed in half a clock cycle, and the remaining half clock time is allocated to the calculation time of the PLA device.

In recent years, central processing units have tended to have higher clock frequencies, more complex instructions, and an increased number of data bits to process in order to achieve high-speed processing.

FIG. 4 is a circuit diagram of a Dynamigo PLA device showing an example of such a conventional device.

As shown in FIG. 4, the conventional PLA device has a first register 1 which temporarily latches the data input of 1l12, and an AND gate 2 which takes the logical product of the output of the first register 1 and the output of the first register φ1. , a PLA unit 3 which inputs the output of the AND gate 2 and relays it with the tarlock TI, a second register 4 which temporarily latches the output of the ni of the PLA unit 3, and an input strobe signal and a clock φ1. and an AND gate 5 for latching the register 2 and 4 using the output strobe signal and the clock φ2.

Such a dynamic PLA device performs precharging with a clock φ1 and discharges with the next clock φ2. That is, the input data is P
Before the LA section 3, the signal is latched in the register 1 by the AND gate of the clock φ1 and the strobe signal, and the signal is ANDed with the precharge signal φ1 and input to the PLA section 3. Ru. In addition to this signal, a negative logic precharge signal φ1 is input to the PLA section 3, and the output of the PLA section 3 is the sampling clock φ.
2 and the output strobe signal by an AND gate 5 and is latched into a register 4.

[Problem to be solved by the invention]

The conventional dynamic PLA device described above uses a high-frequency tarock with a large number of input/output signals and product terms, performs precharging in half a clock, and performs sampling in the next half clock, resulting in high speed. The drawback is that it becomes very difficult to design large-scale circuits.

Generally, if the circuit type of the PLA device is the same, the sampling speed is determined by the number of input/output signals and the number of product terms. The problem here is that if you increase the clock frequency,
As the speed of large-scale PLA equipment becomes more demanding, sampling time can be gained by preparing a special frequency-divided tarok, but the timing must also be delayed for small-scale PLA equipment. Another possible method is to use a fast clock and a frequency-divided clock, but this method has the disadvantage of requiring two to four additional clocks to be laid out on the integrated circuit, which lowers the degree of integration.

An object of the present invention is to provide a dynamic PLA device that can mask precharge as necessary to gain sampling time for such large-scale devices, and that facilitates the design of high-speed and large-scale circuits. It is about providing.

[Means to solve the problem]

The dynamic PLA device of the present invention includes m sets of first registers that temporarily latch m pieces of input data using an input strobe signal, and n sets of first registers that temporarily latch n pieces of output data using an output strobe signal. comprising a second register and a PLA section that supplies m outputs of the first register to the input via gate means and supplies the n outputs to the input of the second register; A dynamic PLA device that requires precharging using a clock includes: a mask control circuit that masks a precharging clock using a mask signal; and m AND gates that receive the output of the control circuit and the output of the first register. The output of the AND gate is used as an input signal of the PLA section, and the output of the mask control circuit is used as a precharge signal of the PLA section.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a dynamic PL showing a first embodiment of the present invention.
It is a circuit diagram of A device.

As shown in FIG. 1, in this embodiment, the first register 1 temporarily latches m pieces of input data, the AND of the m pieces of output of the first register 1, and the precharge signal C. m AND gates 2 and these m AND gates 2
A PLA section (programmable logic array section) 3 which inputs the output of and converts the logic under the control of the precharge signal C, and a second register which temporarily latches 0 outputs of this PLA section 3. 4, an AND gate 9 for ANDing the input strobe signal and clock φ1 and latching the first register 1, and an AND gate 9 for ANDing the output strobe signal and clock φ2 and latching the second register 4. It has a mask control circuit 6 consisting of an AND gate 5, an NA and ND gate 8 for masking the precharge clock φ1, and a delay circuit 7 for delaying the mask signal by half a clock by the clock φ2. That is, in this embodiment, when valid data is given, the precharge clock φ1 is activated by the mask signal.
In particular, the mask control circuit 6 performs NAND logic between the output of the delay circuit 7 and the clock φ1 to provide a precharge signal and the input of the PLA section 3. Creates an enable signal for

FIG. 2 is a timing chart of various signals and circuit outputs shown in FIG. 1.

As shown in FIG. 2, the waveform at point a, that is, the mask signal, is delayed by half a clock in the delay circuit 7, and the waveform at point b is obtained. As a result, a clocked waveform at point C is obtained.

Next, the operation of the dynamic PLA device described above will be explained with reference to FIGS. 1 and 2.

First, when a valid value is given to the data input, a lobe signal to input 1 becomes active for latching data into first register 1. That is, the signal obtained by ANDing the clock φl with the AND gate 9 becomes the strobe signal of the first register 1. The contents of this register 1 are:
It is necessary to hold it until the sampling of the PLA unit 3 is completed, that is, until the output strobe signal becomes active once and then becomes inactive.

On the other hand, precharging is performed for a period of 4yl during a period in which a precharge mask signal is not output. The active low precharge mask signal, that is, the waveform at point a in Figure 2, has a half clock delay.
After passing through the circuit 7, the waveform becomes the point shown in FIG. As can be seen from the waveform of FIG. 2, this precharge mask signal may be a signal obtained by inverting the input strobe and delaying it by half a clock. The output waveform obtained by NANDing this signal and the precharge clock φl becomes the waveform at point C in FIG. Looking at this waveform, the precharge clock is masked by one cycle by the precharge mask signal. As a result, after the input data is determined, a high level period of 1.5 clocks of the waveform at point C is secured as the sampling time of the PLA section 3.

The dynamic PLA device of this embodiment has one cycle every two cycles.
sampling is possible. Although it appears that the performance is degraded because sampling cannot be performed every cycle, -i-like PLA does not necessarily perform sampling every cycle, and moreover, a large-scale PLA is used. Considering that this makes it difficult to increase the overall clock frequency of the integrated circuit, sampling once every two cycles does not impair the performance of the integrated circuit.

FIG. 3 shows a dynamic PL showing a second embodiment of the present invention.
It is a circuit diagram of A device.

As shown in FIG. 3, this embodiment differs from the first embodiment described above in that an inverter 10 is added. That is, while the first embodiment uses a PLA device with a negative logic precharge input, this embodiment shows a PLA device with a positive logic precharge input.

〔Effect of the invention〕

As explained above, the dynamic PLA device of the present invention is provided with a mask control circuit that inputs a clock for precharging and a mask signal, and by masking the precharging by one cycle, the sampling time is reduced by 1.570 cycles. This has the effect of ensuring sufficient sampling time even when operating integrated circuits at high frequencies without having to supply a divided clock. It has the effect of making circuit design easier9

[Brief explanation of drawings]

FIG. 1 shows a dynamic PL showing a first embodiment of the present invention.
FIG. 2 is a timing diagram of various signals and circuit outputs shown in FIG. 1, FIG. 3 is a circuit diagram of a dynamic PLA device showing the second embodiment of the present invention, and FIG. 4 is a circuit diagram of the device A. FIG. 1 is a circuit diagram of a dynamic PLA device showing an example of the conventional technology. 1... first register (input data register), 2.
5.9...AND gate, 3...Programmable
Logic array section (PLA section), 4... Second register (output data register), 6... Mask control circuit, 7... Delay circuit, 8... NAND gate, 1
0...Inverter.

Claims (1)

[Claims] m sets of first registers for temporarily latching m pieces of input data in response to an input strobe signal; n sets of second registers for temporarily latching n pieces of output data in accordance with an output strobe signal; A PLA section that supplies m outputs of one register to the input via gate means and supplies the n outputs to the input of the second register, and requires precharging by a clock. The PLA device includes a mask control circuit that masks a precharge clock with a mask signal, and a mask control circuit that receives an output of the control circuit and an output of the first register as inputs.
AND gate, wherein the output of the AND gate is used as an input signal to the PLA section, and the output of the mask control circuit is used as a precharge signal for the PLA section.