JPH03214241A - Test method for microprocessor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Industry-1-] The present invention relates to a testing method for microprocessors.

[Conventional technology]

In recent years, with advances in semiconductor circuit integration technology, microprocessors have become more sophisticated and highly integrated, but their testing methods have become increasingly complex, and simplifying them is an important issue. The current situation is that

In the conventional FFI microprocessor testing method, a dedicated test circuit is provided, and the test is performed by reading out the internal state of the microprocessor using this test circuit.

FIG. 2 shows the configuration of an apparatus used in a conventional microprocessor testing method using the scan path method. In this figure, (II)(+2)...(In) are the first to nth registers having two systems of input, a selection control input for selecting these two systems of input, and one system of output;
(20) is a combinational circuit.

(21)(22)...(2n) is a combinational circuit (20
), the internal states of the microprocessor given by the corresponding registers (11), (12)...(1
Connect the signal line (31) to one of the two input systems of n) (
32)...(3n) converts the internal state of the microprocessor given to each register (II) (12)...(In) from the combinational circuit (20) to the two input systems of the next register. The signal line (40) given to the other side is the signal L (4J) (
42)...(4n) are registers (II) (+
2)...(In) is a selection control input signal line for selecting the input of either the combinational circuit (20) or the output of the previous stage register.

In the above configuration, the internal state of the microprocessor provided by the combinational circuit (20) is stored in the second register (11) through the signal line (2I), and is stored in the second register (!2) through the signal line (32). stored in
Thereafter, they are sequentially shifted to the next register in the same way,
The nth register (1n) at the final stage through the signal line (3n)
After being stored in the memory, it is read out to the outside through a signal line (40).

As mentioned in 1-1, in the scanvase method, the shift register (
A dedicated test circuit consisting of 11) to (In) is provided, and the internal state of the microprocessor is tested by each register (II).
) to (1n), and sequentially registers (11) to (I
n) The test was carried out by reading by software.

[Problem to be solved by the invention]

However, if a dedicated test circuit is provided as in the conventional example described in - and a test is performed by reading out the internal state of the microprocessor, then registers (II) to (
There is a problem in that the amount of hardware increases, such as the need for In).

The present invention was made in view of these problems, and
One purpose of this invention is to provide a microprocessor testing method that can suppress the increase in hardware, evaluate the internal state of a microprocessor, and perform tests efficiently.

[Means to solve the problem]

In order to achieve objective L1 in item 1-8, the method of the present invention includes: an interrupt detection means; a priority assignment means for assigning a priority to the interrupt detected by the interrupt detection means; an interrupt processing control means configured with an address generation means for generating a specific address indicating the start of interrupt processing according to the content of the attached interrupt, and a test interrupt generation means, the interrupt generation means 5, the internal information of the microprocessor is evaluated, and as a result of evaluating this internal information, the interrupt generating means generates an interrupt, and the address generating means generates an interrupt according to the contents of the interrupt prioritized by the priority assigning means. This method is characterized by testing the internal state of a microprocessor by evaluating a specific address.

[For production]

According to the present invention, internal information of the microprocessor is given to the test interrupt generating means, and as a result of evaluating this internal information, the interrupt generation stage 1 generates an interrupt. Next, in response to the generated interrupt, the address generating means generates a specific address according to the content of the interrupt prioritized by the priority assigning means.

Therefore, it is possible to test the internal state of the microprocessor by evaluating the generated specific address.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the configuration of the apparatus used in this embodiment. (51) (52)... (5n) is an interrupt detection means, (GO) is an interrupt detection means (51
) (52)...Priority assignment means (5n) assigns a priority to the detected interrupt, and (61) performs interrupt processing according to the content of the interrupt prioritized by the priority assignment means (GO). This is address generation means that generates a specific address indicating the start.

Further, (71072)...(7n) are signal lines for notifying the priority allocation means (60) of the interrupts detected by the interrupt detection means (51052)...(5n), respectively. The means (60) assigns priorities to the interrupts to be processed from among the notified interrupts. (80) is the priority assignment means (
This is a signal line that notifies the address generation stage (61) of the contents of the interrupt to be processed whose priority has been given in step 60), and the address generation stage (61) is responsible for notifying the notified interrupt to be processed. A specific address indicating the start of interrupt processing is determined according to the contents of the address. (81) is address generation 19
Read out the address created in step (old) to the outside
``It's the J line.

(82) is an interrupt processing control means conventionally provided in a microprocessor, and in this embodiment, 1
) 1f interrupt detection means (51H52) = 15n), priority allocation means (60), and address generation means (6
1). (83) is a test interrupt generation means, and (84) is a test interrupt setting stage (83) that is notified of the state #X transition information of PLA in the microprocessor (;, j "J' (85) is the test interrupt generation I] Ding stage (83) evaluates the information on the state transition of the PLA in the microprocessor, and assigns the interrupt generation /l a priority level to the first stage (6
0) is the Shinkyu Line.

In the test method according to this embodiment, which is carried out by preparing each of the means listed below, when the PLA in the microprocessor enters a certain state, the test interrupt generating means (83) detects this and interrupts the signal line. The occurrence of the interrupt is notified to the priority allocation means (6o) through (85). Next, the priority assignment means (6o) assigns the priority of the interrupt contents and notifies the address generation means (61) of the result through the signal zz line (80). Then, the address generating means (6r) generates a specific address according to the interrupt contents and outputs it to the outside from the I word line (81).

Therefore, by evaluating the specific address output from the Il'l code line (81), the state of the PLA within the microprocessor can be tested. In history, information on the state transition of the PLA in the microprocessor is sent to the Schiff line (84) by A in the microprocessor.
Even if it is replaced with other information in the microprocessor, such as LU operation result information, cache hit or miss information, the specific address to be output from the Jinno line (81) to the outside can be replaced with: It goes without saying that the internal state of the microprocessor can be tested by checking the value.

〔Effect of the invention〕

1. As explained above, when the microprocessor testing method of the present invention is used, an interrupt detection means, a priority assignment means for assigning a priority to the interrupt detected by the interrupt detection means, and a priority assignment means for assigning a priority to the interrupt detected by the interrupt detection means, A microprocessor interrupt processing control means comprising an address generation means that generates a specific address indicating the start of interrupt processing according to the contents of the interrupt prioritized by the allocation means, and an evaluation of internal information of the microprocessor for testing purposes. An interrupt generation r' stage that generates an interrupt based on the result is prepared, and a test is performed using one of these stages. Since a specific address is generated from the address generation means according to the contents of the interrupt prioritized in the priority allocation stage in response to an interrupt, by evaluating this specific address, In addition to suppressing the increase in hardware, the internal state of the microprocessor can be evaluated and the microprocessor can be tested efficiently.As a result, the reliability of the microprocessor or the system using the microprocessor can be improved. This resulted in an excellent effect in that it was possible to direct the

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a test device used in an embodiment of the method of the present invention, and FIG. 2 is a block diagram showing the configuration of a device used in a conventional microprocessor test method using the scan path method. FIG. (51H52)...(5n)...Interrupt detection means, (Go)...Priority assignment P stage, (Gl)...
- Address generation means, (82)...Interrupt processing control means, (83)...Test interrupt generation means.

Claims (1)

[Claims] An interrupt detection means, a priority assignment means for assigning a priority to the interrupt detected by the interrupt detection means, and a specification indicating the start of interrupt processing according to the content of the interrupt prioritized by the priority assignment means. An interrupt processing control means constituted by an address generation means for generating the address of The interrupt generating means generates an interrupt and tests the internal state of the microprocessor by evaluating a specific address generated by the address generating means according to the contents of the interrupt prioritized by the priority assigning means. Characteristics of microprocessor testing methods.