JPH03214251A - Information processor - Google Patents

Abstract

PURPOSE:To improve the data transfer efficiency of a bus by masking a refresh request produced during the transfer of a data block carried out with a direct memory access DMA, counting the frequency of unexecuted refresh requests produced in accordance with masking of the preceding refresh request, and executing an unexecuted refresh cylce after transfer of the data block. CONSTITUTION:When a refresh request signal 12 is produced while a transfer cycle 22 is carried out for a data block with a DMA, the signal 12 is not inputted to a bus arbitration circuit 3 and inputted to a refresh request mask circuit 1 and an unexecuted refresh request counter 2. The signal 12 is masked by a data block transfer request signal 11 of the DMA while the data block is transferred with the DMA. Then the signal 12 counts up the counter 2. Therefore the grant for the long-term use of the bus is never interrupted despite a refresh request produced during the transfer of the data block carried out with the DMA. Thus it is possible to prevent the deterioration of the data transfer efficiency of the bus.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an information processing device, and particularly to an information processing device capable of performing block transfer of data by direct memory access (hereinafter referred to as DMA). .

(Prior Art) Conventionally, in an information processing device capable of performing block transfer of data using DMA, a bus is occupied by the block transfer of data using DMA.

Furthermore, even when the bus is occupied, if a memory refresh request is generated, the occupation of the bus by DMA transfer is relinquished, and bus arbitration is performed in which the memory refresh cycle is executed preferentially.

An example of such an information processing device is shown in FIG. Further, a signal timing diagram of this information processing device is shown in FIG.

A block transfer of data using DMA is executed, and the DMA
A data block transfer request signal 41 is sent to the bus arbitration circuit 31. The bus arbitration circuit 31 permits long-term use of the lotus when a data block transfer request 41 by DMA occurs. Then, a bus cycle 51a executed at the start of data block transfer by DMA occurs, and a data block transfer cycle 52 by DMA occurs.
a is executed.

When a refresh request occurs during this DMA block transfer of data, a refresh request signal 42 is sent to the bus arbitration circuit 31. The refresh request signal 42 is input to the bus arbitration circuit 31 without being masked by the data block transfer request signal 41 by DMA. The bus arbitration circuit 31 sends an instruction signal 43 to the refresh cycle control circuit 32 instructing it to suspend permission for long-term use of the lotus and to perform refresh once. As a result, the refresh cycle control circuit 32 sends out a refresh signal 44. When the refresh signal 44 is sent out, the DMA data block transfer cycle 52a is interrupted by a refresh request, and a refresh cycle 54 is inserted, as shown in FIG. Therefore, between the interruption of data block transfer by DMA and the restart of data block transfer by DMA, there is a bus cycle 53a executed at the end of data block transfer by DMA and a data block by DMA. A bus cycle 51b occurs which is executed at the beginning of the transfer.

When the bus cycle 51b occurs, the DMA data block transfer cycle 52b is executed again, and the DMA
A hash cycle 53b, which is executed at the end of data block transfer, occurs. When a refresh request occurs after this, a cycle 55 occurs in which refresh is executed only once.

[Problem to be solved by the invention]

In the conventional information processing apparatus described above, data block transfer by DMA is interrupted by execution of a refresh cycle. Therefore, a bus cycle that is executed at the start and end of the DMA block transfer occurs between when the DMA block transfer is interrupted and when the DMA block transfer is restarted.

The bus cycles executed at the start and end of data block transfer by DMA are bus cycles in which no data transfer is actually performed. Therefore, as the number of bus cycles executed at the start and end of data block transfer by DMA increases, the data transfer efficiency of the bus decreases. Therefore, if the DMA data transfer is interrupted by the execution of a refresh cycle, there is a drawback that improvement in bus data transfer efficiency is hindered.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing device that can eliminate such drawbacks and prevent the data transfer efficiency of the bus from decreasing when a refresh cycle is executed.

[Means for Solving the Problems] The present invention provides an information processing device that is capable of performing block transfer of data by direct memory access and sends out a refresh signal when a memory refresh request is made. a refresh request mask unit that masks a memory refresh request signal generated during a block transfer of data by direct memory access; an unexecuted refresh request counter unit that counts the number of memory refresh requests generated during a block transfer of data by direct memory access; a bus arbitration unit that instructs to execute memory refresh cycles consecutively for a number of times equal to “1” added to the number of unexecuted refresh requests counted by the counter unit; and a bus arbitration unit that sends out a refresh signal according to instructions from the bus arbitration unit. The memory refresh cycle control unit is characterized in that the block transfer of data by direct memory access is not interrupted by a memory refresh request, and one unexecuted memory refresh cycle is continuously executed after the block transfer is completed. .

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The information processing apparatus shown in FIG. 1 includes a refresh request mask circuit 1 for masking a memory refresh request signal 12 generated during block transfer of data by DMA;
The unexecuted refresh request counter 2 counts the number of refresh requests that occur during data block transfer by DMA, and the number of unexecuted refresh requests counted by the unexecuted refresh request counter 2 plus "1". A bus arbitration circuit 3 causes refresh cycles to be executed continuously, and a refresh signal 16 is generated by an instruction signal 15 sent from the bus arbitration circuit 3.
The refresh cycle control circuit 4 sends out the refresh cycle control circuit 4.

Next, the operation of this information processing device will be explained with reference to the signal timing diagram of FIG.

A block transfer of data using DMA is executed, and the DMA
A data block transfer request signal 11 is applied to the refresh request mask circuit 1, the unexecuted refresh request counter 2, and the bus arbitration circuit 3. The bus arbitration circuit 3 permits long-term use of the bus when a data block transfer request 11 by DMA occurs. Then, a bus cycle 21 is generated, which is executed at the start of data block transfer by DMA. Subsequently, a data block transfer cycle 22 using DMA is executed.

If a refresh request signal 12 is generated during this period, this refresh request signal 12 is not input to the bus arbitration circuit 3 but is input to the refresh request mask circuit 1 and the unexecuted refresh request counter 2. The refresh request signal 12 is D during data block transfer by DMA.
It is masked by the data block transfer request signal 11 by the MA. Furthermore, the refresh request signal 12 is
The unexecuted refresh counter 2 is counted up.

Therefore, even if a refresh request occurs during data block transfer by DMA, permission for long-term use of the bus is not interrupted.

At the end of the block transfer, a bus cycle 23 occurs, which is executed at the end of the DMA pig block transfer. The refresh request signal 12 which is generated after the completion of a data block transfer by DMA is not masked by the data block transfer request signal 11 by DMA.

For this purpose, the refresh request mask circuit 1 sends a request signal 13 to the lotus arbitration circuit 3. The bus arbitration circuit 3 is D
A refresh continuous execution cycle 24 is executed by a refresh request signal 12 generated when a block of data is not being transferred by the MA. At this time, the hash arbitration circuit 3 sets the number of unexecuted refresh requests to "1" according to the count signal 14 indicating the number of unexecuted refresh requests.
The refresh cycle is executed for the number of times added. The bus arbitration circuit 3 sends an instruction signal 15 to the refresh control circuit 4 to instruct continuous execution of refresh. Refresh cycle control circuit 4 controls refresh signal 16 in accordance with instruction signal 15 instructing continuous execution of this refresh.

Thus, it is clear that block transfer of data using DMA can be performed without being interrupted by execution of a refresh cycle.

〔Effect of the invention〕

As explained above, the present invention masks refresh requests that occur during block transfer of data by DMA, counts the number of unexecuted refresh requests that occur as a result, and stores unexecuted refresh requests after completion of block transfer. By performing consecutive execution refresh cycles, the DM
This prevents block transfer of data by A from being interrupted by execution of refresh. This allows the DMA
The number of bus cycles executed at the start and end of a block transfer of data by
This has the effect that the improvement in bus data transfer efficiency due to block transfer of data by A is not hindered.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a signal timing diagram of the embodiment of FIG. 1, and FIG. 3 is a block diagram showing an example of a conventional information processing device. FIG. 4 is a signal timing diagram of the information processing apparatus of FIG. 3. 1... Refresh request mask circuit 2...
Unexecuted refresh request counter 3...Bus arbitration circuit

Claims (1)

[Claims] (1) In an information processing device that can perform block transfer of data by direct memory access and sends out a refresh signal when a memory refresh request is made, mask the memory refresh request signal generated during block transfer of data by direct memory access. an unexecuted refresh request counter unit that counts the number of memory refresh requests that have occurred during block transfer of data by direct memory access; a bus arbitration unit that instructs to execute memory refresh cycles consecutively for a number of times equal to “1” added to the number of times, and a refresh cycle control unit that sends out a refresh signal according to instructions from the bus arbitration unit; An information processing device characterized in that block transfer of data by memory access is not interrupted by a memory refresh request, and unexecuted memory refresh cycles are continuously executed after block transfer is completed.