JPH03214252A - Microprocessor - Google Patents

Abstract

PURPOSE:To improve the availability of a bus by varying the activation timing of the write/read control signals to a memory and an I/O in accordance with the value stored in a register. CONSTITUTION:A register 2 stores the value that is used for setting a blank period lasting until an I/O control signal is applied at the I/O cycle start. A state generating circuit 3 inputs a clock CLK 5 of a square wave signal, an access request signal 6 which starts a bus cycle, a READY signal 7 serving as an external terminal, and the contents of the register 2, At the same time, the circuit 3 outputs a state S1 signal 8, a state S2 signal 9, and a state SI signal 10 to a bus control circuit 4. The circuit 4 decides the change timings of an address bus 11, a memory, and an I/O control signal 12 based on the signal state of a state signal group. Thus a programmer is not required to consider the insertion of a NOP instruction, etc., in an I/O cycle just by setting the desired value to the register 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor, and particularly to a storage device (
The present invention relates to a microprocessor that performs data transfer with an input/output device (hereinafter referred to as 1710) and an input/output device (hereinafter referred to as 1710).

[Conventional technology]

Conventionally, this type of microprocessor has memory and Ilo
When the bus cycle for accessing is started, control signals such as write and read become active at a certain timing, and data is transferred to and from the memory and Ilo.

[Problem to be solved by the invention]

In the conventional microprocessor described above, the active timing of the control signal in the bus cycle is fixed after a certain period of time from the start of the bus cycle.

However, depending on the type of T10, there are some types in which the next operation cannot be performed immediately after write data transfer, that is, a long write recovery time is required. In such a case, consideration must be given to software so that write operations to Ilo are not continuous. For example, the programmer must insert a NOP (no-operation instruction) when writing to Ilo to avoid consecutive write cycles due to the need for a long write recovery time for I,10. itself will occur.

Furthermore, when the operating frequency of a microprocessor is changed by hardware, there is a drawback that it becomes necessary to increase or decrease the number of dummy instructions (processing M for discontinuous write cycles).

An object of the present invention is to provide a microprocessor that does not require program changes or hardware additions even when using 10, which has a long write recovery time.

[Failure to solve the problem]

The microprocessor of the present invention includes a control circuit that generates a control signal for an external device, a register in which a desired value is set, and an activation timing of the control signal for the control circuit in response to the value of the register. and a state generation circuit that controls the state.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram for explaining a first embodiment of the present invention. As shown in the figure, microprocessor 1
There are a register 2, a state generation circuit 3, and a bus control port li'84 inside. Register 2 stores a value for setting the margin period until the ■/'0 control signal is applied at the start of the I10 cycle. The state generation circuit 3 inputs a square wave signal clock CLK5, an access request signal 6 for starting a bus cycle, an external terminal R, an EADY signal 7, and the contents of the register 2.
State S1 signal8. State S2 signal 9 S date SI
A signal 10 is output to the bus control circuit 4. Bus control port 1?
84 is the address bus 1 depending on the signal state of the state signal group.
1 and memory, 110 determines the change timing of the control signal 12.

The second UA is a state transition diagram showing an example of the operation of the stay 1 to generation circuit 3, which are one of the constituent elements of the present invention. The internal states of the microprocessor 1 are SL, S2 . SI, and each state changes in units of one clock (CLK). Here, the S1 state is a state in which data is supplied to the address bus in I10 cycles, but the I1010 control reliability is not supplied, and the S2 state is a state in which data is supplied to the address bus and I1010 control signals are supplied. The SI state refers to an idling state in which neither address data nor 110 control signals are supplied.

FIG. 3 shows an example of bus cycle operation timing according to an embodiment of the present invention. In the I10 access cycle, the contents of register 2 are set to 1', and S1→S1→S2→S2
An example of the transition is shown.

The operation of one embodiment of the present invention will be explained with reference to the drawings. When the access request signal 6 indicating that there is an I10 cycle after the memory cycle becomes active, the state becomes 81 immediately after the memory cycle ends, and the state S1 signal 8 becomes rl. In this S1 state, address information is output to the address bus 11, and a bus cycle starts. At this time, the data value stored in register 2 sets the period M from when the I10 cycle is activated until the I,10 control signal is supplied. Specifically, if the data value stored in register 2 is "n", the S1 state is set to 'n+1'.
Transition continues to S2 state.

In the S2 state, address information is continued to be output to the address bus 11, and the memory I1010 control signal 2 is made active. Also, in the S2 state, the READY signal 7 is sampled at the rising edge of the clock 5, and if it is "1", the S
It will transition to the 1 state or the SI state, and if r Q 4, it will continue in the S2 state. Further, when transitioning to the S1 state or the SI state, the memory 1010 control signal 2 is made inactive.

By setting a desired value in register 2 as in this embodiment, a period from the start of the I10 cycle to the supply of the I1010 control signal is automatically provided, so that the programmer can This means that there is no need to consider the insertion of NOP instructions.

FIG. 4 is a block diagram for explaining a second embodiment of the present invention. As shown in the figure, microprocessor 1
01 includes an A register 102, a B register 107, a state generation circuit 103, and a bus control port i\8104. The state generation circuit 103 inputs the clock CLK 105 of the method wave signal, the access request signal 106 for starting the bus cycle, the contents of the A register 102, and the contents of the B register 107, and generates the STATE 1-SL signal 1.
08, state S2 signal 109. State SI signal 11
0 to the bus control circuit 104. Bus control circuit 10
4 determines the change timing of the SHUAS 111 and the memory, I, 'O control signals 112 based on the signal states of the state signal group.

In the sixth embodiment, the transition from the S2 state is recorded in the B register]0
7, which has the advantage of reducing the number of terminals compared to the first embodiment.

〔Effect of the invention〕

As described above, according to the present invention, the timing at which the control signal for writing to and reading from the memory or Ilo becomes active can be varied depending on the value stored in the register.

This will require longer recovery time■／○
When incorporating software into a system, software designers do not need to program dummy instructions in consideration of hardware limitations, and can design for optimal bus cycle timing, increasing bus usage efficiency. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the embodiment of the present invention, FIG. 2 is a state transition diagram showing the operation of the state generation circuit, which is one of the constituent elements of the present invention, and FIG. FIG. 4 is a timing diagram showing an example of the bus cycle operation of the first embodiment of the present invention. FIG. 4 is a block diagram for explaining the second embodiment of the present invention. 1.101...Microprocessor, 2.102107
・Register, 3.103... State generation circuit, 4,
104...Bus control circuit, 5.105...Clock signal, 6,106...Access request signal, 7...External R
EADY signal, 8,108...S1 signal, 9.109
...S2 signal, 10,110...SI signal, 111
], 1...Address bus, 12.112...Memory, I10 control signal.

Claims (1)

[Claims] a control circuit that generates a control signal to an external device;
A microprocessor comprising: a register in which a desired value is set; and a state generation circuit that controls activation timing of the control signal for the control circuit in response to the value of the register.