JPH0498558A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve the control efficiency of an external memory, an external I/O, etc., by adjusting the control time width of the bus cycle of a microcomputer for integral fraction of CPU operating cycle time. CONSTITUTION:A clock source signal CF of double as high as the frequency of a CPU operating clock is inputted to a clock unit CKU 4 from an external clock frequency source. The signal CF is shaped into a desired clock waveform by a clock generator CG 41. The frequency of the shaped signal CF is halved by a half frequency divider 42, i.e., the cycle of the signal CF is doubled. This signal CF is supplied as an operating clock of an EXU 1. Furthermore the output signals of the divider 42 are partly inputted to a double multiplier 43 with the double frequency, i.e., the half frequency. These multiplied signals are supplied as the operating clocks of a BCU 2 and an interface 3. Therefore the BCU 2 works in a half unit of the CPU operating clock. At the same time, the interface 3 holds the data in a half clock unit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and particularly to a synchronous bus control microcomputer.

[Conventional technology]

In conventional microcomputers, the operations of the bus control unit (BCU) that controls external memory and external I10, such as fetching instructions and reading/writing data, are as follows:
The unit of operation was one CPU clock, and it was completely synchronized with the internal processing unit.

Therefore, external memory that is slower than the CPU bus cycle,
In order to control the external I10, a weight was inserted in the single-lock sheep position and the control time was extended.

An example of a conventional microcomputer is shown in FIG.

In FIG. 6, the conventional microcomputer is comprised of an internal arithmetic unit (EXU) 1, a bus control unit (BCU) 2, and a clock unit (CKU) 4.

EXUl further includes an arithmetic operation unit (ALU) 11
, a general-purpose register 12 , and an instruction decode unit (IDU) 13 .

BCU2 further includes a brief fetch pointer (PPP)
21 and a brief fetch queue (QUEUE) 22.

CKU4 further includes a clock generator (CG) 41.
and a frequency divider circuit (1/2DIV) 42.

Next, the operation of a conventional microcomputer will be explained.

First, the PPP 21 generates the address of the instruction to be executed.

Second, the data IO of the external memory indicated by the PPP 21 is read out, and the command data is stored in the QUEUE 22 for one day.

Thirdly, in EXU1, when the execution of the previous command is completed, the command data stored in the IDU 13 is sent from the QUEUE 22.

The IDU 13 interprets the instruction data, and as a result,
For example, execute the following command:

First, data is transferred from the external memory and external ■/○ to the general-purpose register 12 using an IO multiplication signal.

Second, the data is transferred from the general-purpose register 12 to the external memory, external I10, using an IO multiplication signal.

Third, an operation is executed in ALUII using the general-purpose register 12, external memory, and external I10 as source data, and the result of the operation is written to either the general-purpose register 12, external memory, or external I10.

The clock unit (CKU) 4 receives a clock source signal CF that is twice the operating clock frequency of the CPU from an external clock frequency source, and generates a clock generator (CG) 4.
1, the clock waveform is shaped into the required clock waveform.

Next, the frequency of the shaped clock source signal is halved by the frequency divider 42, that is, the period is doubled, and the EXU1
and BCU2 as an operating clock.

[Problem to be solved by the invention]

In the conventional microcomputer described above, both the internal arithmetic unit and the bus control unit operate in units of one clock of the CPU.

Therefore, in order to control an external memory or an external I10 that is slower than the CPU's bus cycle, there is a drawback that it is necessary to insert a wait in units of one CPU clock and extend the access time.

For example, if the CPU bus cycle is 2 clocks and the access time is slightly insufficient with no wait, if 1 wait is inserted, the access time becomes 3 clocks. The bus control time is 1.5 times that of the case without waits, resulting in a disadvantage that the processing time is significantly increased.

The increase in bus control time naturally has the disadvantage of increasing the overall CPU processing time.

[Means to solve the problem]

The microcomputer of the present invention includes a CPU clock;
The bus control unit has a clock supply circuit that supplies a one-cycle clock whose cycle is an integer fraction of the CPU clock cycle.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to FIG. 1, the microcomputer of the present invention has an internal arithmetic unit (EXU) 1 similar to the conventional example described above.
, hash control unit) (BCU) 2, clock unit (CKU) 4, and interface 3.
It consists of

EXUl further includes an arithmetic operation unit (ALU) 11
, a general-purpose register 12, and an instruction decode unit (IDU) 1B.

BCU2 further includes a brief fetch pointer (PFP)
21, and a brief fetch queue (QUEUE>22).

CKU4 further includes a clock generator (CG) 41.
In addition to the frequency divider circuit (1/2DIV) 42 and the frequency divider circuit (1/2DIV) 42, it also includes a doubler 43.

Here, the difference from the conventional example described above is that the BCU2 is
It is configured to operate in units of 1/2 of the U operation clock.

The interface 3 is composed of a well-known latch circuit that holds data in 1/2 clock units.

Next, the operation of this embodiment will be explained.

The clock unit (CKU) 4 receives a clock source signal CF twice the operating clock frequency of the CPU from an external clock frequency source, and outputs a clock generator (CG>4).
1 to shape the clock waveform into the required clock waveform.

Next, the frequency of the shaped clock source signal is halved by the frequency divider 42, that is, the period is doubled, and the EXUI
Supplied as the operating clock.

Further, a part of the output signal of the frequency divider 42 is transmitted to the frequency divider 42.
3 and double its frequency, i.e., its period by 1/
2, it is supplied to each of the BCU 2 and interface 3 as an operation clock.

FIG. 2 is a time chart of the bus cycle of the circuit of this embodiment shown in FIG.

As shown in Figure 2, for the CPU operation clock of A,
In the case of a microcomputer with a two-clock basic bus cycle, the basic bus operation is in a no-wait state as shown in B.

If there is insufficient access time to the external memory or external I10, a wait is inserted.

The unit of weight insertion is based on the CPU operating clock.
This can be done in 1/2 clock units.

C indicates the case of 1/2 weight insertion, and D indicates the case of 1 weight insertion.

FIG. 3 is a time chart of the CPU operation of this embodiment shown in FIG.

A indicates the CPU operating clock, B indicates the operating timing of EXUl, C indicates the operating timing when synchronized with the BCU clock, and D indicates the operating timing when not synchronized with the ECU clock.

When fetching an instruction, the brief fetch pointer (
PPP) 21 generates the address of the instruction to be executed.

Next, the three or more operations of reading data 0 at the address of the external memory indicated by the PPP 21 and temporarily storing the command data in the QUEUE 22 are completed within the BCU 2, so 1/2
It can be executed in clock units.

However, when executing data transfer between ALU II or general-purpose register 12 and external memory or external I10, BC
Since the operation spans between U2 and EXUl, synchronization must be considered.

Since EXUI operates in CPU clock units, data exchange between EXUl and BCU2 is necessarily performed by CPU.
Must be done on the trailing edge of the U-operation clock.

On the other hand, since the BCU2 operates in 1/2 clock units, the data output does not necessarily coincide with the trailing edge of the CPU operating clock, so there may be cases where data cannot be exchanged between the EXU1 and the BCU2.

For example, data IO from external memory is sent to BCU2.
When transferring from the EXUI general register 12, the third
As shown in C in the figure, when the trailing edge of the bus cycle matches the trailing edge of the CPU clock, there is no problem from BCU2 to E.
It is possible to send and receive data to XUI. However, as shown at D in FIG. 3, if it is at the trailing edge of the hash cycle or in the middle of the CPU clock, a time gap of 1/2 clock occurs in data exchange.

In order to hold data during this blank time, in this embodiment, interface 3 is inserted between EXIJl and BCU2.

As described above, the interface 3 is composed of a latch circuit that holds data in units of 1/'t, clocks.

Therefore, data transfer from BCU2 to EXUl is as follows:
Through the interface 3, the execution is completely synchronous with a maximum delay of 1/2 clock.

Conversely, when transferring data from EXUl to BCU2, if BCU2 is executing another instruction, 1/
Since it is necessary to hold data for a period from 2 clocks to several clocks, this is done using ink face 3.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a block diagram of a circuit showing a second embodiment of the present invention.

The difference from the conventional example is that, like the first example, it is configured to operate in units of BCU2 or 1/2 of the CPU operating clock.

The difference from the first embodiment is that there is no interface 3, and further, the clock cycle of the BCU2, that is, the bus cycle, is controlled by the CPU control signal SWC in the CKU4 in units of 1 CPU clock or 1/2 clock. A switching circuit (SW) 44 for switching to either one is added.

Furthermore, in this embodiment, the bus cycle is controlled in units of 1/2 clock during instruction briftches and data writes, but is controlled in units of 1 clock during data reads. This change in bus cycle control unit is automatically performed within the CPLI.

Next, the operation of this embodiment will be explained.

FIG. 5 is a lotus cycle diagram of this embodiment.

A is the CPU operation clock, B, C, and D are external control signals for no wait, 1/2 wait, and 1 wait, respectively, and E is the EXU operation timing.

As in the first embodiment, there is no problem in performing a brief fetch of an instruction whose operation is limited within the BCU 2 in units of a bus cycle or 1/2 clock.

In addition, in a data write execution instruction such as an example of transferring data from the general-purpose register 12 to external memory, EXU
Data is transferred from BCU2 to BCU2. In this case, EX
While Ul operates in units of 1 clock, BCU2 operates in units of 1/2 clock, so there is no problem because synchronization will not be lost.

However, in the case of a memory read, control of the data bus shifts from the BCU 2, which is controlled in units of 1/2 clock, to the EXUI, which is controlled in units of 1 clock.

Since the EXUI must receive data on the trailing edge of the clock, as shown in Figure 5E, if the bus cycle ends in the middle of the clock, as shown in Figure 5C, the BCU
It becomes impossible to send and receive data from 2 to EXUl.

Therefore, in this embodiment, as described above, the bus cycle is controlled in 1/2 clock units during instruction briftches and data writes, but is controlled in 1 clock units when data is read. This change in bus cycle control unit is automatically performed within the CPU.

Next, an example of the flow in the case of memory read will be described.

First, in step 1, a memory read instruction is generated from EXU1 to BCU2.

In step 2, EXUl starts reading memory.

In step 3, it is determined whether the BCU2 cycle has ended in the middle of the EXUI cycle.

If YES, step 4 is reached, in which the clock period is switched in units of one clock, thereby extending the BCU2 cycle by 1/2 clock.

If no, proceed to step 5.

At step 5, the BCU2 cycle ends and hands over the data to EXUl.

Therefore, the user must remove all external memory, external I10
Waits are set in 1/2 clock units.

Although the present invention has been described in detail above, the present invention is not limited to the above-mentioned embodiments and can be modified in various ways.

For example, in the embodiment, the bus cycle is controlled by the CPU.
It goes without saying that it may be set to 1/2 of the operating clock, or may be an integral number of the CPU operating clock, without departing from the spirit of the present invention.

[Effects of the Invention] As explained above, the present invention adjusts the control time width of the bus cycle of the microcomputer in units of one integer of the operating cycle of the CPU.
This has the effect that lo etc. can be controlled efficiently.

In addition, the external control time for the entire system is reduced, so
The time when CPU operation is affected by the bus is reduced, and the C
It is possible to operate with the original performance of the PU, which has the effect of shortening the system processing time.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a circuit showing an embodiment of the present invention, Fig. 2 is a bus cycle operation time chart of the circuit shown in Fig. 1, and Fig. 3 is an operation time of the circuit shown in Fig. 1. 4 is a block diagram of a circuit showing the second embodiment of the present invention, FIG. 5 is a bus cycle operation time chart of the circuit shown in FIG. 4, and FIG. 6 is an example of a conventional microcomputer. FIG. 2 is a block diagram of a circuit illustrating. 1... Internal processing unit (EXU), 2... Bus control unit (BCU), 3... Interface, 4... Clock unit (CKU), 11...
Arithmetic unit (ALU), 12... general-purpose registers,
13... Instruction decoding unit (ID
U), 21...Briefetch pointer (PFP), 2
2...Briefetch queue (QUEUE) 41...
Clock generator (CG), 42...-frequency divider, 4
3...Double multiplier, 44...Switching circuit (SW).

Claims (1)

[Scope of Claims] 1. A clock supply circuit that supplies a CPU clock and a one-cycle clock whose cycle is a one-integer fraction of the cycle of the CPU clock for operating the bus control unit. microcomputer. 2. A data buffer circuit that operates with the integer/one cycle clock for data transfer between the CPU and the bus control unit and holds data in units of the integer/one clock cycle. The microcomputer according to claim 1, characterized in that: 3. means for comparing the trailing edge of the operating cycle of the bus control unit with the trailing edge of the operating cycle of the CPU; and when the trailing edge of the bus control unit's operating cycle is before the trailing edge of the operating cycle of the CPU; 2. The microcomputer according to claim 1, further comprising clock switching means for switching the clock of the microcomputer to the CPU clock.