JPH03214664A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a capacity between an element and a substrate so as to attain a high performance and simultaneously to enable reliable isolation of the element by a method wherein a buried layer is formed in a low-concentration semiconductor substrate, the surface concentration of the semiconductor substrate is made high thereafter, an epitaxial layer is formed and then an element isolation region is formed. CONSTITUTION:After a buried layer 2 of a second conductivity type is formed in a prescribed area of one main surface of a low-concentration semiconductor substrate 1 of a first conductivity type, impurities of the first conductivity type are introduced into the whole of the one main surface of the semiconductor substrate, so that the surface concentration of the semiconductor substrate 1 be made high. After an epitaxial layer of the second conductivity type is formed on the one main surface of the semiconductor substrate 1, an insulating layer 5 and a region 10 of the first conductivity type extending to the semiconductor substrate 1 and located just below the insulating layer 5 are formed, so as to form an element isolation region 11. The semiconductor substrate is made to be of low concentration in this way. Thereby a capacity between an element and the substrate is reduced and a high performance can be attained. In addition, the downward diffusion of the epitaxial layer formed can be held down and element isolation can be performed without fail.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to, for example, bipolar transistors, BICMO
The manufacturing method of semiconductor devices such as S, especially the insulating layer and the first layer immediately below it.
The present invention relates to a method for manufacturing a semiconductor device that performs element isolation in a conductive region.

[Summary of the invention]

The present invention provides a method for manufacturing a semiconductor device in which element isolation is performed using an insulating layer and a first conductivity type region immediately below the insulating layer, in which a buried layer of a second conductivity type is formed in a predetermined region of the whole surface of a low concentration semiconductor substrate of a first conductivity type. After the formation, impurities of the first conductivity type are introduced into the entire surface of the semiconductor substrate to increase the surface concentration of the semiconductor substrate, and then an epitaxial layer of the second conductivity type is formed.
By forming an element isolation region by forming an insulating layer and a first conductivity type region directly below the insulating layer that reaches the semiconductor substrate, diffusion of the epitaxial layer toward the substrate side is suppressed, and the capacitance between the element and the substrate is reduced. This is intended to improve performance and at the same time ensure element isolation.

[Conventional technology]

FIG. 2 shows an example of a hyperpolar transistor in an LSI (large scale integrated circuit). In the figure, (1) is, for example, p
This p-type silicon substrate (1)
After forming an n-type epitaxial layer (3) through an n-type collector buried layer (2) on the entire surface of the 5), and a p-type intrinsic base region (7) is formed in the collector region (6) formed by the n-type epitaxial layer.
) and a p+ extrinsic base region (8), and an n-type emitter region (9) within the p-type intrinsic base region (7). (10) shows a p′″ region directly below the field insulating layer (5) that reaches the +[l′)con board (1),
This p+ region (10) and field insulating layer (5) form an element isolation region (11).

In such a bipolar transistor (12),
One way to improve its performance is to use silicon substrates (1).
By reducing the substrate concentration of the collector substrate (1), the capacitance Cj
A method for reducing s has been proposed.

On the other hand, as one method for miniaturizing bipolar transistors by so-called selective oxidation separation as shown in FIG. 2, a p+ region (10
) is formed by high-energy ion implantation through the field insulating layer (5).

This method is used before forming the n-type epitaxial layer (3),
Compared to the method of forming the p+ region (10) before selective oxidation, impurity re-diffusion in the p+ region (10) is suppressed, so the distance β between the collector buried layer (2) and the p' region (10) is can be reduced. However, in this method, the defects formed in the p+ region (10) during high-energy ion implantation remain even after the subsequent annealing process, so the dose of 11
Ion implantation on the order of 0"cm' or more cannot be performed.

[Problem to be solved by the invention]

By the way, in order to improve the performance and miniaturize bipolar transistors, the above-mentioned low concentration substrate (1) and the p+ region (10) formed by high energy ion implantation after selective oxidation are used.
When the above formation method is used in combination, there is also downward diffusion of the n-type epitaxial layer (3) (diffusion toward the p-type silicon substrate (1) side), so that the p' region (10) is formed on the p-type silicon substrate (1).
This may result in insufficient element isolation. in this case,
A countermeasure to this problem is to reduce the concentration of the n-type epitaxial layer (3), but the thickness of the n-type epitaxial layer (3) is 1 to 2 μm.
The n-type epitaxial layer concentration that can be realized in mass production is l
Q I S cm-3 order at most, and by lowering the concentration of the n-type epitaxial layer (3), the base region (7)
Considering the Kirk effect of , an increase in collector resistance Rc, etc., there is a limit to how low the concentration of the n-type epitaxial layer (3) can be reduced.

In addition, p + region (10) by ion implantation after selective oxidation
Since the substrate potential extraction region is also formed in the same process as the formation of , the substrate potential extraction also becomes insufficient due to the downward diffusion of the epitaxial layer as described above.

FIG. 3 shows a comparative example of a method for manufacturing an npn bipolar transistor using a low concentration substrate and a p+ region formation method using high energy ion implantation after selective oxidation.

As shown in Figure 3A, a low concentration p-type silicon substrate (1)
After forming an n-type collector buried layer (2) in a predetermined region on one main surface of the substrate, an n-type epitaxial layer (3) is formed as shown in FIG. Is this epic? The n-type epitaxial layer (3) is diffused downward toward the p-type silicon substrate (1) in a thermal process during silicon growth. (d1) is a difference in which the n-type epitaxial layer (3) is diffused downward from the principal surface of the substrate (1). Next, as shown in FIG. 3C, a thin S10 is formed. A film (15) is formed and a resist mask (16) is formed.
), an n-type collector extraction region (4) reaching the collector buried layer (2) is formed by, for example, ion implantation and subsequent heat treatment. Even in this diffusion heat treatment of the collector extraction region (4), the epitaxial layer (3) is diffused downward, resulting in a difference d2. Next, as shown in FIG. 3D, a SiN film (17) is deposited on the thin Sin2 film (15) by CVD (
After deposition by chemical vapor deposition), a resist mask (18) with a predetermined pattern is formed, and this resist mask (
As shown in FIG. 3E, the SiN film (17), the SiO2 film (15), and the epitaxial layer (3) corresponding to the field area are selectively etched away through the etching process (18).
A recess (19) is formed. Next, as shown in FIG. 3F, selective oxidation is performed to form a field insulating layer (SiO2) (5). After that, a newly formed resist mask (20
), a p-type impurity (for example, boron) (22) is ion-implanted to form a p+ region (10) that constitutes an element isolation region (11) directly under the field insulating layer (5), and a substrate potential extraction region. A p′ region (21) is formed. The heat treatment during selective oxidation further diffuses the epitaxial layer (3) downward, resulting in a difference d3. Thereafter, as shown in FIG. 3G, a p-type impurity is diffused through the first p+ polycrystalline silicon film (24a) to form a p+ external base region (8), and this p+ polycrystalline silicon film (
24a) is used as a base extraction electrode, and p-type impurities and n-type impurities are diffused through the second polycrystalline silicon film (25) to form a p-type intrinsic base region (7) and an n-type emitter region (9). form. Further, in the substrate potential extraction section, a p+ region (26) reaching the p+ region <21> is formed by further p-type impurity diffusion using the first p+ polycrystalline silicon (24b), and both p+ regions <21> are formed. In step (26), a substrate potential extraction region (27) is formed.

After that, the emitter electrode (28) and base electrode (
29) and a collector electrode (30) are formed, and at the same time, a substrate potential extraction electrode (31) is formed.

As shown in FIG. 3G, if no countermeasures are taken, the p' region for element isolation ( 10
) does not reach the substrate (1), resulting in insufficient element isolation, and similarly in the substrate potential extraction section, the p+ region (21) does not reach the substrate (1).
1) was not achieved, resulting in insufficient extraction of the substrate potential.

Figure 4 shows that in Figure 3, the thickness of the field insulating layer (5) is 8000 mm, and the specific resistance of the n-type epitaxial layer (3) is 0.
．． 3Ωcm, thickness 1.0μm Sp type silicon substrate (1)
The specific resistance is 15 Ωcm, and the boron ion implantation condition for forming the p+ region (10) for element isolation is energy 3.
60KeV, dose 6 x 1013 cm
− 2, the impurity profile of the element isolation region (11) after the formation of the emitter region (9) (that is, after annealing) (the impurity profile on the aa line in FIG. 3G)
Here is an example.

In the figure, the solid line (I) is the final impurity concentration profile, the broken line (n) is the boron concentration profile, and the dashed line (II) is the final impurity concentration profile.
I) is the phosphorus concentration profile. As is clear from this impurity profile, the p” region for element isolation
) and the p-type silicon substrate (1), an n-type epitaxial downward diffusion portion (3a) remains, resulting in insufficient element isolation.

Note that increasing the thickness of the field insulating layer (5) can also be taken as a countermeasure, but increasing the thickness increases the burst peak, resulting in disadvantages in terms of miniaturization and defects.

In view of the above-mentioned points, the present invention provides a method for manufacturing a semiconductor device that minimizes the element-to-substrate space, suppresses downward diffusion of the epitaxial layer, and makes it possible to form reliable element isolation regions. be.

[Means to solve the problem]

The present invention includes an insulating layer (5) and a first conductivity type region (
In the method for manufacturing a semiconductor device that performs element isolation in step 10), after forming a buried layer (2) of a second conductivity type in a predetermined region of the whole surface of a low concentration semiconductor substrate (1) of a first conductivity type, the semiconductor substrate ( 1) introducing a first conductivity type impurity (41) into the entire surface of the semiconductor substrate (1) to increase the surface concentration of the semiconductor substrate (1); A step of forming an epitaxial layer (3), and then forming an insulating layer (5).
) and a first conductivity type region (10) reaching the semiconductor substrate (1) is formed directly under the insulating layer (5) to form an element isolation region (11).
It is characterized by having a step of forming.

[Effect]

According to the above-mentioned manufacturing method, after forming the buried layer (2) of the second conductivity type, the impurity of the first conductivity type (41) is introduced into the entire surface of the semiconductor substrate (1). By increasing the surface concentration, diffusion of the second conductivity type epitaxial layer (3) formed on one main surface of the semiconductor substrate (1) toward the substrate side (so-called downward diffusion) is offset, and the epitaxial layer (3) Downward diffusion is suppressed. Therefore, when an element isolation region (11) is formed by the insulating layer (5) and the first conductivity type region (10) immediately below it, there is a gap between the first conductivity type region (10) and the substrate (1). There is no downward diffusion part of the epitaxial layer (2), and element isolation can be ensured. Therefore, while achieving reliable element isolation, the capacitance between the element substrates can be reduced by lowering the concentration of the semiconductor substrate.

〔Example〕

Hereinafter, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. Note that this example is applied to a bipolar transistor in an LSI, and in FIG. 1, parts corresponding to those in FIG. 3 are designated with the same reference numerals.

In this example, as shown in FIG.
) After forming a collector buried layer (2) of the second conductivity type, that is, n-type, in a predetermined region on the whole surface of the substrate (1), a p-type impurity such as boron (41) is added at 1013c to the entire surface of the whole surface of the substrate (1).
Ions are implanted with a dose of m-2 or less, and the substrate (1
) to increase the surface concentration. (41a) indicates a boron ion implantation region.

Next, as shown in FIG. 1, an n-type epitaxial layer (3) having, for example, an impurity concentration on the order of IQI[lCm-3] is formed on one main surface of the substrate (1).

The subsequent steps are similar to those shown in FIG. 3C and subsequent steps.

That is, as shown in FIG. 1C, a thin S102 film (15)
1 1 and reaches the collector buried layer (2) through a resist mask (16) by, for example, ion implantation and heat treatment.
A shape collector extraction area (4) is formed.

Next, as shown in FIG.
After a SiN film (17) is deposited on the top by CVD method, a resist mask (18) with a predetermined pattern is formed, and a resist mask (18) is formed to correspond to the field area as shown in FIG. 1E through this resist mask (18). A recessed portion (19) is formed by selectively etching away the portion to be removed.

Next, as shown in FIG. 1F, the field insulating layer (SiO2) (5) is selectively oxidized using the SiN film (17) as a mask.
After forming the newly formed resist mask (20)
A p-type impurity, such as boron (22), is ion-implanted at high energy through the field insulating layer (5) to form a p+ region (10) that constitutes an element isolation region (11), and also as a substrate potential extraction region. The p+ region (21)
form.

Thereafter, as shown in FIG. 1G, a p-type impurity is diffused using the first p+ polycrystalline silicon film (24a) as a diffusion source to form a p' external base region (8). Using the p+ polycrystalline silicon film (24a) as a base extraction electrode, p-type impurities and n-type impurities are diffused through the second polycrystalline silicon film (25) to form a p-type intrinsic base region (7) and an n-type An emic region (9) is formed, and this second polycrystalline silicon film (25) is used as an emitter extraction electrode. Further, in the substrate potential extraction section, the first p
A p+ region (21) is formed by p-type impurity diffusion using the polycrystalline silicon film (24b) to reach the p+ region (21).
26), and a substrate potential extraction region (27) is formed in both p' regions (21) and (26). Then, an emitter electrode (28), a base electrode (29), and a collector electrode (30) are formed using M, and at the same time, a substrate potential extraction electrode (31) is formed, and the desired particle type npn bibolar transistor (42) is formed. get.

According to the above manufacturing method, by lowering the concentration of the p-type silicon substrate (1), the capacitance C between the n-type collector substrate (1) is reduced.
js can be reduced, and the performance of the bibolar transistor can be improved. Moreover, after forming the n-type collector buried layer (2), 1I:l boron ions are implanted into the entire surface of the p-type silicon substrate (1) at a dose IQ of 13 cm-2 or less to increase the surface concentration of the substrate (]). By increasing the height, when the n-type epitaxial layer (3) is formed next, even in a certain subsequent heat treatment, the downward spread of the n-type epitaxial layer (3) (re-diffusion toward the substrate (1) side) is prevented. It can be suppressed. That is, the downward diffusion of the n-type epitaxial layer (3) is offset by the highly doped surface of the p-type silicon substrate (1), and the downward diffusion of the n-type epitaxial layer (3) is substantially suppressed. Therefore, the element isolation region (11)
The p' region (10) reaches the p-type silicon substrate (1),
Reliable element isolation can be performed. In addition, the p'' region (21) of the substrate potential extraction portion is formed in the same process as the formation of the p'' region (10) for element isolation by ion implantation, and this p+ region (21) is also formed using the n-type epitaxial layer (3). ) by suppressing the downward diffusion of the p-type silicon substrate (1).
, and the substrate potential can be reliably extracted.

On the other hand, since the p' region (10) for element isolation is formed by ion implantation after forming the field insulating layer (5), the distance β between the collector buried layer (2) and the p' region (10) is reduced. It is possible to promote miniaturization14.

Therefore, in this method, the collector-substrate capacitance Cjs is reduced by lowering the concentration of the substrate (1).
This can be achieved without causing a failure in taking out the substrate potential.

In the above example, the application was applied to the manufacture of a particle-type bipolar transistor, but other Bi-CMOS (MOS
}Including cases where the transistor side has a buried layer), the present invention can also be applied to the manufacture of lateral type bibolar transistors having a base buried layer, etc. In a lateral bipolar transistor, by using a low concentration substrate, the capacitance between the base and the substrate can be reduced and high performance can be achieved.

〔Effect of the invention〕

According to the method for manufacturing a semiconductor device according to the present invention, by lowering the concentration of the semiconductor substrate of the first conductivity type, it is possible to reduce the element-to-substrate capacitance and improve performance. Moreover, by increasing the surface concentration of the semiconductor substrate by introducing impurities of the first conductivity type after forming the buried layer of the second conductivity type, it is possible to suppress the downward diffusion of the subsequently formed epitaxial layer, and thereby to separate the elements. can be done reliably. Therefore, a highly reliable and high performance semiconductor device can be manufactured.

In particular, the present method vertical bibolar transistor, [l
It is suitable for application to the manufacture of LSIs having i-CMOS, lateral type bipolar transistors, etc.

[Brief explanation of drawings]

1A to 1G are manufacturing process diagrams showing an example of applying the semiconductor device manufacturing method according to the present invention to a bipolar transistor, FIG. 2 is a cross-sectional view of a bipolar transistor, and FIG.
Figures A to G are manufacturing process diagrams showing a comparative example of the manufacturing method of a bipolar transistor, and Figure 4 is an impurity profile on the aa line shown in Figure 3. (1) is a p-type silicon substrate, (2) is an n-type collector buried layer, (3) is an n-type epitaxial layer, (5) is a field insulating layer, (6) is a collector region, and (7) is an intrinsic base region. ■ b region, (9) is the emitter region, (10) is the p'' region for element isolation, (41) is the boron ion. Agent Hidemori Matsukuma 17 1 (ko 1...p most silicon certain destruction 2 n◇Koshikta melt hNk layer 3...n% epitaxial layer 4...Collector J's cleaning 4 beak collection 5 Fee + LP 蛯Green waste 6 Ko Shikutai order t87・Kiyoshi Taku base now negative cough'' 8...External base bandit' 9...Emitter 脣76゛10゛・p+/@smoking' 11...Kou 5l-kai Kojaku jealous' 12... Bypass Transmission Q (d) Ward Nakako)

Claims (1)

[Claims] In a method for manufacturing a semiconductor device in which device isolation is performed using an insulating layer and a first conductivity type region immediately below the insulating layer, a second conductivity type is added to a predetermined region of one principal surface of a first conductivity type low concentration semiconductor substrate. After forming the buried layer, a step of introducing a first conductive impurity into the entire surface of one main surface of the semiconductor substrate to increase the surface concentration of the semiconductor substrate; A semiconductor device comprising the steps of forming an epitaxial layer, and then forming an insulating layer and a first conductivity type region directly below the insulating layer reaching the semiconductor substrate to form an element isolation region. Manufacturing method.