JPH03214760A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03214760A
JPH03214760A JP2009694A JP969490A JPH03214760A JP H03214760 A JPH03214760 A JP H03214760A JP 2009694 A JP2009694 A JP 2009694A JP 969490 A JP969490 A JP 969490A JP H03214760 A JPH03214760 A JP H03214760A
Authority
JP
Japan
Prior art keywords
resistor
pad
input protection
protection resistor
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009694A
Other languages
Japanese (ja)
Inventor
Toshihiro Yosako
與迫　利博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2009694A priority Critical patent/JPH03214760A/en
Publication of JPH03214760A publication Critical patent/JPH03214760A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce an improper opening of an Al pad and an input protective resistor due to overetching at the time of forming a contact hole by forming a conductor layer under the resistor in the connection part of the resistor made of polysilicon to the pad. CONSTITUTION:An input protective resistor 4 made of polysilicon provided on a semiconductor substrate 1 and a pad 6 made of Al to be connected to the resistor 4 are provided. In this case, a conductor layer 3 is provided at the lower part of the resistor 4 at the connection part of the resistor 4 to the pad 6. That is, the layer 3 is provided at the lower part of the resistor 4 under a contact hole 8. Accordingly, even if the resistor 4 is etched to form an overetched part 9 by overetching at the time of formation of the hole 8, the resistor 4 is connected to the pad 6 through the layer 6. Thus, an improper opening can be eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に入力保護回路部の入力
保護抵抗とＡｌパッドの接続構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a connection structure between an input protection resistor and an Al pad in an input protection circuit section.

〔従来の技術〕[Conventional technology]

従来、入力保護回路部を有する半導体装置においては、
Ａｌパッドとポリシリコンからなる入力保護抵抗の接続
は次のように行なわれていた。Conventionally, in a semiconductor device having an input protection circuit section,
The connection between the Al pad and the input protection resistor made of polysilicon was performed as follows.

すなわち第２図に示ず様に、シリコン基板１上に絶縁膜
からなる素子分離帯２を形成し、その上に入力保護抵抗
４を形成する。次で眉間絶縁膜５Ａを形成した後にコン
タクト六８をウエツ１・およびドライエッチング法にて
形成する。次に、このコンタクト穴８を含む全面にＡｌ
膜を形成し、パターニングしてＡ４７パット６を形成す
ることにより入力保護抵抗４とＡｌパッド６の接続を行
なっていた。That is, as shown in FIG. 2, an element isolation band 2 made of an insulating film is formed on a silicon substrate 1, and an input protection resistor 4 is formed thereon. Next, after forming the glabellar insulating film 5A, a contact 68 is formed by wet etching and dry etching. Next, the entire surface including this contact hole 8 is coated with Al.
The input protection resistor 4 and the Al pad 6 are connected by forming a film and patterning it to form an A47 pad 6.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のＡ！２パッドと入力保護抵抗の接続構造
では、素子分離領域上での接続となっているので、第２
図に示した様に、入力保護抵抗４とＡｌパッド６とのコ
ンタクトを取る際に眉間膜５Ａがオーバーエッチングさ
れた場合、入力保護抵抗４までエッチングされてしまい
入力保護抵抗４とＡｆｆｌパッド部６とがオープンにな
ってしまうという欠点があった。The conventional A! mentioned above! In the connection structure between the 2nd pad and the input protection resistor, the connection is made on the element isolation region, so the 2nd
As shown in the figure, if the glabellar film 5A is over-etched when making contact between the input protection resistor 4 and the Al pad 6, the input protection resistor 4 will also be etched, and the input protection resistor 4 and the Affl pad portion 6 will be etched. The disadvantage was that the information was left open.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、半導体基板上に設けられたポリ
シリコンからなる入方保護抵抗とこの入力保護抵抗に接
続するＡ℃がらなるパッドとを有する半導体装置におい
て、前記入力保護抵抗とパッドとの接続部における入力
保護抵抗の下部に導伝体層を設けたものである。A semiconductor device of the present invention includes an input protection resistor made of polysilicon provided on a semiconductor substrate and a pad made of A° C. connected to the input protection resistor, wherein the input protection resistor and the pad are connected to each other. A conductor layer is provided below the input protection resistor at the connection portion.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を示す断面図である。以下製
造方法と共に説明する。FIG. 1 is a sectional view showing one embodiment of the present invention. The manufacturing method will be explained below.

半導体基板１上に絶縁膜からなる素子分離帯２を所望箇
所に形成する。次に全面にポリシリコン膜を約２０００
人の厚さにスパッタ蒸着し、リン拡散を行なったのちパ
ターニングし、導伝体層３を形成する。次に全面に眉間
絶縁膜５を形成した後、導伝体層３上に開口部を設けた
のち、全面に例えばポリシリコンを約２５００人の厚さ
に成長させる。次でエネルギー７０ｋｅＶ，　　ドーズ
量１　Ｘ　１　０　１６ｃｍ−２の条件にてリンのイオ
ン注入を行なったのち、パターニングし、ボリシリコか
らなる入力保護抵抗４を形成する。次に再び眉間絶縁膜
５Ａを約７０００人の厚さに成長させた後、入力保護抵
抗４とＡｌパッド６との接続用のコンタクト穴８をウェ
ットおよびドライエッチング方法にて形成する。次にＡ
ｌを約１１０００人の厚さにスパッタ蒸着し、パターニ
ングしてＡｌパット６を形成したのちカバー膜７を成長
させ、ボンディングパッド用の穴をあける。Element isolation bands 2 made of an insulating film are formed on a semiconductor substrate 1 at desired locations. Next, apply a polysilicon film of about 2,000 layers to the entire surface.
The conductor layer 3 is formed by sputter deposition to a thickness of about 100 mm, followed by phosphorus diffusion and patterning. Next, after forming a glabellar insulating film 5 on the entire surface, an opening is provided on the conductor layer 3, and then, for example, polysilicon is grown on the entire surface to a thickness of about 2500 nm. Next, phosphorus ions are implanted at an energy of 70 keV and a dose of 1.times.10.sup.16 cm.sup.-2, followed by patterning to form an input protection resistor 4 made of borosilico. Next, after growing the glabellar insulating film 5A again to a thickness of about 7000 mm, a contact hole 8 for connecting the input protection resistor 4 and the Al pad 6 is formed by wet and dry etching methods. Next A
Al is sputter-deposited to a thickness of about 11,000 mm, patterned to form an Al pad 6, a cover film 7 is grown, and a hole for a bonding pad is made.

このように本実施例によれば、コンタクト穴８下の入力
保護抵抗４の下部には、導伝体層３が設けられているた
め、コンタク１・穴８の形成時にオーバーエッチングに
より入力保護抵抗４までエッチングされてオーバーエッ
チング部９が形成されても、導伝体層６を通して入力保
護抵抗４とＡｌパッド６が接続されているため、オープ
ン不良をなくすことができる。According to this embodiment, since the conductive layer 3 is provided below the input protection resistor 4 under the contact hole 8, the input protection resistor is over-etched when forming the contact 1 and the hole 8. Even if the over-etched portion 9 is formed by etching up to 4, since the input protection resistor 4 and the Al pad 6 are connected through the conductor layer 6, open defects can be eliminated.

上記実施例においては、導伝体層としてポリシリコンを
用いた場合について説明したが、ポリシリコンのかわり
にタングステンシリサイドを用いてもよい。この場合、
タングステンシリサイドのエッチングレートはポリシリ
コのエッチングレートよりおそい為コンタクト穴のオー
バーエッチングの際、タングステンシリサイド表面のエ
ッチングによりダメージが少なくなるなめ、オーバーエ
ッチングによるオープン不良がさらに低減出来るという
利点がある。In the above embodiment, a case has been described in which polysilicon is used as the conductor layer, but tungsten silicide may be used instead of polysilicon. in this case,
The etching rate of tungsten silicide is slower than the etching rate of polysilicon, so when over-etching a contact hole, there is less damage due to etching of the tungsten silicide surface, which has the advantage of further reducing open failures due to over-etching.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体装置においてボリ
シリコからなる入力保護抵抗とＡｌパッドの接続部にお
ける入力保護抵抗の下に導伝体層を形成することにより
、コンタクト穴形成時のオーバーエッチングによるＡｌ
パッドと入力保護抵抗とのオーブン不良を低減すること
が出来るという効果がある。As explained above, in a semiconductor device, the present invention forms a conductor layer under the input protection resistor at the connection portion between the input protection resistor made of borosilico and the Al pad, thereby reducing the risk of Al damage caused by over-etching when forming the contact hole.
This has the effect of reducing oven defects between the pad and the input protection resistor.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の断面図、第２図は従来例の
断面図である。 ５ １・・・シリコン基板、２・・・素子分離帯、３・・・
導伝体層、４・・・入力保護抵抗、５．５Ａ・・・層間
絶縁膜、６・・・Ａ．Ｃパッド、７・・・カバー膜、８
・・・コンタクＩ・穴、９・・・オーバーエッチング部
。FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. 5 1...Silicon substrate, 2...Element separation band, 3...
Conductor layer, 4... Input protection resistor, 5.5A... Interlayer insulating film, 6... A. C pad, 7...Cover membrane, 8
...Contact I/hole, 9...Over-etched part.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に設けられたポリシリコンからなる入力保
護抵抗とこの入力保護抵抗に接続するＡｌからなるパッ
ドとを有する半導体装置において、前記入力保護抵抗と
パッドとの接続部における入力保護抵抗の下部に導伝体
層を設けたことを特徴とする半導体装置。In a semiconductor device having an input protection resistor made of polysilicon provided on a semiconductor substrate and a pad made of Al connected to the input protection resistor, a lower part of the input protection resistor at a connection part between the input protection resistor and the pad is provided. A semiconductor device characterized by providing a conductor layer.
JP2009694A 1990-01-19 1990-01-19 Semiconductor device Pending JPH03214760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009694A JPH03214760A (en) 1990-01-19 1990-01-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009694A JPH03214760A (en) 1990-01-19 1990-01-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03214760A true JPH03214760A (en) 1991-09-19

Family

ID=11727334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009694A Pending JPH03214760A (en) 1990-01-19 1990-01-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03214760A (en)

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