JPS61240656A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an electrode film having a smooth slope with good reproducibility and to prevent the second gate electrode from being disconnected by thermally diffusing a high density impurity in a polycrystalline silicon film to become the first layer electrode,then accumulating an amorphous silicon film on the surface, and then performing an isotropic etching. CONSTITUTION:After a polycrystalline silicon film 4 to become the first layer electrode is accumulated, an impurity is added in high degree by thermal diffusion to reduce the resistance of the film, and an amorphous silicon film 5 is then accumulated on the entire surface. An isotropic etching is selectively performed, and a lower electrode having a suitable tapering angle shape is formed by utilizing the difference of the etching velocities of both. Then, an insulating film 8 and the second electrode material film 9 are formed over the stepwise tapered difference portion on the surface of the first film. The second electrode material film is selectively removed by etching to form the second electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a two-layer gate electrode structure including a lower electrode and an upper electrode.

[Technical background of the invention and its problems]

In recent years, due to the demand for higher integration in the manufacture of integrated 1-1 circuits, VH pole cell structures with multilayer wiring have come into widespread use. In addition, as devices have become faster to operate, conventional polycrystalline silicon has been replaced as the electrode material, and high-melting-point metals and their silicides, which have low specific resistance, are attracting attention. In response to such demands for high integration and high speed operation, we have developed an M O in which polycrystalline silicon is used for the fourth IW electrode and a high melting point metal or its silicide is used for the second layer electrode.
S-type dynamic l{, AM, CCIJ, etc. have been developed.

However, when manufacturing a semiconductor device with such a structure, if the polycrystalline silicon serving as the first layer electrode is etched by isotropic or anisotropic plasma etching, the etched shape will be at right angles or close to it. It becomes a steep angle. Therefore, on top of the first layer electrode (+
After the high melting point metal or its silicide as the second layer electrode is broken through the K+ material and buttered, the pretreatment B1+ is added and these materials forming the second layer electrode are bonded. Since the stress after heat treatment is large, breakage occurs at the stepped portion, resulting in open spaces between the wiring lines.

In order to improve these problems, a method has recently been reported in which, before etching the first layer electrode, impurity ions are implanted into the surface layer to damage the surface layer and induce defects, and then etching is performed to achieve taper etching. ing.

However, when this method is actually applied to device formation, the following problems arise. The first W used in normal semiconductor devices
The layer resistance of the electrode 11 needs to be as low as 20 to 30 Ω/cm'', but if this is to be doped with impurities by ion implantation, it will be necessary to add impurities of about I x 10''/C''.

However, when polycrystalline silicon into which ions have been implanted to this extent is etched, the taper angle becomes too large, approximately 13 degrees, making it difficult to form fine patterns.

Furthermore, in order to obtain a desired taper angle of 20 to 30 degrees, the amount of impurity added by ion implantation is 1 to 3 x 1
The optimal value is about 0'Il/crrf, but if the layer resistance is 2
Since it becomes as high as 00 to 500 Ω/crrV, it cannot be used practically as an electrode, and there are also problems such as the reproducibility of the taper angle being inconsistent.

[Purpose of the invention]

In the present invention, after thermally diffusing impurities at a high concentration into a polycrystalline silicon film that will become the first layer electrode, an amorphous silicon film is deposited on the surface of the polycrystalline silicon film, and then isotropic etching is performed to form the first layer electrode. The polycrystalline silicon film and the amorphous silicon film are suitably taper-etched, and then the second layer 1 is etched through the insulating film.
! [It is characterized by depositing a high melting point metal or its silicide which is ei.

[Summary of the invention]

That is, in the present invention, after depositing a polycrystalline silicon film that will become the first layer electrode, impurities are added to a high concentration by thermal diffusion to lower the resistance of the polycrystalline silicon film, and then an amorphous silicon film is deposited on the entire surface. is deposited on. and a step of selectively performing isotropic etching and utilizing the difference in etching speed between the two to form a lower electrode having an appropriate taper angle shape;
forming an insulating film and a second electrode material film on the surface of the first electrode material film to cover the tapered stepped portion; and selectively etching and removing the second electrode material film;
The method is characterized by comprising a step of forming the electrode.

[Embodiments of the invention]

An example in which the present invention is applied to the manufacture of an MO8 type dynamic RAM having a two-layer gate electrode structure will be described below (see FIG. 1).
a) Explain in detail with reference to 5(f).

First, an area other than the element region of a P-type silicon substrate is etched using a silicon nitride film (not shown) as a mask, and boron ions are implanted into this etched area to form a P+ etching layer for channel cutting.
After forming the mold region, selective oxidation is performed using the silicon nitride film as an oxidation-resistant mask to form a field oxide film.

Subsequently, thermal oxidation treatment is performed to grow an oxide film with a thickness of about 300× in the element region of the silicon substrate.

Next, a polycrystalline silicon layer as a first gate electrode material film is deposited over the entire surface to a thickness of about 400 OA.

Subsequently, phosphorus is diffused at 900° C. for 30 minutes in order to lower the layer resistance of the polycrystalline silicon layer. FIG. 1(a) Next, a plasma device is used to deposit an amorphous silicon film with a thickness of 500 to 100%.
0x deposit. As shown in FIG. 3 (q), a resist pattern is formed in the area where the first gate electrode is to be formed by photo-etching.Then, using the resist pattern as a mask, plasma etching is performed to form the first gate electrode. An electrode is formed. Next, using this first gate electrode as a mask, the exposed silicon oxide film is etched to form a first gate oxide film. Next, after removing the resist pattern, a wet oxygen atmosphere at, for example, 850°C is formed. A heat treatment is performed for about 30 minutes in the wafer.At this time, an oxide film with a thickness of about 20007e grows on the upper surface of the first gate electrode, and at the same time, the amorphous silicon film becomes polycrystalline.

Then, on the exposed silicon substrate surface, an oxide film with a thickness of about 400λ is grown as a second gate oxide film (see FIG. 1).
d).

Next, the second game on the entire surface)! A molybdenum silicide film is deposited as an electrode material to a thickness of about 300X and selectively etched to form a second gate electrode overlapping the first gate electrode with an oxide film interposed therebetween.

Subsequently, the oxide film is etched using the second gate electrode as a mask to form a second gate oxide film.

(Figure 1(e)).

Next, ions of, for example, an element are implanted into the exposed bamboo plate by self-alignment, and activated by heat treatment or the like to form a measurement region that will become a digit line.

After this, a CVD-8iO2 film is deposited on the entire surface, and a CVD-8iO2 film is deposited on the entire surface, and a CVD-8iO2 film is deposited on the entire surface.
．． The film and the thermal oxide film are selectively etched away to form a contact hole. After that, an aluminum film is vacuum-deposited and patterned to form an aluminum wiring connected to the first and second gate electrodes and the leaf-shaped region through a contact hole.
AM is manufactured (FIG. 1(f)).

〔Effect of the invention〕

Therefore, according to the above embodiment, the first layer made of polycrystalline silicon
The layer resistance of the first gate electrode can be made sufficiently low, and since an amorphous silicon layer is deposited on the top surface of the first gate electrode, the subsequent taper etching can be performed by utilizing the difference in etching speed of the amorphous silicon layer. An electrode film having a gentle slope can be formed with good reproducibility.

Therefore, the wiring is overlapped with the first gate electrode via the insulating film.

The second gate electrode is not disconnected and can be wired with high reliability.

Further, although the polycrystalline silicon film that becomes the first gate electrode is doped with highly concentrated phosphorus, according to the present invention, the upper surface of the first gate electrode, except for a portion of the taper, is doped with phosphorus. The majority of the film is amorphous silicon film, which is not coated. This also has the effect of preventing phosphorus in this polycrystalline silicon film from out-diffused and being incorporated into the second gate oxide film when forming the second gate oxide film, resulting in device reliability. is M (') 8 according to an embodiment of the present invention
FIG. 3 is a process-by-step cross-sectional view showing the manufacturing process of the dynamic type RλM.

In the figure, 1...Silicon substrate 2...Field oxide film 3...Gate oxide film 4...Polycrystalline silicon film 5...Amorphous silicon film 6... Photoresist pattern film 7...Second gate oxide film 8...Interlayer isolation W film 9...MO8i, membrane 10・・CVD-8in, film 11... Aluminum film

Claims (2)

[Claims] (1) After depositing an amorphous semiconductor material on the surface of highly doped polycrystalline silicon that will become the first layer electrode,
1. A method of manufacturing a semiconductor device, which comprises performing isotropic etching to taper-etch the laminated film, and then depositing a high melting point metal or its silicide, which will become a second layer electrode, through an insulator. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the amorphous semiconductor material is an amorphous silicon film.