JPH03214941A - Pattern synchronizing device - Google Patents

Abstract

PURPOSE:To shorten a maximum time required for synchronization even when an input pattern and a reference pattern are ultra long patterns in a pattern synchronizing device for an error rate measuring instrument by blocking the supply of a clock to an M series generator to generate a queue pattern as an output of a pattern generating section and supplying the clock to the M series generator continuously when an input pattern is coincident with the queue pattern. CONSTITUTION:An M series generator generates an M series with a prescribed pattern content whose pattern length is 2N-1 bits by receiving clocks continuously. When a queue pattern being an output of a reference pattern generating section 70 is coincident with an input pattern produced at the blocking of the clock supply to the M series generator 10, the output of the reference pattern generating section 70 is synchronized with the input pattern and clocks are fed continuously to the M series generator of the reference pattern generating section after the time of coincidence and a reference pattern is generated from a reference pattern generating section to obtain the reference pattern synchronously with the input pattern from the reference pattern generating section after the coincidence.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a pattern synchronization device for an error rate measuring device. ``Prior Art'' To measure the error rate of a digital transmission system, a measurement pattern generator with a predetermined bit length (generally 2N-1 bits) is generated on the input side of the digital transmission system to be measured. This is then supplied to the digital transmission system, and on the output side of the digital transmission system, a standard similar to the measurement pattern supplied to the digital transmission system from a reference pattern generation section similar to the measurement pattern generation section on the input side is generated. By obtaining a pattern and comparing it with the input pattern obtained through the digital transmission system, errors in the input pattern obtained through the digital transmission system are detected, and the number of errors per unit bit length is counted. In this case, if the reference pattern obtained from the reference pattern generator is not synchronized with the input pattern obtained through the digital transmission system, it will be determined that there is an error even if there is no error in the input pattern. For this, a pattern synchronization device is provided to synchronize the reference pattern obtained from the input pattern with the input pattern, and errors in the input pattern are counted while the reference pattern is synchronized with the input pattern by this pattern synchronization device.
The pattern synchronization device of such an error rate measuring instrument is
As shown in Japanese Patent Application No. 62-324831, the reference pattern obtained from the reference pattern generator is compared with the input pattern obtained through the digital transmission system using the clock from the clock generator, and the reference pattern is determined as the input pattern. A clock that corrects the phase of the reference pattern obtained from the reference pattern generation section by temporarily prohibiting the supply of the clock to the reference pattern generation section and temporarily stopping the generation of the reference pattern from the reference pattern generation section when the clock does not match the reference pattern generation section. It is structured in a way that can be called the extraction method. Therefore, the maximum number of clock removal operations until the reference pattern is synchronized with the input pattern is equal to the pattern length of the reference pattern and the input pattern. [Problems to be Solved by the Invention] However, in the conventional pattern synchronization device using the clock extraction method described above, there is a time delay between the clock edge and the generation of reference pattern data in the reference pattern generation section. In reality, it is necessary to allow a loss time of about 100 nanoseconds for one clock removal operation, so for example, if the pattern length of the input pattern and reference pattern is 2xs 1 bit (
8Mbit), the maximum time required for synchronization is 1
00 x 10-” seconds x 8 x 10” -0.8 seconds
...(1), but for example, if the pattern length of the input pattern and reference pattern is 2s + 1 bit (2G bit), the maximum time required for synchronization is 100XI
O-' seconds x 2 x 10 seconds = 200 seconds...(2)
If the input pattern and the reference pattern are extremely long patterns, as shown in the following, there is a disadvantage that the maximum time required for synchronization becomes extremely long. Accordingly, the present invention provides a pattern synchronization device for an error rate measuring device in which the maximum time required for synchronization is significantly shortened even when the input pattern and the reference pattern are extremely long patterns. "Means for Solving the Problem" The present invention has an M-sequence (maximum periodic sequence) generator, and by continuously supplying a clock to the M-sequence generator, the pattern length is 2'4-1. A reference pattern generation unit that obtains a reference pattern consisting of an M sequence with a predetermined pattern content of l bits; The data content equal to the data content of specific consecutive J bits in one pattern (J is the number where a data string with data content equal to the data content of the J bits appears only once in the above one pattern, where J is N or more) Generating a standby pattern, detecting whether or not the input pattern consisting of the M sequence matches the standby pattern, and continuously clocking the M sequence generator from when the input pattern matches the standby pattern. and a detection control section that causes the reference pattern generation section to generate the reference pattern by supplying the reference pattern to the reference pattern generation section.

"Effect" G(x) with pattern length of 24-1 bits = x' + x
In the M series where the data content of one pattern is 111100010011010, which is expressed by a generator polynomial of In other words, the number of types of consecutive 4-bit data is equal to the pattern length, and certain types of consecutive 4-bit data, such as 1111, are included in one pattern. As is clear from the fact that it appears only once, in general, in an M sequence with a pattern length of 2N-1 bits, the number of types of data content of consecutive N bits is equal to the pattern length, and the number of types of data content of consecutive N bits is equal to the pattern length. A specific one appears only once in the l pattern.

Therefore, in the pattern synchronization device of the present invention configured as described above, the standby pattern that is the output of the reference pattern generator when the clock supply to the M-sequence generator of the reference pattern generator is blocked is With the above configuration, when the input pattern matches the standby pattern, the output of the reference pattern generation section is synchronized with the input pattern, and after that match, the M sequence of the reference pattern generation section By continuously supplying a clock to the generator and generating a reference pattern from the reference pattern generation section, a reference pattern synchronized with the input pattern can be obtained from the reference pattern generation section after the coincidence occurs.

In the pattern synchronization device of the present invention, if the number of standby patterns and input patterns to be monitored in the detection control section is K, the maximum number of input patterns from initialization to synchronization when clock supply to the M-sequence generator is blocked is K. If (2'-1)XK bits of the pattern are required and the bit rate of the input pattern and reference pattern is fc = 1/TC,
The maximum time required for synchronization is K(2' 1)Tc.

Therefore, when N=23, that is, the pattern length of the input pattern and the reference pattern is 223 1 bits (
8 Mbit), the maximum time required for synchronization is 64 ms when K = 8, fc = IGHz, and 6.4 ms when K = 8, fc = 10 GHz, and N = 31, that is, when the pattern length of the input pattern and the reference pattern is 231 bits (2 Gbits), the maximum time required for synchronization is K=
8, when fc=IGHz, it is 16 seconds, and K=8,
When fc=10 GHz, the maximum time required for synchronization becomes 1.6 seconds, and even when the input pattern and the reference pattern are extremely long patterns, the maximum time required for synchronization is significantly shortened.

Embodiment FIG. 1 shows a general example of the pattern synchronization device of the present invention, which includes an M-sequence generator 10, a PN synthesizer 20, a multiplexing circuit 30, a division circuit 40, a coincidence detection circuit 50, and a clock division circuit 50. Equipped with a control circuit 60, an M-sequence generator 10, PN
Synthesizer 20 and multiplexing circuit 30 constitute reference pattern generation section 70 , and coincidence detection circuit 50 and clock frequency division control circuit 60 constitute detection control section 80 .

The M-sequence generator 10 generates an M-sequence with a predetermined pattern content having a pattern length of 2'-1 bits by being continuously supplied with a clock, and is constituted by a circulating register with N stages. .

The PN synthesizer 20 performs PN synthesis on the outputs Ml, M2, .
By continuously supplying a clock to the sequence generator 10, the output Ml. When the above M sequences are obtained as M2...MN, the L outputs Sl,
S2...SL, respectively its M sequence generator 1
The M sequences that are the same as the M sequences obtained from 0 are obtained with the respective required phases shifted from each other. However, in relation to the number of stages N in the M-sequence generator 10, the stacked number L is set equal to N when N is a power of 2, and when N is not a power of 2, it is a power of 2 larger than N. be made into That is, when N = 4, L = 4, and when N = 31, the minimum value is =
Becomes 32.

The multiplexing circuit 30 converts the L outputs Sl, S2, . . . SL of the PN synthesizer 20 into the K outputs Rl, R2, .
・It is multiplexed to RK, and K is set to 1/integer of L.

The dividing circuit 40 receives an input pattern I obtained at a terminal 91.
The input pattern IP is divided into K outputs 11, 12, . This is the resulting M series. The coincidence detection circuit 50 detects the outputs R1 and R of the multiplexing circuit 30.
2...RK and the output 11, I2 of the dividing circuit 4o...
...It detects whether the IKs match or not. The clock frequency division control circuit 60 includes a frequency divider 61, an AND gate 62, a frequency divider 63, a D flip-flop 64, an OR gate 65, a frequency divider 66, and an OR gate 67. Input pattern IP
The human clock CLl obtained at the terminal 92 with a frequency equal to the bit rate of is divided by 1/K, and the output clock CL2 is supplied to the AND gate 62,
is reset by the initialization signal IN obtained at the terminal 93 to divide the output CL2A of the AND gate 62 into K/L, and the D flip-flop 64 is reset by the initialization signal IN to divide the output CL2A of the frequency divider 63 into K/L. The output RI of the coincidence detection circuit 50 at the falling edge is read, and the output Rr of the coincidence detection circuit 50, one output DX of the D flip 7 lop 64, and the output CL4 of the frequency divider 63 are read.
A is supplied to the OR gate 65, the output OR of the OR gate 65 is supplied to the AND gate 62, the frequency divider 66 is reset by the other output DY of the D flip-flop 64, and the output CL2A of the AND gate 62 is set to K/L. The output CL4B of the frequency divider 66 and the output DY of the D flip-flop 64 are supplied to an OR gate 67, the output CL4C of the OR gate 67 is supplied as a clock input to the M sequence generator 10, and the output of the AND gate 62. CL2A
is supplied as a clock input to the multiplexing circuit 30, and an initialization signal IN is supplied to the M-sequence generator 10 and the multiplexing circuit 30. Further, the input clock CL1 and the output clock CL2 of the frequency divider 6l are supplied to the division circuit 40 as clock inputs.

The operation of the above-mentioned configuration example is as follows: N=4, L=
4, K=2. This can be easily understood from the detailed explanation of the case J=4. FIG. 2 shows an example of the pattern synchronization device of the present invention in the case of N=4, L=4, K=2, and J=4.

In this example, the M-sequence generator 10 has D flip-flops 11-14 and an exclusive-OR gate 15, and the initialization signal IN obtained at the terminal 93 is connected to the reset terminals of the D flip-flops 11-13 and The output CL4C of the OR gate 67 is inverted by the inverter 16 and supplied to the clock terminals of the D flip-flops 11 to 14, and the outputs Ml, M2 . M
3 are supplied to the data terminals of D flip-flops 12, 13, 14, respectively, and the outputs M3. M4 is supplied to the exclusive OR gate 15, and the output XO of the exclusive OR gate 15 is supplied to the D flip-flop 1.
In this configuration, when the D flip-flops 11 to 13 are each reset by the initialization signal IN and the D flip-flop 14 is set, the D flip-flops are supplied to the data terminal 1 of FIG. 1
1.12.13.14 outputs Ml, M2, M3, M4 become O, 0, 0.1, and from this state, when a clock is obtained as the output CL4C of the OR gate 67, the outputs of the D flip-flops 11 to 14 M1 to M4 are ranked 2, 3, etc. in Figure 3 for each falling edge of the clock.
The outputs M1 to M4 of the D flip-flops 11 to 14 each have a pattern length of 24-1
The data content of the l pattern, expressed by the generator polynomial of bits G(x)=x' +x+1, is 11110001
0011010, M sequences whose phases are shifted by 1 bit from each other are obtained between the output M1 and the output M2, between the output M2 and the output M3, and between the output M3 and the output M4. In these M sequences, there are 15 types of consecutive 4-bit data, excluding the case where all 4 bits are 0, as shown in data string Zl-215 in Figure 4. The number of types of data content is equal to the pattern length, and if the data content of consecutive 4 bits is 1111, for example,
Appears only once in a pattern.

The PN synthesizer 20 has exclusive OR gates 21 to 24.
and a D flip-flop 12 . of the M-sequence generator 10 .
14 output M2. M4 is supplied to the exclusive OR gate 21, the outputs M3 and M4 of the D flip-flop 13.14 are supplied to the exclusive OR gate 22, and the output M1. M2 is supplied to the exclusive OR gate 23, and the output BX,X of the exclusive OR gate 22.23
3 is supplied to the exclusive OR gate 24, the output M4 of the D flip-flop I4 is directly taken out as the first output AX, and the output A of the exclusive OR gates 21, 22, 24
Y, BX, and BY are taken out as second, third, and fourth outputs. Therefore, as mentioned above, the M-sequence generator 10
When an M sequence is obtained as the outputs M1 to M4 of the PN synthesizer 20, as shown in FIG.
AY, BX, BY are the same as outputs M1 to M4, respectively, in terms of phase, output AV lags output AX by 7 bits, output BX lags output AX by 11 bits (leads 4 bits), and output BY An M sequence is obtained in which the output BX is delayed by 7 bits.

The multiplexing circuit 30 receives an input clock CLI as described later.
The outputs AX, AY and BX, BY of the PN synthesizer 20 are multiplexed into the outputs RA and RB, respectively, using a clock having a frequency of 1/2 of the frequency of the PN synthesizer 20. The dividing circuit 40 divides the input pattern IP into outputs IA and IB using the input clock CLI and the output clock CL2 of the frequency divider 61 whose frequency is 1/2 of the input clock CLI, and the input pattern IP has a pattern length of 24. -1 bit G
M expressed by the generator polynomial (x)-x' +x+1
It is a series. The coincidence detection circuit 50 includes an exclusive OR gate 5
1, 52 and an AND gate 53, the multiplexing circuit 3
The output RA of 0 and the output IA of the dividing circuit 40 are supplied to an exclusive OR gate} 51, and the output RB of the multiplexing circuit 30 and the output IB of the dividing circuit 40 are supplied to an exclusive OR gate 52. .52 outputs XI and X2 are each inverted and supplied to the AND gate 53, and the output Rl of the AND gate 53 is taken out as the output of the coincidence detection circuit 50, so that the seven inputs RA and IA are both 1 or 0. , and when the outputs RB and IB are both 1 or O, the outputs XI and X2 are both 0 and the output Rl is 1; otherwise, the outputs XI and χ2
If either becomes 1, the output Rl becomes 0. That is, the match detection circuit 5o detects whether the output RA and the output IA match and whether the output RB and the output IB are in a single loss. In this example, the frequency divider 61 is a 1/2 frequency divider consisting of one T flip-flop, and the frequency divider 63
, 66 are each composed of one T flip-flop.
/2 frequency divider. In the above example, the frequency divider 63 is activated by the initialization signal IN.
When the D flip-flops 64 and 64 are reset, the output CL4A of the frequency divider 63 becomes low level, one output DX of the D flip-flop 64 becomes low level, the other output DY becomes high level, and the OR gate 67 becomes low level. Output CL4
As C goes high, the D flip-flop 64
The frequency divider 66 is reset by the output DY of the frequency divider 66 becoming a high level, and the output CL4B of the frequency divider 66 becomes a low level. At this time, the M sequence generator 10 is initialized by the initialization signal IN, that is, the D flip-flops 11 to 13
are reset, and the D flip-flop 14 is set, so that the outputs of the D flip-flops 11, 12, 13, 14 (7) Ml, M2 are set as shown in the order 1 of FIG.
, M3. M4 becomes 0, 0, O, l, the outputs AX, AY, BX, BY of the PN synthesizer 2o become 1, and the output CL4A of the frequency divider 63 and the output DX of the D flip-flop 64 become low level. The output Rl of the coincidence detection circuit 50 is still at a low level, the output OR of the OR gate 65 is at a low level, and the clock is not yet obtained at the output CL2A of the AND gate 62, so the output of the multiplexing circuit 30 is The outputs AX and BX of the PN synthesizer 20 with the M sequence generator 10 initialized are obtained as RA and RB, and the outputs RA and RB are respectively l.
become. Periods T1, T2, . . . in FIG. 5 sequentially indicate periods corresponding to two cycles of the input clock CLI after the above-mentioned initialization, and in period TI, the output RA. RB are respectively indicated by lXJ and are equal to the outputs AX and BX of the PN synthesizer 20 in the state where the M-sequence generator 10 is initialized as described above.The outputs RA and RB in this state are standby pattern R
It is called X.

FIG. 5 shows a case in which consecutive two bits of the input pattern IP become OOot and oo during periods TI, T2, and T3, and output RA. RB and the outputs IA and IB of the dividing circuit 40 do not match, the output Rl of the coincidence detection circuit 50 maintains a low level, the output OR of the OR gate 65 maintains a low level, and the clock is applied to the output CL2A of the AND gate 62. Therefore, the output CL4A of the frequency divider 63 is kept at a low level, and the D flip-flop 64 is not triggered, and the output DY of the D flip-flop 64 is kept at a high level, and the clock is not obtained at the output CL4C of the OR gate 67. I can't. In period T4, the outputs RA and RB and the outputs IA and IB match, the output Rl of the coincidence detection circuit 50 becomes high level, and the output OR of the OR gate 65 becomes high level and is divided into the output CL2A of the AND gate 62. The output clock CL2 of the frequency generator 61 is obtained. Then, in the next period T5,
At the end of period T4, the output CL2 of AND gate 62
As A falls, the output RA of the multiplexing circuit 30
, RB are respectively 1 as in the periods T1 to T4, but the M sequence generator 10 is
Output A of the PN synthesizer 20 in the initialized state
Y and BY are obtained (the outputs RA and RB in this state are referred to as a standby pattern RY), and the frequency divider 63 is triggered by the fall of the output CL2A of the AND gate 62 at the end of the period T4, so that the frequency divider 63 is The output CL4A of the frequency divider 63 becomes high level, the output OR of the OR gate 65 becomes high level, and the output clock CL2 of the frequency divider 61 is obtained as the output CL2A of the AND gate 62. However, in the period T5, the outputs RA and RB which become the standby pattern RY and the output IA of the dividing circuit 40
, IB do not match and the output Rl of the match detection circuit 50 becomes a low level, so at the end of the period T5, the frequency divider 63
Even if the D flip-flop 64 is triggered by the falling edge of the output CL4A, the outputs DX and DY of the D flip-flop 64 are not inverted, the output DY remains at a high level, and no clock is obtained at the output CL4C of the OR gate 67. ．． In the period T6, the output CL2A of the AND gate 62 falls at the end of the period T5, so that the standby pattern R is output as the outputs RA and RB of the multiplexing circuit 30.
However, since the standby pattern RX and the outputs IA and IB of the dividing circuit 40 do not match, the match detection circuit 5
0's output Rl holds a low level, the output OR of the OR gate 65 becomes a low level, and the output CL of the AND gate 62
2A cannot receive a clock, and the output of frequency divider 63 is CL4A.
becomes a low level, the D flip-flop 64 is not triggered, and the output DY of the D flip-flop 64 maintains a high level, so that the output CL4C of the OR gate 67 does not receive a clock. In the periods T7, T8, and T9, apart from the specific data content of the input pattern IP, the period T4
, T5, and T6. Period TIO, Tl1. T1
2 and T13 are the same as periods Tl, T2, and T3, respectively, apart from the specific data content of the input pattern IP. Then, in the period T14, similarly to the periods T4 and T7, the outputs RA and RB serving as the standby pattern RX match the outputs IA and IB of the dividing circuit 40, and the coincidence detection circuit 50
The output Rl of becomes high level, and the output O of the OR gate 65 becomes high level.
R becomes high level and the output CL2A of the AND gate 62
, the output clock CL2 of the frequency divider 6l is obtained, and in the next period T15, the standby pattern RY is obtained as the outputs RA and RB of the multiplexing circuit 30, as in periods T5 and T8, and the output clock CL2 of the frequency divider 63 is obtained. The output CL4A of becomes high level, the output OR of the OR gate 65 is kept at high level, and the output clock CL2 of the frequency divider 61 is obtained as the output CL2A of the AND gate 62, but unlike the periods T5 and T8, When the standby pattern RY and the outputs IA and IB of the dividing circuit 40 match, the output Rl of the match detection circuit 50
maintains a high level, at the end of period T15, the D flip-flop 64 is triggered by the fall of the output CL4A of the frequency divider 63, and the outputs DX and DY of the D flip-flop 64 are inverted for the first time. The output DX becomes a high level and the output DY becomes a low level, and the reset state of the frequency divider 66 is released, and the output CL4C of the OR gate 67 falls from a high level to a low level, and the fall is used as a clock M. It is supplied to the sequence generator lO.

Therefore, in the next period 716, the M-sequence generator 10 exits the initialization state and outputs M of the D flip-flops 11.12, 13.
l, M2, M3, M4 become 1, 0, 0.0, and the outputs AX, AY, BX, BY of the PN synthesizer 20 become o, o.
, o, i, and the output CL2A of the AND gate 62 falls at the end of the period T15, so that the outputs AX, BX of the PN synthesizer 20 are obtained as the outputs RA, RB of the multiplexing circuit 30, and the outputs RA, R.B.
become 0, their outputs RA and RB match with the outputs IA and IB of the dividing circuit 40, and the output Rl of the match detection circuit 50 maintains a high level. In the next period Tl7, the output CL2A of the AND gate 62 falls at the end of the period T16, so that the output AY of the PN synthesizer 20,
BY is obtained, the outputs RA and RB become 0.1, the outputs RA and RB match the outputs IA and IB of the division circuit 40, and the output Rl of the coincidence detection circuit 50 maintains a high level.

During periods T16 and T17, the D flip-flop 6
The output DY of the frequency divider 66 is held at a low level, and the output C of the frequency divider 66 is
Similar to the output CL4A of the frequency divider 63, a clock having a frequency of 174 of the input clock CLI is obtained as L4B,
Input clock C as output CL4C of OR gate 6'7
Since a clock with a frequency of 174 of LI is obtained, in the next period 71B, the output Ml of the D flip-flops 11, 12, 13, and 14 as shown in rank 3 in FIG.
, M2, M3, M4 become 0.1.0.0, and the outputs AX, AY, BX, BY of the PN synthesizer 20 become 0.1,
0.1, and the outputs RA, R of the multiplexing circuit 30
The outputs AX and BX of the PN synthesizer 20 are obtained as B, the outputs RA and RB are respectively 0, and the output R
A, RB match the outputs IA, IB of the dividing circuit 40, and the output Rl of the match detection circuit 50 maintains a high level. Furthermore, since the output RI of the coincidence detection circuit 50 is at a high level at the falling edge of the output CL4A of the frequency divider 63 at the end of the period T17, the output DY of the D flip-flop 64
remains at a low level. The same goes for the rest, and the subsequent state is the sixth one.
As shown in the figure. As is clear from this, after the period T14, the outputs RA and RB of the multiplexing circuit 30 and the outputs IA and IB of the dividing circuit 40 match, respectively, and the outputs RA and RB of the multiplexing circuit 30 are multiplexed. is the reference pattern RP, the reference pattern RP is the input pattern I which is the multiplexed output IA and IB of the dividing circuit 40.
Synchronize with P. That is, in the example of FIG. 2, as explained in FIG. 4, the pattern length is 24-1 bits, G(x)=x' +x
In the M sequence expressed by the generator polynomial +l, the data string z1, which is one of the consecutive 4-bit data strings, is l
Since it appears only once in the pattern, by blocking the clock signal supply to the M-sequence generator 10, the data string Z1 can be considered as continuous multiplexed outputs RA and RB of the reference pattern generator 70. Generate standby patterns RX, RY equal to , detect whether the input pattern IP matches the standby patterns RX, RY, and after the input pattern IP matches the standby patterns RX, RY, the M sequence The reference pattern RP is synchronized with the input pattern IP by continuously supplying a clock to the generator 10 and generating the reference pattern RP as the outputs RA and RB of the reference pattern generating section 70. In the case of Fig. 5, the input pattern IP is the standby pattern R.
D flip-flop 6 by matching X, RY
It is at the end of period T15 that the output DY of No. 4 falls from a high level to a low level, but as is clear from FIG.
Since the reference pattern RP synchronized with P can be obtained, if the reference pattern RP synchronized with the input pattern IP can be obtained after a period of time T15, 14×2 bits of the input pattern IP will be required until synchronization. Become.

FIG. 7 shows how the number of bits or time required for synchronization differs depending on which phase timing of the input pattern IP the M-sequence generator 10 is initialized.
The first standby patterns RX in cases 1 to 15 are immediately after the M-sequence generator 10 is initialized, and the standby patterns RX and RYo with bold frames respectively match the input pattern IP. Case 2 is the case shown in FIGS. 5 and 6, Case 1 is the case where the number of bits required for synchronization or the time is maximum, and Case 15 is the case where the number of bits required for synchronization is the maximum. This is the case where the number or time is the minimum. Therefore, in the example shown in FIG. 2, (24-1)x2 bits of the input pattern IP are required at most until synchronization, and if the period of the input clock CLI is Tc, that is, the bits of the input pattern IP and the reference pattern RP. Rate fc=
If 1/Tc, the maximum time required for synchronization is 2(24-
l) It becomes Tc. N=4, L=4. From the above description of the example of FIG. 2 in the case of K=2 and J=4, it will be readily understood that the same applies to the general example of FIG. In other words, in general, the input pattern IP (2'
-1) Requires XK bits and the maximum time required for synchronization is K(
2' 1) Tc.

Therefore, when N=-23, that is, the pattern length of the input pattern and the reference pattern is 223-1 bits (
8M bits), the maximum time required for synchronization is 0.8 seconds in the conventional clockless method, regardless of the bit rate of the input pattern and reference pattern, as shown in equation (1). On the other hand, in the standby system of this invention, K=8, fc=IGHz
When , it becomes 64 milliseconds, K=8, fc=10GH
When N=31, that is, when the pattern length of the input pattern and the reference pattern is 231 bits (2 Gbits), the maximum time required for synchronization is 6.4 milliseconds when In the sampling method, the time is 200 seconds regardless of the bit rate of the input pattern and the reference pattern, as shown in equation (2), whereas in the standby method of this invention, the time is 200 seconds.
= 8, when fc = IGHz, it will be 16 seconds, and K = 8
, fc-10GHz, it becomes 1.6 seconds, and in the standby method of the present invention, even when the input pattern and the reference pattern are extremely long patterns, the maximum time required for synchronization is significantly shortened. ``Effects of the Invention'' As described above, according to the present invention, since a configuration that can be called a standby method is adopted, the maximum time required for synchronization is significantly shortened even when the input pattern and the reference pattern are extremely long patterns.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a general example of the pattern synchronization device of the present invention, and FIG. 2 is a block diagram showing a general example of the pattern synchronization device of the present invention. FIG. 3 is a block diagram showing an example in the case of J=4, and FIG. The figure is a diagram for explaining the properties of the M sequence expressed by the generator polynomial G(x)=x' +x+l with a pattern length of 24-1 bits. FIG. 7, a time chart used to explain the operation of the example, shows how the number of bits or time required for synchronization differs depending on which phase timing of the input pattern the M-sequence generator is initialized in the example of FIG. 2. FIG.

Claims (1)

[Claims] (1) It has an M-sequence generator, and by continuously supplying a clock to this M-sequence generator, the pattern length is 2^
a reference pattern generating section that obtains a reference pattern consisting of an M sequence having a predetermined pattern content of N-1 bits; Data equal to the data content of specific consecutive J bits in one pattern of the series (J is the number where a data string with data content equal to the data content of the J bits appears only once in the above one pattern, where J is N or more) A standby pattern of the content is generated, it is detected whether or not the input pattern consisting of the M sequence matches the standby pattern, and from when the input pattern matches the standby pattern, the M sequence generator is clocked. a detection control section that generates the reference pattern from the reference pattern generation section by continuously supplying the reference pattern.