JPH03219737A - Pattern synchronizing circuit - Google Patents

Abstract

PURPOSE:To synchronize a reference pattern with a low speed data in a short time by latching n-string of low speed data by prescribed P data, arranging the data in the order of original input data and presetting them in parallel with a reference pattern generator. CONSTITUTION:Low speed data of n-string from a multiplex/demultiplex circuit 12 is fed also to a latch means 22. The latch means 22 processes the data so that the total sum of latched data number is number of stages P of shift registers of a reference pattern generator 16 or over. Then a data from the latch means 22 is extracted in the same order as the input data of an input terminal 11 and P sets of data are preset in parallel with P-stages of shift registers of the reference pattern generator 16. Then n-string of low speed data and n-string of reference patterns are compared by each comparator circuit and when coincidence is detected consecutively for P number of times from any of comparator circuits 170, 171, it is discriminated to be in the synchronization state.

Description

Detailed Description of the Invention "Industrial Application Field" This invention is used, for example, to measure the error rate of a digital signal transmission system. This invention relates to a pattern synchronization circuit for synchronization.

``Prior Art'' A synchronous circuit used in a conventional faulty vehicle side regulator is shown in FIG.
The pseudorandom pattern (generally the longest linear code string) is processed by the demultiplexer 12 as n columns (n-2 in this example) of low-speed data φ. ,φ,. The demultiplexing circuit 12 is, for example, a serial-parallel conversion circuit, and a clock synchronized with input data is supplied from a clock input terminal 13 through a clock removal circuit 14 to a frequency dividing circuit 15, and the frequency dividing circuit 15 divides it into 1/n. Both the clocks before and after the frequency division are supplied to the demultiplexing circuit 12, and the input data is separated into n columns of low-speed data. The output of the frequency dividing circuit 15 is also supplied to the reference pattern generator 16, and the reference Bakun generator 16 operates with the frequency-divided clock and sequentially generates n columns of reference patterns whose phases are shifted by 1/n period. do. In this example, reference patterns RD and RD whose phases are shifted by 172 cycles are generated. These reference patterns RD, and the corresponding phase φ of the output low-speed data of the demultiplexing circuit 12 with RD+. and φ are compared by comparison circuits 17° and 171, respectively. The comparison results of these comparison circuits 17° and 171 are supplied to the control circuit 1. The output of the frequency dividing circuit 15 is counted by a counter 19, and the count value of the counter 19 is supplied to the control circuit 18.

Comparison circuit 17°, 17. When a mismatch is output from any one of them, the control circuit 18 resets the counter 19 and controls the clock removal circuit 14 to remove one clock supplied to the frequency division circuit 15. Therefore, the demultiplexer circuit 1
2 output low speed data φ. , φ1 is shifted later by one clock (one data) of the input data.

In other words, the relationship between the low-speed data and the reference pattern deviates.

When a state in which the comparison results of both the comparison circuits 17° and 171 match can be obtained continuously for a predetermined number of times, that is, the number of stages P of the shift registers constituting the reference pattern generator 16 (pattern period is 2'-1 bits). That is, when the count value of the counter 19 reaches P, the control circuit 18 determines that the reference pattern generator 16 is synchronized with the input data, outputs a signal indicating this from the output terminal 19, and then the comparison circuit 17
The error rate is measured by counting the number of mismatches, that is, the number of errors.

Incidentally, the operation side until the reference pattern generator 16 is synchronized is shown in FIG. This is a case where the number n of low-speed data is 2, the period of the reference pattern is 23-1 bits (P=3), and the input data is REC.

DATA, the clock is CLOCK, the output clock of the frequency dividing circuit 15 is CLOCK, the low speed data is φ. ,φ
1. The start of synchronous operation is shown as 5YNC3TART, the reference pattern is shown as RD, RD, the removal command to the clock removal circuit 14 is shown as S, C0NT, and the output indicating that the synchronization state has been achieved is shown as 5YNC. Input data REC, D
Data with “a” added above in ATA is low speed data φ0
The data with rbJ added thereto are separated and converted into low-speed data φ1. The "x" added to the upper right of the data of the reference pattern RD, is the reference pattern RD,,RD.

and low-speed dataφ. , φ1, it is shown that at least one of them is inconsistent.

Therefore, the clock removal commands S and C0NT are generated immediately after the "x", and as a result, the frequency divider circuit 15 stops dividing the clock by one clock, and the divided clocks D and CLOCK are in the same state for two clocks. The "O" attached to the upper right of the data of the reference pattern RD, which appears on the right side of the diagram, represents the reference patterns RDo and RD, and the low-speed data φ. and φ
1 indicates a match, and this match is P=3
When the synchronization is repeated repeatedly, an output 5YNC indicating synchronization is generated.

``Problems to be Solved by the Invention'' In this way, the conventional pattern synchronization circuit compares the corresponding homology between the n-column reference pattern and the n-column low-speed data.
Since the generation of the reference pattern is shifted by one clock when either one of them does not match, in the worst case, it takes one period of the reference pattern of the reference pattern generator 16 to achieve a synchronized state.

Recently, high-speed digital transmission such as optical communication has been carried out, and GH2
It is used in bands. Since the period of the test signal for this digital transmission system is kept the same, the number of bits in one period of the test signal, that is, the longest linear code string, is increased. Furthermore, high-speed data is separated into a plurality of low-speed data to facilitate processing, and the number n of low-speed data is increased. These increase the time required to synchronize the reference pattern generator to the input data, making it impractical.

For example, if the number of bits in one period of the longest linear code string of input data is 22ff1, the frequency f is 2GH, and the number n of low-speed data is 16, one period of the reference pattern is 64 milliseconds, and the longest linear code string is The number of bits in one period is 2”
-1, f is 2 GHz, and n is 11, one period of the reference pattern is about 17 seconds. In this way, the test pattern (
The bit length of -period of input data) is 2''-1 (=2.
In the case of a long pattern such as a focus (15 x 10''), the time required for synchronization can reach up to 17 seconds, making it impractical.

"Means for Solving the Problem" According to the present invention, a latch means for latching n columns of low-speed data in parallel is provided, and the latch means Arrange the latched data in the order of input data, preset the P pieces of data into the P-stage shift register of the reference pattern generator, and then compare the low-speed data with the reference pattern in the comparator circuit to create the reference pattern. Controls the generation phase of the pattern generator.

"Embodiment" FIG. 1 shows an embodiment of the present invention, and parts corresponding to those in FIG. 3 are given the same reference numerals. In the present invention, n columns of low-speed data φ are sent from the demultiplexing circuit 12. .

φ is also supplied to the latch means 22. Latch means 22
is composed of, for example, a RAM, and the total number of latched data is set to be greater than or equal to the number of stages P of the shift register of the reference pattern generator 16.

That is, when the bit length of the period of the reference pattern is (2'1) bits, P or more data are latched into the latch means 22. Thereafter, the data is extracted from the latch means 22 in the same order as the input data of the input terminal 11, and the P pieces of data are preset in parallel to the P-stage shift register of the reference pattern generator 16. Conventionally, each comparison between the low-speed data and the reference pattern of n columns is performed by a comparison circuit, and when a mismatch output occurs as a result of the comparison, one clock input to the reference pattern generator 16 is removed by the clock removal circuit 14. If a match is detected twice in a row from either of the comparison circuits 17° and 17□, it is determined that the synchronization state is established. The above processing is performed by the control circuit 18.

When the input data at the terminal 11 is the longest linear code, the converted low-speed data of n columns becomes the same longest linear code with the phase sequentially shifted by 1/n period. 2 Input data as shown in Figure A is input into two low-speed data φ.

When separated and converted into φ, it becomes as shown in FIG. 2 C2D. In other words, input data and low-speed data φ.

φ and φ are the same pattern, and as can be understood by looking at the part with four consecutive “1”s as shown by the dotted line, for example, φ for input data. is delayed, and φ is further delayed. Therefore, in Fig. 1, the low-speed data φ
. , φ1 are latched in the latch means 22, which are read out, arranged in the same order as the original input data, and preset in the reference pattern generator 16, so that the preset data is the low-speed data φ. , φ1, respectively, that is, the reference pattern generator 1
Reference patterns RD,,RD generated from 6.

are also low-speed data φ. , φ1, but since the amount of advance is relatively small, the comparison circuits 17°, 17. By operating the comparison output of , the reference patterns RD, ,RD, can be converted into low-speed data φ in a short time. , φ1, respectively.

Note that when the input data shown in Figure 2A is separated and converted into four columns of low-speed data, they become as shown in Figure 2C2D, F, and G, which have the same pattern as the input data and are different from the input data. On the other hand, the phase is sequentially delayed. Therefore, in this case as well, if the latch data is latched in the latch means 22 and the latch data is preset in parallel in the reference pattern generator 16 according to the serial data, the four rows of reference patterns obtained at this time are the four rows of low speed It is relatively slightly advanced relative to the data and allows the reference pattern generator 16 to be synchronized to the slow data in a short period of time. Similarly, when input data is generally separated and converted into n columns of low-speed data, the reference pattern generator 16 can be synchronized with the low-speed data in a short time. Note that P pigs are directly fetched from the input data of the terminal 11 into the shift register without being latched by the latch means 22, and the P data of the shift register are sent in parallel to the reference pattern generator 16.
It is also conceivable to preset it to , but this would require a high-speed shift register.

"Effects of the Invention" As described above, according to the present invention, at least a total of P data of n columns of low-speed data are latched, these data are arranged in the order of the original input data, and a reference pattern is generated. At that time, the n-column reference pattern obtained from the reference pattern generator is relatively slightly delayed from the n-column low-speed data, and these reference patterns and low-speed data are compared respectively. However, by delaying the generation phase of the reference pattern generator due to the mismatch, the reference pattern can be synchronized with low-speed data in a short time.

[Brief Description of the Drawings] Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a diagram showing an example of separating and converting input data into multiple low-speed data, and Figure 3 is a diagram showing a conventional synchronous circuit. The block diagram shown in FIG. 4 is a diagram showing waveforms of various parts of an operation example of a conventional synchronous circuit.

Claims (1)

[Claims] (1) Convert input data into n columns (n is an integer of 2 or more) of low-speed data using a demultiplexing circuit, divide the clock synchronized with the input data to 1/n using a frequency divider circuit, and A reference pattern generator is operated using a clock that has been rotated, and the n-column reference patterns whose phases are sequentially shifted by 1/n periods and which are generated by the reference pattern generator have corresponding phases to the n-column low-speed data. are compared by n comparison circuits, and when a mismatch output occurs as a result of the comparison, a control circuit removes the clock supplied to the reference pattern generator to synchronize the reference pattern with the low-speed data. , a latching means is provided for latching the n-column low-speed data until the total number of all data is equal to or greater than a number P related to the bit length (2^P-1) of the pattern period of the reference pattern; Means for arranging the data latched by the latch means in the same order as the input data and presetting it in the P-stage shift register of the reference pattern generator, and then controlling the reference pattern generator by the output of the comparison circuit. is provided in the control circuit, A pattern synchronization circuit characterized in that: