JPH03214998A - Processing system for signal in digital cross connect device - Google Patents

Abstract

PURPOSE:To eliminate need for an adjustment procedure such as frame phase adjustment in the device at system rising or the like and to reduce the hardware scale by inserting an in-equipment frame synchronizing signal to a VT path overhead part not defined in a VT signal (virtual group signal) at a reception interface section so as to attain frame synchronization of the VT signal in the equipment. CONSTITUTION:When a transmission line signal such as a DSI signal is inputted to a reception interface circuit 1, the DSI signal is converted into a VT signal of a VT format in a frame in the equipment by a VT format generating section 11, an in-equipment frame synchronizing signal '11101000' is inserted to an undefined V4 byte in the VT signal by a V4 frame insertion section 12, fed to a switch section 2, in which cross connect processing is implemented and the result is outputted to a transmission interface circuit 3. A V4 synchronization detection section 31 of the transmission interface circuit 3 detects synchronizingly the frame synchronizing signal inserted in the V4 byte in the inputted VT signal for each channel and takes frame synchronization of the inputted VT signal to convert the VT signal of each channel into the DSI signal while applying multiplexing and the result is sent.

Description

[Detailed Description of the Invention] [Summary] Regarding an in-device signal processing method that synchronizes the frame phase within the device in a digital cross-connect device that performs cross-connection by terminating various transmission line signals, The aim is to eliminate the need for troublesome adjustment procedures such as frame phase adjustment and to reduce the hardware scale. In a digital cross-connect device that includes a switch section that cross-connects VT signals from the interface section, and a transmission interface section that converts the VT signal from the switch section into a transmission line signal and outputs it, the VT signal is connected at the reception interface section. An intra-device frame synchronization signal is inserted into the undefined VT path overhead part of the signal. This intra-device frame synchronization signal allows V
It is characterized in that it is configured to perform frame synchronization of T signals.

[Field of Industrial Application] The present invention relates to a digital cross-connect device that terminates various transmission line signals and performs cross-connection while using the SONET-VT format as a frame structure for internal signal processing, and particularly relates to a digital cross-connect device that performs cross-connection while terminating various transmission line signals and using the SONET-VT format as a frame structure for internal signal processing. This invention relates to an intra-device signal processing method for synchronizing intra-device frame phases in a digital cross-connect device.

recent years. In North America, SONET (Syn
Chronous Optical Network
) standard has been newly defined, and therefore the conventional ASYNC-
DS3, DS2, DSIC. Not only transmission line signals such as DS1. Signals that meet this new standard (e.g. QC-1
, OC-3, etc.) is required. In such digital cross-connect equipment. When the SONET-VT format is used for the frame configuration for internal signal processing, this format does not provide a frame synchronization signal, so a signal processing method that can achieve frame synchronization within the equipment is required. There is.

[Prior Art] FIG. 5 shows an ASYNC-DS3. DS2, DSIC.
A schematic configuration of a digital cross-connect device that terminates only conventional transmission line signals such as DS1 is shown. In FIG. 5, 51 is ASYNC-DS3, DS2, DSIC,
A reception interface section 52 receives a transmission line signal such as DS1 and converts it into an internal frame, and a switch section 52 cross-connects the output signal from the reception interface section 51. 53 is a transmission interface unit that converts the signal after cross-connection into a transmission line signal in the switch unit 52 and transmits the signal;
4 is a cross-connect control section that controls the switch section 52.

In this device, a frame format as shown in FIG. 6 is used as a frame structure for internal signal processing. In the figure, φl is a time slot indicating manual input #l of the DSI signal, FO and Fl are frame synchronization signals, and Ci
indicates a stuffing control signal, and Vl indicates a stuffing time slot.

By the way, if you try to terminate the newly specified SONET OC signal using this conventional internal frame format, the transmission capacity of this conventional internal frame will be 0.
Because it does not have the capacity to directly process C signals,
This OC signal cannot be terminated.

For this reason, conventional ASYNC-DS3, DS2. DSIC
．． Not only transmission line signals such as DS1 etc. In order to also terminate the OC signal of the new SONET standard, a new format is required as an internal frame format, and the SONET-VT format can be used for this.

By using this VT format for the internal frame, the VTl. 5 signals and S
TS-1 signals or DS3 signals can be cross-connected without terminating them, and VTl. 5
When terminating V1. It has the advantage that it can be easily converted by simply replacing the V2, V3, and V4 bytes with internal frames.

However, this VT format does not have a frame identification pattern (frame synchronization pattern).
For this reason. If a phase difference occurs in the VT format signal of each channel (hereinafter referred to as VT signal) output from the receiving interface section 5l due to transmission delay or the like within the device, the switching section 52 or the transmitting interface section 53 signal processing cannot be performed properly.

The transmission delay of each channel signal is. For example, as shown in Fig. 7, the arrangement position of the transmitting/receiving interface section of each channel when the digital cross-connect device is installed in one rack, or the transmitting/receiving interface section of each channel when it is distributed in one building. This is caused by the difference in transmission path length caused by the location of the cables, and is unavoidable, so some kind of countermeasure is required to deal with this.

As a countermeasure to this problem, a method using phase absorption means as shown in FIG. 8 has been proposed. In other words. Switch section 52
In this system, a reference timing signal common to all channels is applied to all the transmitting/receiving interface units 55 from the input/output interface unit 55, and a phase absorbing means 56 is provided on the input/output side of the switch unit 52.

In this method. As shown in Figure 9. Switch part 5
In response to the reference timing signal output from 2, the receiving section of each interface section 55 sends out a received signal of its own channel. Due to the difference in transmission path length, the signals of each channel have a phase shift of 1 bit or more when input to the phase absorption means 56, but the phase absorption means 54 adjusts the phase shift of each channel so that this phase shift does not occur. The phase of each signal is adjusted so that all the signals input to the switch section 52 have the same phase.

Furthermore, the signals cross-connected by the switch unit 52 are similarly sent to the transmitting unit of each interface unit 55 using a reference timing signal. A similar phase shift occurs here as well, so the phase absorption means 56 is used to match the phase with the reference timing.

[Problem to be solved by the invention] In the case of the method using the above-mentioned phase absorption means. Since conditions such as the installation position of the interface section differ for each system, it is necessary to adjust the setting amount of the phase absorption means on-site for each system when starting up that system.

This increases the number of configuration steps required during system installation, and
This timing adjustment is difficult because it is delicate and requires specialized knowledge. Furthermore, this phase absorption means also causes an increase in the hardware scale of the apparatus.

Therefore, an object of the present invention is to eliminate the need for troublesome adjustment procedures such as intra-equipment frame phase adjustment at the time of system startup in a digital cross-connect device that uses the SONET-VT format as a frame configuration for internal signal processing, and to eliminate the need for hardware It is an object of the present invention to provide an in-device signal processing method that can also be reduced in scale.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

The in-device signal processing method of the digital cross-connect device according to the present invention includes a receiving interface unit 61 that receives a transmission line signal and converts it into a VT (virtual group) signal having a virtual group frame format, and In a digital cross-connect device that includes a switch section 62 that cross-connects VT signals, and a transmission interface section 63 that converts the VT signal from the switch section 62 into a transmission line signal and outputs it, the reception interface section 6
1, an intra-device frame synchronization signal is inserted into an undefined VT path overhead portion of the VT signal, and this intra-device frame synchronization signal performs frame synchronization of the VT signal within the device.

[Operation] The VT (virtual group) frame format used in SONET is V1, V2, V3, as shown in Figure 1.
, V4 (7) Consists of four VT path overhead sections and four data sections each consisting of a bytes. The number of bytes a in the data section is VTI. For 5 signals, a=26. V
a=35 for T2 signal, a=53 for VT3 signal, VT
For 6 signals, a=107. The contents of the Vl and V2 bytes in the VT path overhead part are already defined, but
V3 and V4 bytes are still undefined.

In the present invention, the reception interface unit 61 inserts a frame synchronization signal for intra-device frame synchronization into the undefined VT path overhead portion of each channel converted into a VT signal using a synchronization signal insertion stage 64. As a result, the VT signal within the device has a timing for each channel, so there is no need for a reference timing signal that is common to all channels as in the prior art.

Each part inside the digital cross-connect device. The internal frame synchronization signal inserted into this undefined VT path overhead section is detected, frame synchronization is established, and signal processing is performed. For example, the transmission interface section 63 uses this internal frame synchronization signal to match the frame phase of the VT signal of each channel after cross-connection at the switch section 62, and
These signals are converted into transmission path signals by multiplexing, etc., and then transmitted.

Although both V3 and V4 bytes can be used as the VT path overhead portion into which the intra-device frame synchronization signal is inserted, it is more appropriate to use the V4 byte. This is because the v3 byte does not necessarily exist every cycle.
This is because when the V3 byte is used for a frame synchronization signal, the frame synchronization characteristics are inferior.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

A digital cross-connect device using an in-device signal processing method as an embodiment of the present invention is shown in FIG. In FIG. 2, ``■'' is a reception interface circuit which receives a DSL signal including a plurality of channels and has a function of converting this DSI signal into a VT signal and outputting it. A plurality of reception interface circuits 1 are provided.

This receiving interface circuit 1 converts a manually generated transmission line signal, such as a DSI signal, into a VT format which is a frame format for internal signal processing. It is configured to include a 4-frame inserting section that inserts a frame synchronization signal into the v4 byte of the data, a pulse generating section 13 that generates various timing clocks in the receiving interface section l, and the like.

These VT signals from the reception interface section 1 are input to the switch circuit 2, respectively. This switch circuit 2 has a function of cross-connecting the VT signals of each channel.

VT of each channel after cross-connection in switch circuit 2
The signal is input to the transmission interface circuit 3. A plurality of such transmission interface circuits are provided. This transmission interface circuit 3 is . v in the input VT signal
Extract the internal frame synchronization signal from the 4-byte part■
4 synchronization detection section 31, a VT/DSI conversion section 32 that performs frame synchronization based on this frame synchronization signal and converts a human-powered VT signal into a transmission line signal (for example, DSI), and various timing clocks in the transmission interface section 3. It is configured to include a pulse generator 33 and the like that generates a narrow pulse.

VTI. used within the device. A frame format of 5 is shown in FIG. In the figure, Vl. V2, V3.
V4 (7) Each byte is a VT path overhead byte (
or service byte). Also, I is the information department, 0
is the overhead part fixed at "0"'. C,,C2 are stuff control bit parts,S. ．． S2 is the stuff bit part,
R is a reserve part.

In this VT frame format. The contents of the V1 and v2 bytes have been defined, and an internal frame synchronization signal with a fixed pattern of ゜'l 1 101000- is inserted into the undefined V4 byte, and path check data is inserted into the V3 byte. Ru.

The operation of this embodiment device will be explained below.

When a DSL signal, for example, is input to the reception interface circuit 1 as a transmission path signal, this DSL signal is converted into a VT signal in the VT format, which is an internal frame in the device, in the VT format creation unit l1, and then is converted into a VT signal in the VT format, which is an internal frame in the device. An internal frame synchronization signal "1 1 101000" is inserted into the undefined 4 bytes of this VT signal.

The VT signal with the frame synchronization signal inserted into the v4 byte is then sent to the switch unit 2 where cross-connect processing is performed and output to the transmission interface circuit 3 side.

In the transmission interface circuit 3, the V4 synchronization detector 3l synchronizes the frame synchronization signal inserted into the four bytes of the input VT signal for each channel, and thereby synchronizes the frame of the input VT signal. The VT signals of the channels are multiplexed, converted into Dsi signals, and transmitted.

Note that even if the input signal to the reception interface circuit 1 is an OC signal for which termination is not permitted, only the Vl, V2, V3, and V4 bytes of the VT format in this OC signal can be terminated. An intra-device frame synchronization signal can be inserted into the V4 or V3 byte.

FIG. 4 shows in more detail and concretely an example of the overall configuration of the interface circuit of the digital cross-connect device according to the present invention. In this embodiment, a reception interface circuit and a transmission interface circuit are incorporated into one unit, and each block within the unit has the following functions.

The LB control block 101 mainly performs local loop pack and self-check loopback. It also controls output data.

DEC block 102 is a B8 manufactured by Univola.
The ZS code or AMI data is decoded and converted into NRZ data.

The BPV detection block 103 monitors uni-bolar data and detects and outputs patterns that do not conform to the bi-bolar code rules.

The IN DOWN detection block 104 monitors input data and input clock, and detects no pulse of 175±75 bits.

The AIS control block 105 switches the output data to the memory block 106 when the IN DOWN detection block 104 detects an input cutoff.

The memory block 106 performs phase synchronization and speed conversion of the R side input data with the DAX device internal clock.

The DPC block 107 monitors the phase of the R side memory block 106. Perform staff control.

The stuff control block 108 performs stuff control based on the stuff request output from the DPC block.

MRCK generation block 109 creates a clock for reading data from memory block 106.

The S/P control block 110 stores the data read from the memory block 106 in an 8 format suitable for data processing in subsequent stages.
Convert to bit parallel data.

The ID generation block 111 converts the bus ID input from the microcomputer into a path ID format.

(3) The 3 generation block 112 divides the check data generated by the ID generation block 111 into 8 bits and inserts them into (3) bytes.

Vl. V2 generation blank: 71 13 is V1. Insert NDF, VT size, and 10-bit pointer into the V2 byte.

(4) The 4 generation block 114 inserts a frame synchronization pattern into the v4 byte.

(2) The 5 generation block 115 inserts the results of calculations in the BIP-2 count block into the v5 byte.

The OHB insertion/mask block 116 has Vl, V2. V3
, V4 byte, V5 byte, surplus bits such as l-, R bit, O bit, service bits, etc. are inserted and masked to create VT formatted data.

The BIP-2 counter R block 117 stores Vl, V2 . Parity count is performed on data excluding V3 and V4 bytes.

The P/S conversion block 118 converts parallel data for internal processing blocks into serial data.

SELF control block 119 performs loopback during self-check.

The PGR block 120 creates various pulses used in the receiving side VT format conversion block.

The V4 detection block 121 detects a frame synchronization pattern inserted into the V4 byte from the data after passing through the switch.

A synchronization protection block 122 performs synchronization protection.

Since the S/P conversion block 123 performs internal processing in 8-bit parallel, it converts input serial data into 8-bit parallel data.

The PGS block 124 creates various pulses used in the transmitting side VT format conversion block.

Vl. The V2 drop block 125 detects and outputs Vl and V2 bytes from the input data on the transmitting side.

The pointer detection block 126 is one of the Vl and V2 bytes.
Detects a 0-bit pointer and performs stuff control, etc.

(3) The 3-drop block 127 detects and outputs the V3 byte.

The ID detection block 128 receives the path check data inserted into the V3 byte, synchronizes, and outputs the bus ID.

The ID comparison block 129 compares the bus ID detected and output by the 10 detection block l28 with the reference path ID written by the microcomputer to determine an error.

B I P-2 count S block 130 is Vl, V2
, V3, and V4 are excluded from the parity count of the VT data.

BIT staff control block 131! ．． The CI and C2 bits in the tVT data are monitored, and the Sl and 32 bits are controlled by majority decision on the 3 bits.

The OHB drop block 132 has Vl. V2. V3,V
Overhead bytes such as the v5 byte are detected and output from the VT data excluding 4.

V5 (BIP-2) Drop block 133 is OH
B I P-2 data is detected from the V5 byte output by the B drop block 132 and output.

The BIP-2 comparison block 134 compares V5 (BIP-2
) B I P- outputted at the drop block 133
2 data and the result calculated in the BIP-2 count S block 130 are compared and determined.

The MWCK generation block 135 is the S side memory block 13
Create a clock for writing DSI data to 7.

The MPG S block 136 creates pulses for separating data starting with the V5 byte.

The S-side memory block 137 converts data at the VT1.5 rate to the DSL rate.

The DPLL block 138 monitors the write and read timings in the S-side memory block 137 and digitally generates a clock so that the phases do not cross each other.

DSL data selection block 139 performs selection of DSI output data.

The COD block 140 converts NRZ data into unipolar data (AMI and B8ZS codes can be selected by setting).

The microcomputer interface block 141 interfaces with the microcomputer and performs various settings and monitoring.

The TIM DIV block 141 creates timers for detecting various alarms inside the LSI.

[Effects of the Invention] According to the present invention, it is possible to perform signal processing by performing frame synchronization within the device while using a new SONET signal, thereby eliminating cumbersome processing such as phase adjustment procedures at the time of signal startup. It becomes unnecessary, and it is also possible to reduce the hardware scale by the amount of the phase absorption means.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block diagram showing a digital cross-connect device using an in-device signal processing method as an embodiment of the present invention, and FIG. 3 is a VTI according to the present invention. FIG. 4 is a block diagram showing the digital cross-connect device of the present invention in more detail. FIG. 5 is a block diagram showing the digital cross-connect device of conventional configuration. Figure 7 shows the internal frame format used in conventional equipment. Figure 7 shows the external configuration when digital cross-connect equipment is assembled into one rack. FIG. 8 is a block diagram showing a digital cross-connect device equipped with phase absorption means, and FIG. 9 is a time chart for explaining the phase absorption operation by the device shown in FIG. In the figure, l-...Reception interface circuit 2...Switch circuit 3...Transmission interface circuit l1...VT format creation section 12--v4 Frame insertion section l3...Pulse generation section 3m--V4 Synchronization detection section 32--VT/DSI conversion section 33--Pulse generation section

Claims (1)

[Claims] A receiving interface unit (61) that receives a transmission line signal and converts it into a virtual group signal (VT) having a virtual group frame format;
A digital cross-connect device comprising a switch section (62) for cross-connecting T), and a transmission interface section (63) for converting a virtual group signal from the switch section (62) into a transmission line signal and outputting the signal, The receiving interface section (61) inserts an intra-device frame synchronization signal into an undefined path overhead part of the virtual group signal, so that the intra-device frame synchronization signal performs frame synchronization of the virtual group signal within the device. An in-device signal processing method for a digital cross-connect device, characterized in that: