JPH03215979A - Bidirectional thyristor - Google Patents
Bidirectional thyristorInfo
- Publication number
- JPH03215979A JPH03215979A JP1068490A JP1068490A JPH03215979A JP H03215979 A JPH03215979 A JP H03215979A JP 1068490 A JP1068490 A JP 1068490A JP 1068490 A JP1068490 A JP 1068490A JP H03215979 A JPH03215979 A JP H03215979A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- punch
- thickness
- breakdown strength
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002457 bidirectional effect Effects 0.000 title claims description 12
- 230000015556 catabolic process Effects 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- JCALBVZBIRXHMQ-UHFFFAOYSA-N [[hydroxy-(phosphonoamino)phosphoryl]amino]phosphonic acid Chemical compound OP(O)(=O)NP(O)(=O)NP(O)(O)=O JCALBVZBIRXHMQ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明はPNPNP (NPNPN)両方向サイリスタ
、特に耐圧(■■0)の低圧化と静電容量の低減化に関
するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a PNPNP (NPNPN) bidirectional thyristor, particularly to lowering the withstand voltage (■■0) and reducing the capacitance.
(従来の技術)
第1図(a)に示す如き基本構造をもつ両方向サイリス
ク、即ちP型半導体基板の両面にN.層とN2層を形成
し、更にN,,N.層中の一部に表面に露呈するP,,
P2層を形成して、金属電極1゛T2により前記P1層
とN,層及びP2層とN2層をそれぞれ短絡した構造の
5層構造をもち、以下のように動作する両方向サイリス
タはよく知られている。(Prior Art) A bidirectional silicon risk having the basic structure as shown in FIG. 1(a), that is, N. layer and N2 layer, and further N,,N. P exposed on the surface in a part of the layer,
A bidirectional thyristor is well known, which has a five-layer structure in which a P2 layer is formed and the P1 layer and N layer and the P2 layer and N2 layer are short-circuited by a metal electrode 1'T2, respectively, and operates as follows. ing.
第1図(a)の拡散断面図中に示す矢印方向の電流を流
す方向の電圧が印加されるものとする。この電圧が接合
J3の耐圧(vno)を超えると接合J3を通って電流
が流れ出ず。するとこの電流のうちN2層を横方向に流
れる電流成分■2と、横方向抵抗Rにもとづく電圧降下
が接合J4を順ハイアスしてP2層より正孔の注入を生
じさせる。このため第1図(b)に示す電圧電流特性図
のように電極T,,T2間をターンオンさせる。It is assumed that a voltage is applied in a direction that causes a current to flow in the direction of the arrow shown in the diffusion cross-sectional view of FIG. 1(a). When this voltage exceeds the withstand voltage (vno) of junction J3, no current flows through junction J3. Then, the current component (2) of this current flowing laterally through the N2 layer and the voltage drop based on the lateral resistance R forwardly bias the junction J4, causing holes to be injected from the P2 layer. For this purpose, the electrodes T, T2 are turned on as shown in the voltage-current characteristic diagram shown in FIG. 1(b).
また前記と逆方向の電圧が印加されたときは、N,層を
横方向に流れる電流成分によって接合J ,を順バイア
スして、第1図(b)のように電極TT2間をターンオ
ンさせてスイッチング動作を行乙の両方向1ナイリスタ
ぱ2端子であって使用が簡単であり、しかも小型軽量で
あるため、弱電回路例えば通信回線に接続された各種電
子回路のザージ防護用素子として広く使用されるように
なりつつある。When a voltage in the opposite direction is applied, the junction J is forward biased by the current component flowing laterally through the N layer, turning on the electrode TT2 as shown in Figure 1(b). Since it is a bidirectional one-way resistor and two terminals that perform switching operations, it is easy to use, and is small and lightweight, so it is widely used as a surge protection element for various electronic circuits connected to low-power circuits, such as communication lines. It's starting to look like this.
しかし最近のように電子回路の集積化が進んでその耐電
圧値が低《なるに伴い、両方向サイリスタとして低耐圧
(VBO)のものへの要求が強くなり、また最近のデジ
タル化の進展は静電容量の小さい素子への要求を強めつ
つある。However, as electronic circuits have recently become more integrated and their withstand voltages have become lower, there has been a strong demand for bidirectional thyristors with low withstand voltages (VBO), and the recent progress in digitalization has increased. Demand for elements with low capacitance is increasing.
(従来技術とその問題点)
しかしこのようなアハランシェ降伏による従来の両方向
サイリスタの構造では、第1図(a)のT′F2間の耐
圧亙はP層の比抵抗、即ち不純物濃度によりほぼ一義的
にきまり、不純物濃度が小さくなるとL玉は高くなる。(Prior art and its problems) However, in the structure of a conventional bidirectional thyristor using such ahalanche breakdown, the breakdown voltage difference between T'F2 in FIG. As a general rule, the smaller the impurity concentration, the higher the L ball becomes.
一方素子の静電容量を決定ずる接合.12,.1.の静
電容量は、P層の不純物濃度によってほほ−義的に定ま
り、よく知られるように不純物濃度が小になるとこれに
比例して静電容量も小になる。On the other hand, the junction determines the capacitance of the element. 12,. 1. The capacitance is essentially determined by the impurity concentration of the P layer, and as is well known, as the impurity concentration decreases, the capacitance also decreases in proportion to this.
従って百1圧を低くずるためI)層の不純物濃度を高く
ずると静電容量も大きくなる、所謂1・レー1ζオフの
関係となるので、低剛圧で低静電容量の両方向サイリス
タの実現は難しい。Therefore, if the impurity concentration of the I) layer is increased in order to lower the 101 voltage, the capacitance will also increase, resulting in the so-called 1·Re 1ζ off relationship, so a bidirectional thyristor with low stiffness pressure and low capacitance can be realized. is difficult.
そこでこれを解決する手段として、第1図(a)のP層
の厚みWPを小とすることにより不純物濃度を大として
、耐圧■Roを従来のように接合,J2J3のアハラン
シェ降伏によることなく、N, PN2層のパンチス
ルーによって得るようにする方法が考えられる。Therefore, as a means to solve this problem, the impurity concentration is increased by reducing the thickness WP of the P layer shown in FIG. A possible method is to punch through two layers, N and PN.
しかしこの方法によって所要の低耐圧かつ低静電容量の
素子を得ようとすると、第1図(a)の1)層の厚みW
,が薄くなり過ぎるため製造が困難となり、実現が難し
い。However, when trying to obtain a device with the required low withstand voltage and low capacitance using this method, the thickness W of the layer 1) in Fig. 1(a)
, becomes too thin, making it difficult to manufacture and difficult to realize.
例えばP層の不純物濃度を10”/cc, N. ,
N2層の表面濃度を10′8/cc、その拡散深さを3
0μとし、不純物分布を誤差関数型を仮定してパンチス
ルー電圧を150■にすると、■)層への空乏層の拡が
り、従ってN.,N.層におけるP層の厚みW,は35
μ程度となる。その結果N.,N2層を含めた素子全体
の厚さは100μ程度となるので、現在よく使用されて
いる4114ウエハなどを用いての製造処理には著しい
困難を生ずる。For example, if the impurity concentration of the P layer is 10"/cc, N.
The surface concentration of the N2 layer is 10'8/cc, and its diffusion depth is 3.
If we assume that the impurity distribution is of an error function type and the punch-through voltage is 150μ, then the depletion layer spreads to the layer (■), and therefore the N. ,N. The thickness W of the P layer in the layer is 35
It will be about μ. As a result, N. , the thickness of the entire device including the N2 layers is approximately 100 μm, which poses significant difficulties in manufacturing using 4114 wafers, which are commonly used at present.
(発明の目的)
本発明は前記パンチスルーによる手段を利用して通常の
選択拡散等の公知の手段により、所要の低耐圧かつ低静
電容量の素子を容易に製造しろる構造を提供し、前記デ
ジタル化処理機能をもった集積回路などこの種回路のサ
ーシ防護を確実に行いうる両方向サイリスクの実現を図
ったものである。(Object of the Invention) The present invention provides a structure in which an element with a required low breakdown voltage and low capacitance can be easily manufactured by a known means such as ordinary selective diffusion using the punch-through method. The aim is to realize a two-way security risk that can reliably protect this type of circuit, such as the integrated circuit with the digitalization processing function.
(問題点を解決するための本発明の手段)本発明の特徴
とするところは、5層構造をもつ両方向サイリスクのP
,NP2 (N,PN2 )層の一部に、その耐圧がパ
ンチスルーによって決まる領域を設けることにより、P
層の主体部分の厚み、従って素子の厚みをアハランシェ
降伏による従来素子と同様としたまま、低耐圧の素子を
実現できるようにして、要求される低耐圧と低静電容量
の素子を容易に製造できるよ・うにしたものである。次
に本発明を一実施例により説明する。(Means of the present invention for solving the problems) The present invention is characterized by the fact that the P
, NP2 (N, PN2 ) layer by providing a region whose breakdown voltage is determined by punch-through.
By making it possible to realize a device with low breakdown voltage while keeping the thickness of the main part of the layer, and therefore the thickness of the device, similar to that of conventional devices due to ahalanche breakdown, it is possible to easily manufacture devices with the required low breakdown voltage and low capacitance. It can be done. Next, the present invention will be explained by way of an example.
(実施例)
第2図(a) (b) (c)は本発明の一実施例を示
す平面図(電極の図示を省略)、平面図のA−A’部矢
視拡散断面図及びその等価回路図である。本発明ではP
,,P2層の設定部の反対端部のN,,N2層の一部に
、P層中に突出ずるパンチスル一部分C及びC゛を設け
て、この部分により挾みこまれるP層の部分厚さをP層
の主体部分の厚みW,より薄いW’Pとし、この部分が
接合J2,J3のアハランシェ降伏電圧より低い電圧で
パンチスルーずるようにしたものである。次にその動作
について説明する。(Example) Figures 2 (a), (b), and (c) are a plan view showing an example of the present invention (the electrodes are not shown), a diffusion cross-sectional view taken along the line A-A' in the plan view, and a diffusion cross-sectional view of the plan view. It is an equivalent circuit diagram. In the present invention, P
,, Punch through parts C and C' that protrude into the P layer are provided in a part of the N,, N2 layer at the opposite end of the setting part of the P2 layer, and the thickness of the part of the P layer sandwiched by these parts is The thickness of the main portion of the P layer is W, and the thickness is W'P, which is thinner than that of the main portion of the P layer, so that this portion punches through at a voltage lower than the ahalanche breakdown voltage of the junctions J2 and J3. Next, its operation will be explained.
今第2図(b)図中の矢印方向の電流を流す極性で電圧
が印加されたものとする。すると印加電圧が厚みW’P
に相当ずるパンチスルー電圧に達すると突出部分Cを通
して電流T2,I,が流れ出ず。Now assume that a voltage is applied with a polarity that causes a current to flow in the direction of the arrow in FIG. 2(b). Then, the applied voltage becomes the thickness W'P
When the punch-through voltage corresponding to , is reached, the current T2,I, no longer flows through the protruding portion C.
電流■2が増加ずると、P2層直下のN2層の実効横方
向抵抗Rによる電圧降下により接合J4を順ハイアスす
るため、この部分にP2層より正孔の注入が行われて、
第2図(C)のC部分が先ずパンチスルーサイリスクと
してターンオンする。なおこの場合電流■1は接合J1
を逆ハイアスするのみでターンオンには寄与しない。C
部分がタンーオンすると、第2図(C)の等価回路図の
ようにC部分が補助・リーイリスタとなって他の部分に
ターンオン状態が拡がり、ついには全面におけるクーン
オンに発展する動作を行うもので、上記の動作は構造が
対称であるから、以」二と電圧の印加方向が逆の場合に
おいてもC゜部分により同−の動作が行われる。When the current (2) increases, the voltage drop due to the effective lateral resistance R of the N2 layer directly below the P2 layer causes the junction J4 to be forward-biased, so holes are injected from the P2 layer into this part.
Portion C in FIG. 2(C) is first turned on as a punch-through cyrisk. In this case, the current ■1 is the junction J1
It only reverses high-assistance and does not contribute to turn-on. C
When a part is turned on, part C becomes an auxiliary/reel resistor and the turn-on state spreads to other parts, as shown in the equivalent circuit diagram in Fig. 2 (C). Since the above operation is symmetrical in structure, the same operation is performed by the C° portion even when the direction of voltage application is reversed.
以」二のように本発明素子の耐圧■IloはP層の不純
物濃度とバンチスル一部分c,c’ の厚みW’Pによ
って決まり、同一不純物濃度ではW′,のみで決まるた
め、厚みW“,の選定によって所望の低耐圧化が可能と
なる。As shown in Figure 2 below, the breakdown voltage (Ilo) of the device of the present invention is determined by the impurity concentration of the P layer and the thickness W'P of the bunches c and c', and at the same impurity concentration it is determined only by W', By selecting , it is possible to achieve a desired low breakdown voltage.
また素子の静電容量、従って接合J2,J.の静電容量
は不純物濃度のみによって決まるが、静電容量値に関係
するC,C″部分以外のP層部分、従ってP層の主体部
分の厚みは犬であって不純物濃度は小であるので、静電
容量を小にすることができ、前記1−レードオフの問題
は一挙に解決されて低耐圧であって静電容量の小さい両
方向サイリスタの提供が可能となる。Also, the capacitance of the element and hence the junctions J2, J. The capacitance of is determined only by the impurity concentration, but the thickness of the P layer parts other than the C and C'' parts, which are related to the capacitance value, and therefore the main part of the P layer is small and the impurity concentration is small. , the capacitance can be reduced, the problem of 1-rade-off is solved at once, and a bidirectional thyristor with low breakdown voltage and small capacitance can be provided.
また本発明でばパンチスル一部分c,c’以外のP層部
分、即ちP層の主体部分の厚みを従来のアバランシェ降
伏による素子と同様に厚くでき、素子そのものの厚みを
大にできる。従って前記したP層全体の厚みを薄くする
ことによってパンチスルー構造を得るものに比べて、製
造処理上の困難を著しく少なくできる。Further, according to the present invention, the thickness of the P layer portions other than the punch-through portions c and c', that is, the main portion of the P layer, can be made as thick as in the conventional device using avalanche breakdown, and the thickness of the device itself can be increased. Therefore, compared to the case where the punch-through structure is obtained by reducing the overall thickness of the P layer described above, difficulties in manufacturing processing can be significantly reduced.
これに加えて本発明によれば、ザージ防護に当たって要
求される性能であるサージ電流耐量のばらつきの少ない
素子をうろことができる。即ちサージ電流耐量は第1図
(b)に示すターンオン移行領域における電力損失と、
最初にタンーオンする位置即ち初期点弧位置からの全面
へのターンオン領域の拡がり速度に大きく影響される。In addition, according to the present invention, it is possible to use an element with less variation in surge current resistance, which is a performance required for surge protection. In other words, the surge current withstand capacity is determined by the power loss in the turn-on transition region shown in FIG. 1(b),
It is greatly influenced by the speed at which the turn-on area spreads over the entire surface from the initial turn-on position, that is, the initial ignition position.
しかし従来の素子では点弧位置が一定しないため、サー
ジ電流耐量にばらつきを生じ易い。However, in conventional elements, the ignition position is not constant, which tends to cause variations in surge current withstand capacity.
しかし本発明では初期点弧位置はパンチスルー部分C,
C“に必ず局限されるため、ザージ電流耐量のばらつき
の殆どない両方向サイリスクの提供が可能となる。However, in the present invention, the initial firing position is the punch-through portion C,
Since the surge current is always localized to C", it is possible to provide bidirectional surge risk with almost no variation in surge current resistance.
以−1二本発明の一実施例について説明したが、パンチ
スル一部分c, c’の形成に当たって、第3図断面
図のように出発ウェハのc, c’形成部分を予め薄
く形成しておく手段を採用しうる。Hereinafter, an embodiment of the present invention has been described. In forming the punch through portions c and c', there is a means for forming the starting wafer parts c and c' thin in advance as shown in the sectional view of FIG. 3. can be adopted.
またパンチスルー動作部分をN.PN2バンチスルーダ
イオードPDとすることができる。第4図(a)(b)
はその断面図と等価回路である。Also, the punch-through operation part is N. It can be a PN2 bunch-through diode PD. Figure 4(a)(b)
is its cross-sectional view and equivalent circuit.
またバンチスルー領域の形状位置などは種々の変形が可
能であり、製造に当たって拡散以外の公知の方法を採用
できる。また更に本発明はPNPNP (NPNPN)
両方向サイリスクを基本構造とする複合サイリスタに適
用して効果を挙げることができる。Further, the shape and position of the bunch-through region can be variously modified, and known methods other than diffusion can be employed in manufacturing. Furthermore, the present invention provides PNPNP (NPNPN)
It can be effectively applied to a composite thyristor whose basic structure is a bidirectional thyristor.
(発明の効果)
以上の説明から明らかなように本発明によれば、9
低耐圧であって静電容量が小さく、しかもザージ電流耐
量のばらつきの少ないデジタル信号を扱う集積回路のサ
ージ防護に好適する両方向サイリスタを提供できる。(Effects of the Invention) As is clear from the above description, according to the present invention, 9. Suitable for surge protection of integrated circuits that handle digital signals that have low withstand voltage, small capacitance, and less variation in surge current withstand capacity. Bi-directional thyristors can be provided.
第1図は従来素子の説明図、第2図は本発明の一実施例
の説明図、第3図,第4図は本発明の他の実施例の説明
図である。FIG. 1 is an explanatory diagram of a conventional element, FIG. 2 is an explanatory diagram of one embodiment of the present invention, and FIGS. 3 and 4 are explanatory diagrams of other embodiments of the present invention.
Claims (1)
_2)の5層よりなり、表面に露呈したN_1(P_1
)及びP_1(N_1)層が前記P_1、P_2層とそ
れぞれ短絡されて各々一つの電極をなす両方向サイリス
タにおいて、その耐圧がパンチスルーによって定まる領
域を設けたことを特徴とする両方向サイリスタ。P_1N_1PN_2P_2(N_1P_1NP_2N
It consists of five layers of N_1 (P_1) exposed on the surface.
) and P_1 (N_1) layers are short-circuited with the P_1 and P_2 layers to form one electrode, respectively, and the bidirectional thyristor is characterized in that a region is provided whose breakdown voltage is determined by punch-through.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010684A JPH0685436B2 (en) | 1990-01-22 | 1990-01-22 | Bidirectional thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010684A JPH0685436B2 (en) | 1990-01-22 | 1990-01-22 | Bidirectional thyristor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03215979A true JPH03215979A (en) | 1991-09-20 |
| JPH0685436B2 JPH0685436B2 (en) | 1994-10-26 |
Family
ID=11757093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010684A Expired - Fee Related JPH0685436B2 (en) | 1990-01-22 | 1990-01-22 | Bidirectional thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0685436B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06314781A (en) * | 1992-03-27 | 1994-11-08 | Agency Of Ind Science & Technol | Surge protection device |
| CN108538722A (en) * | 2018-04-03 | 2018-09-14 | 苏州德森瑞芯半导体科技有限公司 | Discharge pipe production method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54114574U (en) * | 1978-01-30 | 1979-08-11 | ||
| JPH01183849A (en) * | 1988-01-19 | 1989-07-21 | Fuji Electric Co Ltd | Bidirectional switching element |
| JPH01307265A (en) * | 1988-06-06 | 1989-12-12 | Nippon Telegr & Teleph Corp <Ntt> | Pnpn surge-preventing device |
-
1990
- 1990-01-22 JP JP2010684A patent/JPH0685436B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54114574U (en) * | 1978-01-30 | 1979-08-11 | ||
| JPH01183849A (en) * | 1988-01-19 | 1989-07-21 | Fuji Electric Co Ltd | Bidirectional switching element |
| JPH01307265A (en) * | 1988-06-06 | 1989-12-12 | Nippon Telegr & Teleph Corp <Ntt> | Pnpn surge-preventing device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06314781A (en) * | 1992-03-27 | 1994-11-08 | Agency Of Ind Science & Technol | Surge protection device |
| CN108538722A (en) * | 2018-04-03 | 2018-09-14 | 苏州德森瑞芯半导体科技有限公司 | Discharge pipe production method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0685436B2 (en) | 1994-10-26 |
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