JPH03216015A - Driver circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a driver circuit for amplifying an input symbol and supplying the amplified current to a load.

[Conventional technology]

4 and 5 are circuit diagrams showing the configuration of a driver buffer circuit including a conventional driver circuit disclosed in, for example, Japanese Patent Laid-Open No. 62-123825. FIG. 2 is a circuit diagram of an improved and even faster circuit. In the figure, (1) is an ECL buffer circuit, (
2) is a level conversion circuit, (3C) is a B i CMOS driver circuit, (3d) is a BiNMOS driver circuit, (11), (12), (16) to (18), (20)
~(23), (36), (37), (42), (43)
, are bibolar transistors, (13), (14), (
15), (19), (24), (25) are resistances, (32
) (38), (46), (47), (50), (51) are PMOS transistors, (33) to (35), (39)
-(41), (52), and (53) are NMOS transistors. In Figure 4, ECL buffer circuit (1)
is constituted by a high-polar ECL circuit, receives the signal A at the ECL level, and outputs complementary signals a and a at the ECL level. The level conversion circuit (2) is composed of two current mirror circuits, and has a complementary signal a of the ECL level.
, a and outputs complementary signals b and b at MOS level. The B i CMOS dryer circuit (3C) is composed of a combination of a bipolar transistor and a CMOS circuit, and receives a complementary signal b. output from the level conversion circuit (2). Used to increase the tribe ability of b.

The ECL buffer circuit (1) includes an ECL input circuit section including bipolar transistors (11), (12) and a resistor (13), and resistors (14), (15), (19) and hyperpolar transistors (16) . (17), (18)
a current switch section including bipolar transistors (20), (21), (22), (23) and a resistor (
24) and an ECL output circuit section including (25).

Normally, the positive side power supply voltage VCC is not set to Ov, and the negative side power supply voltage Vr. gid-4. Set to 5V or -562V. An ECL level signal A is applied to the base of the bipolar transistor (11).

The r}iJ level of signal A is -0.9V, and the "L" level is -1.7■. Bipolar transistors (20) and (21) which are emitter follower transistors
), the ECL level signals a,
a is output. The "H" level of the signals a and a is applied from the power supply voltage vcc to the base of the emitter follower transistor.
A level lowered by the emitter voltage VBE (approximately -0.8
V). The "L" level VL of the signals a and a is determined by the following equation.

V'+. =Vcc I・R VBE
-(L) Here, ■ is the current value of the current flowing through the resistor (14) or (15), and R is the resistance value of the resistor (14) or (15). Also, bipolar transistor (17)
A reference voltage Vaa is applied to the head of the circuit. Reference voltage V
The input threshold value is determined by BB. A reference voltage V CSI is applied to the bases of the bipolar transistors (12), (18), (22), and (23). Reference voltage V
The current values of the current switch section and the ECL output circuit section are determined by the CSI.

The level conversion circuit (2) includes a PMOS transistor (46
), (47) and NMOS transistors (48), (
49), and a second current mirror circuit including PMOS transistors (50), (51) and NMOS transistors (52), (53). A signal a is given to the gates of the PMOS transistors (46) and (51>), and the PMOS transistors (46) and (51>
A signal a is given to the gates 47) and (50). P
MOS transistor (47) and NMOS transistor (
A MOS level signal b is output from the connection point with the PMOS transistor (51) and the NMOSI-transistor (53), and a MOS level signal b is output from the connection point between the PMOS transistor (51) and the NMOSI-transistor (53). The "H" level of the signals b, b is the power supply voltage, and the "L" level is the power supply voltage v6E.

The BiCMOS driver circuit (3C) consists of a PMOS transistor (32) and an NMOSI-transistor (33).
), a second CMOS inverter including a PMOS transistor (38) and an NMOS transistor (39), and a first base control circuit including NMOS transistors (34), (35);
a second base control circuit including NMOS transistors (40) and (41); a bipolar transistor (36);
It consists of (37), (42), and (43). Bipolar transistors (36), (37) and bipolar transistors (42), (43) are connected to the positive side power supply voltage VCC.
and the negative side power supply voltage VEE, respectively, are totem-pole connected.

The first CMOS inharter is a bipolar transistor (
The second CMOS inverter switches and drives the bipolar transistor (42).

The first pace control circuit is a bipolar transistor (37
), and the second base control circuit controls the hess current of the pibora transistor (43).

A signal C at the B i CMOS level is output from the connection point between the bipolar transistors (36) and (37), and a signal C at the B i CMOS level is output from the connection point between the bipolar transistors (42) and (43). . Signal C
, C's "H" level is -0.4V, and "L" level is -4.1v or -4.8v.

The circuit shown in Fig. 5 is a large buffer circuit including a driver circuit aimed at higher speed. Base and level conversion circuit (2) output b. b is directly connected, and level conversion circuit (2) output b is bibolar! - Connected to the base of the transistor (36) and the gate of the NMOS transistor (40), and the level conversion circuit (2)
Output b is connected to the base of the bipolar transistor (42) and the gate of the NMOS transistor (34).

Next, the operation of the circuit shown in FIG. 4 will be explained. here,
The operation when the ECL level signal A changes from the "H" level (-0.9V) to "rL"L/BeA/(-1.7V) will be described.

When the ECL signal A applied to the base of the bipolar transistor (11) changes from the "H" level to the "L" level, the collector potential of the bipolar transistor (16) changes from the "L" level to the "H" level. Conversely, the collector potential of the NPN transistor (17) changes from the "H" level to the "L" level. From this, the emitter potential of the bipolar transistor (21) (signal a) is
The emitter potential (signal a) of the bipolar transistor (20) changes from rH to rH.
Changes from J level to [L] level. As described above,
The "H" level of the signals a and a varies from the power supply voltage vCc to the base-emitter voltage V of the emitter follower transistor.

This is a significantly lower level (approximately -0.8V). Further, the "L" level of the signals a and a is determined by the above equation (1). If the amplitude of the output of the current switch section is 1V, the "L" level of the signals a and a will be -1.8V.

As mentioned above, the signal a changes from the "L" level to the rHJ level, and the signal a changes from the "H" level to the "L" level, so the PMOS} transistors (46) and (51) turn on, and the PMOS Transistors (47) and (50) are turned off. Further, the NMOS transistor (49) is turned on and the NMOS transistor (53) is turned off. Therefore, the signal b output from the level conversion circuit (2) is “L”
” level (power supply voltage V.) to “H” level (power supply voltage Vcc), and signal b changes from rJ level (power supply voltage V.
c) to the "off" level (power supply voltage VEE).

These signals b. The level b is a MOS level. Therefore, conversion from ECL level to MOS level has been performed.

Since the level conversion circuit (2) is composed of MOS transistors, its drive capability is not very large.

Therefore, the next stage B i CMOS driver circuit (
3C), it is necessary to increase the drive capacity. As mentioned above, signal b is at "L" level (power supply voltage V EE
) to "H" level (power supply voltage Vcc),
The PMOS transistor (38) is turned off, and the NMOS transistors (39) and (40) are turned on. This results in
The NMOS transistor (41) is turned off. Therefore, the bipolar transistor (42) is turned off and the bipolar transistor (43) is turned on. As a result, BiC
The signal C output from the MOS driver circuit (3C) becomes "L" level (v, }: +o.4V).

On the other hand, as mentioned above, signal b is at "H" level (power supply voltage V
cc) to "L" level (power supply voltage VEE), the PMOS} transistor (32) turns on, and the NMOS
Transistors (33) and (34) are turned off. This turns on the NMOS transistor (35). Therefore, the bipolar transistor (36) is turned on and the bipolar transistor (37) is turned off. As a result, B
i Signal C output from the CMOS driver circuit (3C) or "H" level (Vcc 0.4 V
) nittle.

Conversely, ECL level signal A or "L" level to "H"
Even when the level changes, the same operation will cause
The signal a becomes the "L" level of the ECL level, and the signal a becomes the "H" level of the ECL level. As a result, the signal b becomes the "L" level of the MOS level, and the signal b becomes the MOS level.
It becomes "H" level of S level. Furthermore, the signal C is B i
The CMOS level becomes “L” level, and the signal c becomes Bi
It becomes the "H" level of the CMOS level.

Next, the operation of the circuit shown in FIG. 5 will be explained.

ECL huffer circuit (l) and level conversion circuit (2)
) is similar to the circuit shown in FIG. 4 above.

When the signal A at the ECL level changes from the "H" level to the "L" level, the signal a becomes the "H" level of the ECL level, and the signal a becomes the "L" level of the ECL level.

As a result, the signal b becomes the "H" level of the MOS level, and the signal b becomes the "H" level of the MOS level.

When the MOS level signal b becomes "H" level and the MOS level signal b becomes "L" level, the bipolar transistor (36) of the B i NMOS driver circuit (3d)
) and the NMOS transistor (40) are turned on, and the bipolar transistor (42) and the NMOS transistor (34) are turned off. Therefore, driver output signal C
becomes the rHJ level of BiCMOS level, and NMOS
Since the transistor (35) is turned on, the bipolar transistor (37) is turned off. Also, the NMOS transistor (40) is turned on and the high voltage transistor (43)
In order to supply a Hose current to
The i CMOS level becomes "L" level, and the NMOS transistor (41) is turned off.

Conversely, when the ECL level signal A changes from the "L" level to the "H" level, the same operation causes the signal a to change to the ECL level, and the signal a changes to the ECL level.
It becomes the "H" level of the CL level. This results in signal b
or becomes the “L” level of the MOS level, and the signal b becomes the MOS level.
The level becomes "H" level. Furthermore, the signal C is B i
The CMOS level becomes “L” level, and the signal C becomes Bi
It becomes the "H" level of the CMOS level.

As mentioned above, the BiNMOS driver circuit (
3d) receives the output signals b and b of the level conversion circuit (2) directly through the bipolar transistors (36) and (42), so the rise time is particularly fast compared to the BiCMOS triher circuit (3C) in Fig. 4. There is an advantage to being.

[Invention or problem to be solved]

Since the conventional triher circuit is configured as shown in FIG. 32), NMOS transistors (33) and (34), and therefore the input capacitance of the BiCMOS driver circuit becomes large, which has the disadvantage that the switching time of the signals b and b becomes slow, which is different from the conventional technology. As explained in the operation example, in order to turn on and off the MOI transistor and then turn on and off the bipolar transistor, B
Another drawback was that the switching time of the iCMOS circuit was also slow. In addition, the output level of the BiCMOS driver circuit is rHJ level is VcC-0.4V, and "L" level is V, l: +0.4V, so the next stage CM
There is also the drawback that through current tends to flow through the OS circuit. In addition, in FIG. 5, the fall time of the output of the BiNMOS driver circuit is determined by the NMOS transistor (34),
(40) is turned on and off, and then the pibora transistors (37) and (43)) are turned on and off, so the rise time is slower than when the pibora transistors (36) and (42) are directly switched. Similarly to FIG. 4, the output level of the BiNMOS driver circuit does not swing fully.

This invention was made in order to solve the above-mentioned problems, and provides a driver circuit that can make the rise and fall times of the driver circuit output the same, operate at high speed, reduce the number of elements, and reduce the layout area. The purpose is to obtain.

[Means to solve the problem]

In the driver circuit according to the present invention, a signal at a first logic level is input to the gate of the first conductive channel type MOS transistor and the base of the second bipolar transistor, and a complementary signal at the first logic level is input to the gate of the first conductive channel type MOS transistor and the base of the second bipolar transistor. , is input to the gate of the first bipolar transistor and the gate of the second first conduction channel type MOS transistor;
and the collector of the second bipolar transistor is connected to the first
the sources of the first and second first conductive channel MOS transistors are connected to a second power source;
The emitter of the first bipolar transistor and the first bipolar transistor
The drain of the conductive channel type MOS transistor is connected and becomes the output signal of the driver circuit, and the emitter of the second bipolar transistor and the second first conductive channel M
The drain of the OS transistor is connected to the other output signal of the driver circuit.

[Effect]

The driver circuit in this invention directly receives the output of the level conversion circuit through bipolar transistors and NMOS transistors, so the input capacitance is small and the number of stages is small, so high-speed operation is possible, and the number of elements is small, so the layout area is reduced. becomes smaller. Furthermore, since it is driven by an NMOS transistor, the triher output "L" level drops to the power supply voltage VεE, so the next-stage PMOSI-run transistor can be driven to a high level, and the through-current in the next stage can be reduced.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. The first is a circuit diagram showing the configuration of an input huffer circuit including a driver circuit. In the figure, (1), (2),
(11) to (25), (36), and (46) to (53) are the same as those shown in the conventional example of FIGS. 4 and 5, and therefore their explanation will be omitted. (3a) is a B i NMOS driver circuit. The configurations of the ECL buffer circuit (1) and level conversion circuit (2) are similar to those of the ECL buffer circuit (1) and level conversion circuit (2) shown in the conventional example of FIGS. 4 and 5.

The ECL buffer circuit (1) is ECL level A8A.
and receives a complementary signal a. of ECL level. Output a.

Normally, the positive side power supply voltage VCC is set to Ov, and the negative side power supply voltage VEE is set to -4.5V or -5.2V.

The level conversion circuit (2) receives ECL level signals a, a through PMOS transistors (47), (50) and (46), (51), respectively, and receives MOS level signals b, b.
This is a CMOS current mirror circuit that outputs .

The BiNMOS driver circuit (3a) receives the MOS level output signal b of the level conversion circuit (2) at the base of the bipolar transistor (36) and the gate of the NMOS transistor (40), and receives the other MOS level output signal b from the bipolar transistor. The driver output signal C is received by the base of the transistor (42) and the gate of the NMOS transistor (34), and the emitter of the bipolar transistor (36) and the drain of the NMOS transistor (34) are connected. The emitter and the drain of the NMOS transistor (40) are connected to output a driver output signal C. The "H" level of driver output signals C and C is B of VCc - 0.4V
The iCMOS level is the MOS level of v6}:. Also bipolar transistor (36), (
The collector of 42) is connected to the power supply voltage VCc, and the collector of NMO
The sources of the S transistors (34) and (40) are connected to the power supply voltage VEE.

Next, the operation of the circuit shown in FIG. 1 will be explained.

First, the ECL level signal A is at "H" level (-0.9
The operation when changing from V) to rLJ level /I/(-0.7V) will be described. In this case, similar to the conventional ECL buffer shown in FIGS. 4 and 5, the signal a changes from the "HI" level to the "H" level, and conversely, the signal a changes from the "H" level to the "H" level. Changes to "L" level. Therefore, the PMOS transistor (46) of the level conversion circuit (2)
, (51), NMoS transistor (49) is on, P
The MOS transistors (47), (50) and the NMOS transistor (53) are turned off, and the output signal b of the level conversion circuit (2) changes from the MOS level "L" level to the "L" level, and b changes from the MOS level to the "L" level. "L" from rH4 level
Change in level.

In the B i NMOS driver circuit (3a),
Since the output signal b of the level conversion circuit (2) changes from "L" level to "H" level, and from "H" level to "L" level, the bipolar transistor (36) and N
MOS}-transistor (40) is turned on, and the bipolar transistor (42) and NMOS transistor (34
) is turned off. Therefore, the output C of the B i NMOS driver circuit (3a) changes from the "L" level to the "H" level, and C changes from the "H" level to the "L" level. Note that the BiNMOS driver circuit (3a) output C. r of C} [J level is VCc-O. It becomes about 4V and becomes "L"
The level drops to power supply voltage VEE.

Here, outputs b and b of the level conversion circuit (2) are only connected to the gates of the bipolar transistors (36) and (42) and the gates of the NMOS transistors (34) and (40). Compared to the i CMOS driver circuit (3C), since the input tolerance is reduced, there is an advantage that the switching time of the outputs b, b of the level conversion circuit (2) is sped up.

In addition, since the outputs b and b of the level conversion circuit (2) are directly driven and outputted by the NMOS transistors (34) and (40),
There is also the advantage that the fall time is faster than the BiNMOS driver circuit (3d) in FIG. 5. Also B
“L” of output c, c of iNMOS driver circuit (3a)
"Since the level drops to the power supply voltage VEE, the PM of the next stage
The OS transistor can be driven at high speed, and the through current in the next stage can be reduced. In addition, the BiNMOS driver circuit (3a) consists of bipolar transistors (36) and (42).
and NMOSI-transistors (34) and (40), the BiCMOS driver circuit (3c
), B i NMOS driver circuit (3d) in Fig. 5
Compared to , the number of elements is smaller and the layout area can be reduced. Also, ECL level signal A is “L”
In the case of changing from the level to the "H" level, the signal a becomes the ECL level rl=4 level by the same operation, and the signal a becomes the ECL level "H" level. As a result, the signal b becomes the "L" level of the MOS level, and the signal b becomes the "H" level of the MOS level. Furthermore, the signal C becomes the "L" level of the MOS level, and the signal C becomes the "H" level of the B i CMOS level.

FIG. 2 is a circuit diagram of a large buffer circuit including a driver circuit showing another embodiment of the present invention. In Figure 2, (1), (2), (11) to (25), (46) to (
53) is equivalent to that shown in FIG. (3b) is a BiPMOS driver circuit, (54) and (56) are P
MOS transistors (55) and (57) are bipolar transistors. The configurations of the ECL buffer circuit (1) and the level conversion circuit (2) are similar to those shown in FIGS. 1, 4, and 5.

The B i PMOS driver circuit (3b) converts the output signal b of the level conversion circuit (2) into a pievora transistor (
55) and the gate of the PMOS transistor (56), and the other output signal b is received by the base of the bipolar transistor (57) and the gate of the PMOS transistor (56).
The drain of the PMOS transistor (54) is connected to the emitter of the bipolar transistor (55) and becomes the output signal C of the BiPMOS driver circuit (3b), and the drain of the PMOS transistor (56) is connected to the emitter of the bipolar transistor (55). ) and becomes the other output signal C of the BiPMOS driver circuit (3b). Also PMOS transistor (54)
The source of (56) is connected to power supply voltage Vcc, and the collectors of bipolar transistors (55) and (57) are connected to power supply voltage VEE.

The operating principle of the BiPMOS driver circuit (3b) in FIG. 2 is as follows.

The output signal b of the level conversion circuit (2) goes from the "HI" level to the "H" level, and the other output signal b goes from the "H" level to the "H" level.
When changing to “L” level, the PMOS transistor (5
4) and the bipolar transistor (57) are turned on,
Since the PMOS transistor (56) and bipolar transistor (55) are turned off, the output signal C of the BiPMOS driver circuit (3b) changes from the "L" level to the "H" level.
The level of the other output signal C changes from the "H" level to the "L" level. Here, the "H" level of C and C rises to the power supply voltage VCC, and the "L" level is VEE + 0.4V.
become. Here, also in the BiPMOS driver circuit (3b) shown in FIG. 2, the level conversion circuit (2) output b,
Since b is only connected to the bases of bipolar transistors (55) and (57) and the gates of PMOS transistors (54) and (56), B i CMOS in FIG.
Since the input capacitance is reduced compared to the driver circuit (3c), there is an advantage that the switching time of the output signals b, b of the level conversion circuit (2) is increased.

In addition, since the outputs b and b of the level conversion circuit (2) are directly driven and outputted by the PMOS transistors (54), (56) and bipolar transistors (55), (57), the B i NMOS driver circuit ( There is also the advantage that the fall time is faster than in 3d).

Further, since the "H" level of the outputs c and c of the B i PMOS driver circuit (3b) rises to the power supply voltage vcc, the NMOS transistor in the next stage can be driven to a high level, and the through current in the next stage can be reduced.

Also, since the BiPMOS driver circuit (3b) is composed of bipolar transistors (55) (57) and PMOS transistors (54) and (56), the BiPMOS driver circuit (3b) is similar to the BiNMOS driver circuit (3a) in FIG.
iCMOS driver circuit (3C) and B i in Figure 5
The number of elements is smaller than that of the NMOS driver circuit (3d), and the layout area can be reduced. Also, the output signal b of the level conversion circuit (2) goes from the "H" level to the "L" level, and the other output signal b goes from the "L" level to the "L" level.
In the same way when changing to "H" level, the BiPMOS
The output signal C of the driver circuit (3b) changes from the "H" level to the "L" level, and the other output signal C changes from the "L" level to the rHJ level.

The BiNMOS driver circuit (3a) shown in FIG. 1 and the B i PMOS driver circuit (3b) shown in FIG.
) can be used for each part of BiCMOS/RAM, for example.

B i CMOS-RAM was developed to obtain a large-capacity memory that can operate at high speed and consumes little power, and is constructed by combining a bibolar element and a CMOS circuit. FIG. 3 shows a RAM (Random Acc
FIG. 2 is a block diagram showing the configuration of essMemory.

In the figure, (60) is a memory cell array, (62) is an X address buffer/decoder, (64) is a Y address buffer/decoder, (66) is an R/W control circuit, and (6) is a Y address buffer/decoder.
8) is a sense amplifier, and (70) is a data output buffer.

In FIG. 3, a memory cell array (60) includes a plurality of word lines and a plurality of bit lines arranged to cross each other, and a memory cell is provided at each intersection of the word lines and bit lines. ing. Memory cell array (60) by X address buffer decoder (62)
One word line is selected, one bit line of the memory cell array (60) is selected by the Y address buffer decoder (64), and the memory cells provided at the intersections of these word lines and bit lines are selected. selected. Data is written to the selected memory cell, or data stored in the selected memory cell is read. Writing or reading of data is selected by the R/W control circuit (66).

The R/W control circuit (66) receives an externally applied write enable signal WE and a chip select signal CS.
In response, it operates.

When writing data, input data Din is input to the selected memory cell via the R/W control circuit (66). Furthermore, when reading data, the data stored in the selected memory cell is detected and amplified by the sense amplifier (68), and is taken out to the outside as output data Dout via the data output buffer (7o).

In the B i CMOS-RAM, the memory cell array is composed of MOS transistors, and peripheral circuits such as address buffers and decoders are composed of bipolar transistors or a combination of bipolar transistors and MOS transistors.

The circuits of FIGS. 1 and 2 include, for example, an X address buffer decoder (62) and a Y address buffer decoder (62).
It can be used for the address buffer included in the decoder (64). In this case, the signal A given to the ECL buffer circuit (1) is an address signal.

In addition, the circuits in FIGS. 1 and 2 are R/W control circuits (
66) Self buffer, WE buffer and Di
Can be used for n buffers. The CS buffer is a circuit that receives the chip select signal CS, the WE buffer is a circuit that receives the write enable signal WE, and the D
The in buffer is a circuit that receives input data Din.

In this way, by applying the B i NMOS driver circuit (3a) shown in FIG. 1 and the BiPMOS driver circuit (3b) shown in FIG. 2 to the B i CMOS-RAM, the memory layout area can be reduced and It becomes possible to further increase the speed.

[Effects of the Invention] As described above, this invention has the effect of achieving B as shown in FIG.
i Since the NMOS driver circuit is configured with a bipolar transistor on the pull-up side and an NMOS transistor on the pull-down side, the rise and fall times of the driver output can be made the same, and it operates at high speed.
Since the J level drops to the power supply voltage VEE, the next stage PMO
The S transistor can be driven at high speed, the through current in the next stage is reduced, and the layout area can be reduced because the number of elements is reduced. Moreover, as shown in FIG. 2, B i P
MOS triher circuit pull-up side PMOSI-
Since the transistor and the pull-down side are constructed with pieborer transistors, the rise and fall times of the driver output can be made the same, and the output rl{J level can reach the power supply voltage vcc, similar to the driver circuit shown in Figure 1. As a result, the next stage NMOS transistor can be driven to a high level.
Further, the through current in the next stage is reduced, and the number of elements is reduced, which has the effect of reducing the layout area.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a large buffer circuit including a driver circuit according to an embodiment of the invention, and FIG. 2 is a circuit diagram showing the configuration of an input buffer circuit including a driver circuit according to another embodiment of the invention. 3 is a block diagram showing the configuration of a RAM to which the driver circuit of the present invention can be applied, FIG. 4 is a circuit diagram showing the configuration of an input buffer circuit including a conventional driver circuit, and FIG. 5 is a block diagram showing the configuration of an input buffer circuit including a conventional driver circuit. 4 is a circuit diagram showing the configuration of a driver buffer circuit including a conventional driver circuit that is an improved version of the driver circuit shown in FIG. 4. FIG. In the figure, (1) is an ECL buffer circuit, (2) is a level conversion circuit, (3a) is a BiNMOS driver circuit, (3b) is a BiPMOS F driver circuit,
(46), (47), (50), (51), (54),
(56) is a PMOS transistor, (48) (4
9) (52) and (53) are NMOS transistors,
(11), (12), (16), (17), (18),
(20), (21), (22), (23), (36),
(37), (42), (43), (55), (57))
are bipolar transistors, (13), (14), (1
5), (19), (24), and (25) are resistances. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A driver circuit for amplifying an input symbol of a first logic level or a second logic level and supplying the amplified current to a load, wherein the input symbol of the first logic level is A second logic level input signal is input to the gate of the first conductive channel type MOS transistor and the base of the second bipolar transistor, and the input signal is inputted to the gate of the second first conductive channel type MOS transistor and the gate of the first bipolar transistor. the first bipolar transistor, the collectors of the first and second bipolar transistors are connected to the first power supply, and the first and second
a source of the first conductive channel type MOS transistor is connected to a second power supply;
The emitter of the first bipolar transistor and the first bipolar transistor
The drain of the conductive channel type MOS transistor is connected and becomes the output of the driver circuit, and the emitter of the second bipolar transistor and the drain of the second first conductive channel type MOS transistor are connected and connected to the other output of the driver circuit. A driver circuit characterized by: