JPH03216016A - Tri-state circuit - Google Patents

Abstract

PURPOSE:To improve the degree of circuit integration by providing a 1st inverter and a 2nd inverter is a tri-state circuit in which drains of a P channel transistor(TR) and an N channel TR are connected for switching control. CONSTITUTION:Controls signals of opposite logic state to each other are inputted respectively to the 1st and the 2nd inverters 11, 12, and one of TRs N2, P3 is turned on, then the other is turned on and when the one is turned off, the other is turned off. Thus, the input signal inputted to an input terminal 13 is fed identically to gates of TRs P1, N1 when the TRs N2, P3 are turned on respectively and the inverse signal of the input signal is extracted at an output terminal 14. On the other hand, when both TRs N2, P3 are turned off, the TRs P1, N1 are respectively turned off and the output terminal 14 goes to a high impedance state. Thus, the number of components is reduced to improve the degree of circuit integration.

Description

[Detailed Description of the Invention] (Overview!!) For example, a gate made of CMOS (complementary MOS)? Regarding the tri-state @ path that is effective for arrays, for the purpose of improving the degree of integration, the drains of the first P-channel transistor and the first N-channel transistor are commonly connected to the output terminal, and the drains of the first P-channel transistor and the first N-channel transistor are In the trice art circuit configured to perform switching of the first N-channel transistor, a second Pf channel transistor and a second N-channel transistor are connected, a control signal is input to each gate, and a control signal is input to the gate of each transistor. a first P-channel transistor whose input signal is supplied to the source of the second N-channel transistor, and which supplies an output signal from the connected drain to the gate of the first P-channel transistor;
an inverter, a third P-channel transistor, and a third N-channel transistor, each of which has an inverted control signal input to its gate.
The second inverter is configured such that an input signal is supplied to the source of the third P-channel transistor, and a second inverter supplies an output signal from commonly connected drains to the gate of the first N-channel transistor.

[Industrial application field]

The present invention relates to a tri-state circuit, and particularly to a tri-state circuit effective for CMOS gate arrays.

Tri-state circuits (three-state circuits) whose output can take one of three states: high level, low level, and high impedance state are widely used in integrated circuits, and are therefore used to improve the integration density of integrated circuits. D for
path configuration is required.

(Prior Art) Part 1!) shows a circuit diagram of an example of a conventional tri-state circuit. In the same figure, two-man powered NAND circuit 1 and two-man powered NOR circuit
The input signal ■ is input to one input terminal of each M path 2, and the control signal C is input to the other input terminal of the two-person NAND circuit 1, and the other input terminal of the two-person NOR circuit 2 A control signal C whose polarity has been inverted by the inverter 3 is input to the input terminal of the control signal C.

In addition, P channel MOS type field effect transistor 4 and N
The drains of the channel MOS field effect transistors 5 are commonly connected to the output terminal, the gate of the transistor 4 is supplied with the output signal of the NAND circuit 1, and the gate of the transistor 5 is supplied with the output signal of the NOR circuit 2. is supplied.

According to the conventional tri-state circuit having such a configuration, when the control signal C is logic "1", the logic inversion signal of the input signal is taken out from the NAND circuit 1, and the NORli
Since the logical inversion signal of the input signal is also taken out from the D path 2, when the input signal is logic "0", transistor 4 is turned off and transistor 5 is turned on, and the output O becomes logic "0". When is logic "1", output 0 also becomes logic "1".

On the other hand, when control signal C is logic “0”, NAN
The logic of the output signal of the O circuit 1 is "1", which turns off the transistor 4, and the logic of the output signal of the NOR circuit 2 is "1".
0", the transistor 5 is also turned off, so the output 0 is in a high impedance state. Therefore, to summarize the above operation, the input signal! control signal C and the output signal 0 are as shown in Fig. 5. There is a relationship as shown.

[Problem to be solved by the invention]

However, the above conventional tri-state circuit
The number of elements in each of the OO path 1 and the NORO path 2 is "4", and the number of elements in the inverter 3 is "2", so the number of elements in the inverter 3 is 12 in total, which is a large number of elements and poses a problem for integration. It is.

The present invention has been made in view of the above points, and an object of the present invention is to provide a tri-state θ path that can improve the degree of integration.

Means for Solving CRtli] FIG. 1 shows a diagram of the principle configuration of the present invention. In the same figure, the first P
A tri-state circuit in which the drains of a channel transistor P1 and a first N-channel transistor N1 are connected to each other and switching is unified is provided with a first inverter 11 and a second inverter 12, respectively. The first CMOS inverter 11 includes a second P-channel transistor P2 and a second N-channel transistor N whose gates and drains are connected to each other.
2, a control signal is input to both gates of transistors P2 and N2, and transistor N2
An input signal is supplied to the source of P+, and an output signal is supplied to the gate of transistor P+.

The second inverter 12 includes a third P-channel transistor P3 and a third N-channel transistor N3 whose gates and drains are connected to each other, and the gates of the transistors P3 and N3 are connected to the above-mentioned control. An inverted signal of the signal is input, the input signal is supplied to the source of the transistor P1, and the output signal is supplied to the gate of the transistor N1.

[Effect]

Since control signals with opposite logics are input to the first and second inverters 11 and 12, when one of the transistors N2 and P8 is on, the other is also on, and when one is off, the other is also off. .

Therefore, when the transistors N2 and P3 are on, the input signal input to the input terminal 13 is transmitted to the transistor P1.
The same input signal is supplied to the gates of N1 and N1, and in this case, an inverted signal of the human input signal is outputted to the output terminal 14.

On the other hand, when transistors N2 and P3 are both off, transistors P1 and N1 are off, respectively, so the output Yasuko 14 becomes high impedance.

Such a tri-state circuit of the present invention can be configured with "6" elements.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the present invention. In the figure, the same components as in FIG. 1 are designated by the same reference numerals. In Fig. 2, input terminal 2 to which control signal C is input.
1 is connected to both gates of transistors P2 and N2, respectively, and connected to both gates of transistors P3 and N3 via a CMOS inverter 22, respectively. CM
The OS inverter 22 consists of a P-channel transistor P4 and an N-channel transistor N4, and the gates of the transistors P4 and N4 are commonly connected to the control signal input terminal 21, and the gates of the transistors P4 and N4 are connected in common to the control signal input terminal 21.
Both drains of transistors P3 and N3 are commonly connected to both gates of transistors P3 and N3, respectively.

Next, the operation of this embodiment will be explained. In FIG. 2, when the control signal C is logic "1", the transistor Pz is turned off and N2 is turned on, and since the output control signal C of the CMOS inverter 22 is logic "0", the transistor P3 is turned off. ON, N3 is OFF. Therefore, the input signal input to the terminal 13 is transmitted to the transistor N2.
The signal is input to the gate of the transistor P1 via the source and drain of the transistor P1, and at the same time, the signal is input to the gate of the transistor N1 via the source and train of the transistor P3. Therefore, at this time, when the logic of the input signal is "0", the transistor P1 is on and the transistor N1 is off, so the logic of the output signal of the layer 14 is "1", and the logic of the input signal is "1". When , the transistor P+ is off and the transistor N+ is on, so the logic of the output signal becomes "0".

Next, the case where the control signal C is logic "0" will be explained. In this case, the transistor P2 is on, the transistor N2 is off, and since the output signal C of the CMOS inverter 22 is logic "1", the transistor P3 is off.
Transistor N3 turns on. Therefore, no matter what the logic of the input signal is, by turning off the transistors NZ and P3, the gate input signal a of the transistor P1 becomes logic "1" regardless of the input signal. The gate input signal b of the transistor N1 becomes logic "0". As a result, when the control signal C is logic "0", the transistors P1 and N+ are each turned off, so that the terminal 14 is in a high impedance state (high 2).

The operations of this embodiment described above are summarized in a table as shown in the third WJ. In the figure, "input" indicates a human input signal at the terminal 21, and rXJ may be either logic "0" or "1" (in other words, it is unrelated to the input signal).

According to this embodiment, it can be constructed from eight elements in total, and the number of elements can be reduced compared to the conventional tri-state circuit shown in FIG. 4, thereby improving the degree of integration. .

A similar circuit that has been known in the past is a clocked inverter circuit, in which the final output stage consists of a CMOS inverter to which an input signal is supplied and its CMOS inverter.
Connected in series above and below the MOS inverter, the control 0-
Since it consists of a total of two transistors with the gate signal connected to the gate, if you try to increase the driving ability,
It is necessary to increase the area of the transistors constituting the CMOS inverter accordingly, and even if the number of elements is small, the degree of integration is reduced.

In contrast, according to the invention, the final output stage consists of two transistors P+ . Even if it is made of N+ and increases the driving ability,
The degree of integration can be improved by reducing the number of elements.

It should be noted that the present invention is not limited to the above embodiment, and for example, instead of using a CMOS inverter, other F
Of course, the inverter may be configured by ET.

[911 results of the invention] As described above, according to the present invention, the number of elements can be reduced compared to the conventional circuit, so the circuit scale can be reduced compared to the conventional @ circuit, and the degree of integration can therefore be improved. It has the advantage of being particularly effective when applied to CMOS gate arrays.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is a circuit diagram of an embodiment of the present invention, 3WJ is an explanatory diagram of the operation of Fig. 2, and Fig. 4 is a circuit diagram of an example of a conventional tri-state circuit. , FIG. 5 is an explanatory diagram of the operation of the fourth WJ. In the figure, 11 is a first inverter, 12 is a second inverter, P+-Pz are first to third P-channel transistors, and N1 to N3 are first to third N-channel transistors.

Claims (1)

[Claims] A first P-channel transistor (P_1) and a first N-channel transistor (P_1)
The drains of the channel transistors (N_1) are commonly connected to the output terminal, and the first P-channel transistor (P_1) and the first N-channel transistor (N
_1) In a tri-state circuit configured to control switching, a second P-channel transistor (P_2) and a second N
a channel transistor (N_2), a control signal is input to each gate, and the second
an input signal is supplied to the source of the N-channel transistor (N_2) of the first inverter (11), and a first inverter (11) supplies an output signal from the commonly connected drains to the gate of the first P-channel transistor (P_1); 3 P channel transistor (P_3) and 3rd N
channel transistor (N_3), an inverted signal of the control signal is input to each gate, an input signal is supplied to the source of the third P-channel transistor (P_3), and output from the commonly connected drains. The signal is passed through the first N-channel transistor (N
A tri-state circuit comprising: a second inverter (12) that supplies power to the gate of _1);