JPH03213017A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of wiring while reducing the number of components and to realize miniaturization by forming a 2-input XOR circuit with an inverter, an N-channel MOS transistor(TR) receiving the output of the inverter at its source and a P-channel MOS TR. CONSTITUTION:A 2-input XOR circuit having inputs A, B consists of an inverter 1 inverting the input B, an N-channel MOS TR 3 receiving the input A at its gate and the output of the said inverter as the source input and a P-channel MOS TR 3 receiving said inputs A, B as the gate and source input. Thus, the components of the 2-input XOR circuit are reduced to two MOS TRs and one inverter thereby reducing the number of wiring together with the reduction of the number of the components, and realizing miniaturization of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to the circuit configuration of an exclusive OR circuit thereof.

[Conventional technology]

Figure 3 shows a conventional two-person exclusive OR circuit (hereinafter referred to as XOR).
5.6.
is an inverter, 7.9 is a P-channel type MO3I-transistor, and 8.10 is an N-channel type MOS transistor.
0, the drain and source are commonly connected. A again.

B is the first. The second input, C, is an output, the input A being connected via the inverter 5 to the drain of the transistor 7.8 and directly to the drain of the transistor 9.10. Input B is connected directly to the gates of transistors 8 and 9, and to the gates of transistors 7 and 10 via inverter 6, and the common drain of transistors 7 to IO is output C of the XOR circuit. .

Next, the operation will be explained.

This will be explained with reference to FIG. 2, which is a two-man XOR truth table.

First, when ° "O" is input to input A and "O" is input to input B, the lc point that passed through inverter 5 becomes "1", and the 16 points that passed through inverter 6 also become "1'". The P-channel MOS transistor 9 whose gate is connected to these 16 points is in the off state, and the N-channel MOS transistor IO is in the on state.The P-channel transistor 9 whose gate is connected to the input B is in the on state, and the N-channel transistor 9 is in the on state. Transistor 8 is turned off. That is, P-channel transistor 7 and N-channel transistor 8 are turned off.
Since the P-channel transistor 9 and the N-channel transistor 10 are in the on state, "o" of the input A that has passed through the P-channel transistor 9 appears at the output C.

Next, when "°0'" is input to input A and "l" is input to input A, the lc point becomes "1" and the 16th point becomes "0". Further, P channel transistor 7 and N channel transistor 8 are in an on state, and P channel transistor 9 . The N-channel transistor 10 is in the off state, and the output C has I
1” of point C appears.

Furthermore, when "1" is input to input A and "0" is input to input B, the IC point becomes 0 and the 16 point becomes "'1". Also, transistor 7.8 is in the off state, and transistor 9.10 is in the o state.
It becomes the n state, and "1" of human power A appears in the output.

Finally, when “1” is input to input A and “1” is input to input B, the IC point becomes “0” and the 16th point also becomes “0”. In addition, P channel transistor 7 and N channel transistor 8
n-state, P-channel transistor9. The N-channel transistor 10 is in the off state, and the output C is “
0” appears.

[Problem to be solved by the invention]

Since the conventional two-man power XOR circuit is configured as described above, it has a large number of elements such as four transistors and two inverters, and also has a large number of distribution lines with a large number of elements, which poses an obstacle in the integration of semiconductor devices. It had become.

This invention was made to solve the above-mentioned problems, and the number of elements in the two-man power XOR circuit.

An object of the present invention is to obtain a semiconductor device that can achieve a high degree of integration by reducing the number of wiring lines.

[Means to solve the problem]

A semiconductor device according to the present invention includes a two-power XOR circuit, an inverter to which one of the inputs is connected, an N-channel MOS transistor whose source is connected to the output of the inverter, and whose gate is connected to the other input. is connected to one of the above inputs, the gate is connected to the other of the above inputs, and the drain is connected to the drain of the above transistor.
S transistor, and the commonly connected drain is the output of the two-man power XOR circuit.

[Effect]

In this invention, a two-manpower XOR circuit is constructed using one of the inputs.
an N-channel MOS) transistor whose gate input is the other of the above-mentioned inputs, and a source input which is the output of the inverter; and a P-channel MOS) transistor whose gate input and source input are respectively the above-mentioned inputs. Since the logic output is obtained from the drains of both transistors, the components of the two-man XOR circuit can be reduced to one MOS (MOS) Ranjistaf and one inverter, which reduces the number of elements and the number of wires. As a result, the size of the semiconductor device can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration of a two-manpower XOR circuit according to an embodiment of the present invention, in which l is an inverter connected to the second input B, 2 is a P-channel MO3I-transistor, whose gate is the The source and drain of input A of 1 are connected to input B and output C. Further, 3 is an N-channel MOS transistor whose gate is connected to the above-mentioned human power A, whose source is connected to the output of the above-mentioned inverter 1, and whose drain is connected to the output C.

Next, the operation will be explained according to the truth table shown in FIG.

First, when "0" is input to input A and 0'' is input to input B, P-channel transistor 2 is in the on state, N-channel transistor 3 is in the off state, and the output C has a P-channel transistor The level becomes 0''+Vtp, which is higher by the threshold value Vtp of 2.

Next, when "0" is input to input A and "1'" is input to input B, P-channel transistor 2 is in the on state, N-channel transistor 3 is in the off state, and the output C is
” appears.

If "1'" is input to input A and ゛0pa is input to human power B,
The P-channel transistor 2 is in the off state, the N-channel transistor 3 is in the on state, and the output C has a level of '1'-Vtn, which is lower than the '1' level by the dark value Vtn of the N-channel transistor 3.

Finally, when "1" is input to input A and °"1" is input to input B, P-channel transistor 2 is in the OFF state, N-channel transistor 3 is in the ON state, and the output C is 0'
appears.

Here, “0” + Vtp and “1” −V appearing at output C
By comparing the level tn with the input determination level of the element connected to the output C and controlling V tp and V tn, it can be regarded as "0" and "1", respectively.

In this way, in this embodiment, two
A human-powered XOR circuit includes an inverter 1 that inverts input B;
Since it is composed of an N-channel MOS transistor 3 with input A as a gate input and the output of the inverter as a source input, and a P-channel MOS transistor 2 with the input A and input B as gate and source inputs, the XO can be operated by two people.
The constituent elements of the R circuit can be reduced to two MOS transistors and one inverter, which reduces the number of elements and the number of wires, and the semiconductor device 1 can be made smaller.

In the above embodiment, the influence of the dark value of the MOS transistor appearing on the output C is dealt with by controlling the level of the dark value, but instead of controlling the level of the dark value, a launch circuit is used. may be used to ensure that a "0" or "1" level is obtained in all cases of the truth table of FIG.

FIG. 4 is a diagram for explaining a two-man power XOR circuit having such a configuration. In the figure, 11 is a P-channel MOS transistor, 12 is an N-channel MOS transistor,
These transistors 11 and 12 are connected in series between the power supply and ground, and the connection point is connected to the output C.

Further, 4 is an inverter, the input of which is connected to the output C, and the output thereof to the gates of both the transistors 11 and 12. The transistors 11 and 12 and the inverter 4 constitute a latch circuit.

In this case, in addition to the effect of the above embodiment, input A is 0''',
Even if °0'" is input to input B, 1" is input to input A.
, even if "0" is input to input B, the latch circuit can reliably output the "o" and "1" level to output C, respectively.

In addition, in this embodiment, not only the XOR logic but also the XNOR logic is used at the point D in FIG.
You can also get logic.

〔Effect of the invention〕

As described above, according to the semiconductor device according to the present invention, a two-man power a channel MOS transistor;
It consists of a P-channel MOS transistor with each of the above inputs serving as a gate and a source input, respectively, and a logic output is obtained from the drains of both transistors.
The components of the above two-person XOR circuit are one inverter,
1 N-channel MOS transistor, P-channel MOS
The number of transistors can be reduced to one, which has the effect of reducing the number of elements and wiring, thereby realizing miniaturization.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a two-manpower XOR circuit mounted on a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram of the two-manpower XOR circuit.
FIG. 3 is a diagram showing a truth table of the circuit, FIG. 3 is a configuration diagram of a two-man power XOR circuit in a conventional semiconductor device, and FIG. 4 is a diagram showing a configuration diagram of a two-man power XOR circuit in a semiconductor device according to another embodiment of the present invention. . 1.4 is an inverter, 2 and 11 are P-channel MOS transistors, and 3.12 is an N-channel MOS transistor. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a semiconductor device equipped with an exclusive OR circuit having two inputs, a first and a second, the exclusive OR circuit is configured as an inverter that receives the second input and outputs an inverted signal thereof. , a P-channel MOS transistor having a gate connected to the first input, a source connected to the second input, a gate connected to the first input, a source connected to the output of the inverter, and a drain connected to the drain of the transistor. 1. A semiconductor device comprising N-channel MOS transistors connected to each other, the commonly connected drains of both transistors being the output of the exclusive OR circuit.