JPH03216728A - N-bit comparator - Google Patents

Abstract

PURPOSE:To reduce the scale of a gate by checking whether a bit serial data at every data group is coincident with every successive bit by a coincidence circuit and a decoder. CONSTITUTION:The coincidence of two groups of data Ai and Bi (i=1.2) of n-bit data length is compared by the coincidence circuit 30 at every bit, the result of the comparison is informed of a decoder 31, and the decoder outputs a clock and switches a selector 13 by the output of a JK flip-flop 12 when even just one non-coincidence is generated at every data group. Then, only one bit comparator is sufficient for the n-bit comparator. Thus, an n-bit comparator where the scale of the gate can be reduced can be obtained.

Description

[Detailed Description of the Invention] [Summary] Regarding an n-bit comparison circuit with priority, for the purpose of reducing the gate scale, two series of data Ai and Bi (i = 1, 2) with a data length of n bits are used. A matching circuit matches each bit for each corresponding data set, and the output of the matching circuit is input for each data set, and a clock is output if there is a mismatch in even 1 bit among the n bits of data. A decoder and the output of the decoder as clock power,
, a JK flip-flop that receives two sets of outputs from the matching circuit as inputs, and a selector that receives the two sets of outputs from the matching circuit and selects one of them according to the output of the JK flip-flop. , a comparison circuit that receives the selector output and outputs a carry signal when all n bits of data match, a protection circuit that receives the output of the comparison circuit and applies protection, and a control circuit that controls each of these components. Consisted of.

[Industrial application field] The present invention relates to a prioritized n-bit comparison circuit.

[Prior Art] FIG. 4 is a block diagram of a conventional data transmission/reception system. 1 is a transmitting device, and 2 is a receiving device. The data a that has entered the transmitting device 1 is subjected to a CRC calculation by the CRC calculator 1a, and is then transmitted as data b. On the other hand, data a is also transmitted as is. In receiving device 2, these two
data a and b are received, and the CRC for data a is
A CRC calculation is performed by the calculation unit 2a. The data that entered the receiving side as is is B, and the data that has been subjected to CRC calculation is A.
shall be.

Comparator 2b compares these two data A and B bit by bit. However, the CR of the CRC calculator 2a
Since the timing of starting the C calculation changes, it is difficult to match data A and B. Therefore, as shown in FIG. 5, it is conceivable to provide a plurality of CRC calculators 2a on the receiving side and select the CRC calculator that outputs data Ai that matches data B. That is, the output data At of each CRC calculator 2a is compared with data B, and data that match is selected by the selector 2C.

FIG. 6 is a block diagram of a conventional circuit, showing the configuration of the receiving device 2 shown in FIG. In other words, data B in Figure 5
An example of the configuration of a comparison circuit after data At is shown. In the figure, 10'. Reference numeral 11 is a comparison unit that compares two sets of two data (bit length n) Ai and Bi (i=1, 2) bit by bit (hereinafter, as shown in the figure, COMPI, C
(abbreviated as OMP2). Note that, as shown in FIG. 5, the data Ai and Bi may or may not be the same data. In Figure 6, data A
The case where i is common is shown.

12 is a priority order for outputting a signal to select one of the sets based on a predetermined priority order when there are multiple sets in which all bits match in the comparison results output from the comparison unit 10.11. The circuit uses a JK flip-flop.

The output of COMPI goes into one input of flip-flop 12, and the output of COMP2 goes into the K input.

13 receives the two data comparison results and selects one set based on the output of the JK flip-flop circuit l2.
1 selector. 14 is a protection circuit that receives the output of the selector 13 and applies protection. The protection circuit 14 does not immediately switch the data series to another series even if a state in which all bits of data do not match occurs once, and the state in which all bits of data do not match continues for a predetermined number of times. It functions to switch the data series for the first time.

15 is a comparison section 10, 11.7K flip-flop circuit 1
2 and the protection circuit 14. The operation of the circuit configured as described above will be explained as follows.

All bits of the data (A system, B system) input to the comparison section 10.11 are compared for each set. w47 figure is comparison part 10
It is a figure showing an example of composition. Although only one set is shown in the figure, there are actually two sets of circuits shown in the figure.

The data Ai and Bi of each system that entered the serial/parallel converter 20 and 21 are n parallel data DI,
D2, . . . Dn. The converted data is
Each bit is compared by a comparator 22, and the comparison result is sent to an OR circuit 23. The OR circuit 23 includes n comparators 2
If even one of the two outputs does not match, "0" is output. Only when all bits match, "1" is output.

The flip-flop 11 first sends COMP to the selector 13.
A signal is given to select the l side. and,
While the CMPI bits match, the selector 10 is set to C.
I have selected OMPI. Here, if a mismatch occurs in the bits of COMPI, its output becomes 0, the output of the flip-flop 12 falls from "1" to "0" by the clock from the control circuit 15, and the selector 13 then changes to
The output of OMP2 will be selected. Protection circuit 1
4 protects the data sent from the selector 13.

[Problems to be Solved by the Invention] The conventional priority-based n-bit comparison circuit does not match all bits as shown in FIG. It is necessary to prepare a circuit for comparing discrepancies only for data series set 2, and there is a problem that the gate scale is extremely large.

The present invention has been made in view of these problems, and an object of the present invention is to provide an n-bit comparison circuit that can reduce the gate scale.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 6 are designated by the same reference numerals. In the figure, 30
is two series of data Ai and Bi (i=
1 and 2) are matching circuits that match bit by bit for each corresponding data set, and 31 inputs the output of the matching circuit 30 for each data set, and checks if even 1 bit out of n bits of data does not match. A decoder that outputs a clock if there is one, 12
13 is a JK flip-flop which receives the output of the decoder 31 as a clock input and the two sets of outputs from the coincidence circuit 30 as inputs; A selector that selects one according to the output; 32 a comparison circuit that receives the output of the selector 13 and outputs a carry signal when all n bits of data match; 14 a protection circuit that receives the output of the comparison circuit 32; A circuit 33 is a control circuit that controls each of these components.

[Operation] The matching circuit 30 matches the bit serial data for each data set, and sequentially sends the data to the decoder 31. The JK flip-prop 12 normally selects the pair A and 81. Here, when a mismatch occurs between the pair A and 81, the corresponding output of the matching circuit 30 outputs "0". When the decoder 31 receives this "0", it generates a clock pulse in synchronization with the clock, JK flip-flop 12. As a result, the output of the flip-flop 12 drops from "1" to "0°", and the selectors A and 8
Select pair 2.

The comparison circuit 32 counts the serial data sent from the selector 13 in synchronization with the clock, and when the n-ary counter carries out, it determines that at least one set of data in which all n bits match exists. It shows. The output of the comparison circuit 32 is sent to the protection circuit 14 and is protected. The output of the protection circuit 14 is the detection output DE
It becomes T.

According to the present invention, the coincidence circuit 30 compares the coincidence of data At and Bi bit by bit, and informs the decoder 31 of the comparison result. Since the clock is output and the selector 13 is switched by the output of the JK flip-flop 12, only one n-bit comparison circuit is required.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

Components that are the same as those in FIG. 1 are designated by the same reference numerals.

The embodiment shown in the figure shows a case where there are two sets of data A and B and the bit length is 6. The coincidence circuit 30 is composed of two manually powered EXNOR gates 30a and 30b. Therefore, the gate output becomes "1" when the two inputs Ai and Bi match, and becomes "0°" when they do not match.

The decoder 31 is composed of a NAND gate 31a and D type flip-flops 31b and 31c. The gates 30a and 30b of the matching circuit 30 are connected to the AND gate 31a.
The output of the NAND gate 31a is input as is, and the output of the NAND gate 31a is input to the D input of the first D type flip-flop 3lb (abbreviated as DFFI). A clock is supplied from the control circuit 33 to the clock input of the DFFI.

The Q output of DFFI is input to the clock CK of a second D-type flip-flop 31c (abbreviated as DFF2). The D input of DFF2 is fixed at "1".Then, the JK flip-flop 12 is connected from the Q output of DFF2.
There is a clock to give to. These DFFI, DFF
2 receives a reset signal from the control circuit 33, and when reset, the Q output of each DFF becomes "0". Note that the reset signal is also input to the reset manual R of the JK flip-flop 12.

The selector l3 has one input of the output of each gate of the matching circuit 30, and the other input of the JK flip-flop 12.
OR gate 13a receives the XQ output of
OR gate 1 receives Q output of K flip-flop 12
3b and an AND gate 13c which receives the outputs of these OR gates 13a and 13b.

The comparison circuit 32 includes an AND gate 32a which receives the output Q of the selector 13 at one input, a feedback signal at the other input, and an octal counter 32b (CNTR2) which receives the output of the AND gate 32a at an enable input EN.
) and a D-type flip-flop 32c which receives the carry-out output CO of the counter 32b. The counter 32b has a hexadecimal reset value “1”.
is manually operated, and the load pulse T from the control circuit 33
A preset value is set by LO. Further, the clock of the counter 32b is given from the control circuit 33. The flip-flop 32C relatches the carry output CO of the counter 32b using the latch pulse DECK output from the control circuit 34. Then, the latched signal becomes COPM. This COMP signal is applied to the other input of the gate 1lb.

The control circuit 33 receives the timing signal TiM and the master clock MCK, and generates a clock and a reset pulse CTI.
CO, initial value load pulse TLO and latch pulse DE
Make a CK. The control circuit 33 includes D-type flip-flops 33a to 33C and an octal counter 33d (CNTR
I) and an AND gate 33e. The operation of the circuit configured as described above will be explained below with reference to the timing chart of FIG.

The control circuit 33 receives a master clock MCK as shown in (a) and a timing signal TiM as shown in (b), and receives an initial value load pulse TLO as shown in (C) and an initial value load pulse TLO as shown in (d), respectively. A reset signal CTICO as shown in (e) and a latch pulse DECK as shown in (f) are output. The counter 33d performs hexadecimal counting as shown in (d), and its carryout CTI CO is as shown in (e).

Data A is (g), data Bl and B2 are each (h)
．． Assume that it is as shown in (i). Furthermore, each gate 30a . 30b output J,
K is (j) respectively. Assume that it is as shown in (k). Before starting the comparison, the flip-flops DDFI,
The Q output of DDF2 and JK flip-flop 12 is “o”
become.

As a result, the OR gate 13b opens, so that K is selected as the output of the matching circuit 30. In addition, load pulse TLO
As a result, the initial value of the counter 32b becomes "1". The coincidence output K enters the comparison circuit 32 via the AND gate 13c and enables the counter 32b.

As a result, the counter 32b starts counting from the initial value "1". Assume that a mismatch occurs in the K output at the 6th bit as shown in (k). The output of the NAND gate 31a of the decoder 31 becomes "12". This "1' level is latched to the DFFI, and then the Q output of this DFFI becomes "1" in synchronization with the clock, and at the same time, the DFF2
Q output becomes "1".

As a result, the Q output of the JK flip-flop 12 is “1”
, XQ output becomes "0", and J of the matching circuit 30 output is selected this time. That is, the OR gate 13a is opened and J data is input.

The output Q of the AND gate 13C becomes "0" as soon as K falls to "0", but as soon as the J input is applied, the output Q becomes "0" (p).
The Q output is set to the enable input EN of the counter 32b, and is always enabled when the clock is input and counts the clock.

The comparator circuit 32 starts clock counting from the initial value ゜1'' and outputs a carry-out CO when the count is up.The output Q of the selector 13 is output from the AND gate 3.
The output Q of the selector 13 indicates that there is a matching data set among the data sets. As long as there is a set of data in which all 6 bits match, counter 3 continues to output "1".
2b outputs carryout CO.

This CO is latched by a latch pulse DECK as shown in (f) output from the control circuit 33, and (S)
It is output as a COMP signal as shown in FIG. The output of the flip-flop 32c enters a protection circuit 14 (see FIG. 1), not shown, and is protected.

As described above, according to the present invention, the matching circuit 30 and the decoder 31 can sequentially check whether or not bit-serial data matches each other bit by bit for each data set. A parallel converter is no longer required, and the gate scale can be reduced. Further, by controlling the priority order for each bit, the data set with the highest priority is selected by the selector 12 at the time of 6-bit comparison, so that the detection time can be shortened.

In the above embodiment, the number of data sets is 2 and the bit length (n) is 6.
Although the case has been described as an example, it goes without saying that the present invention is not limited to this.

The present invention can be applied to data of any bit length in any data set. In that case, it is necessary to prepare the same number of matching circuits 30 and JK flip-flops 12 as shown in FIG. 1 for each two data sets.

[Effects of the Invention] As described above in detail, according to the present invention, the matching circuit 30 compares the coincidence of data Ai and Bi bit by bit, and the comparison result is notified to the decoder 31. Since the circuit outputs "0" if even one bit of mismatch occurs in each data set, only one n-bit comparison circuit is required. Therefore, the gate scale can be reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the invention, Fig. 3 is a timing chart showing the operation of each part, and Fig. 4 is a configuration block of a conventional data transmission/reception system. 5 is a configuration block diagram of a conventional data transmission/reception system, FIG. 6 is a configuration block diagram of a conventional circuit, and FIG. 7 is a diagram showing an example of a conventional configuration of a comparison section. In FIG. 1, 12 is a JK flip-flop, 13 is a selector, 14 is a protection circuit, 30 is a matching circuit, 31 is a decoder, 32 is a comparison circuit, and 33 is a control circuit.

Claims (1)

[Claims] Two series of data Ai and Bi (i=1
, 2) are inputted to a matching circuit (30) that matches bit by bit for each corresponding data set, and the output of the matching circuit (30) for each data set is input, and one of the n bits of data is input.
A decoder (31) that outputs a clock when there is a mismatch in bits, and a JK flip-flop that uses the output of the decoder (31) as a clock input and receives two sets of outputs from the matching circuit (30) as inputs. (12), a selector (13) that receives two sets of outputs from the matching circuit (30) and selects one of them according to the output of the JK flip-flop (12); A comparison circuit (32) that outputs a carry signal when all n bits of data match, a protection circuit (14) that receives the output of the comparison circuit (32) and protects it, and controls each of these components. and a control circuit (33).