JPH03216727A - N-bit comparator - Google Patents

Abstract

PURPOSE:To reduce the scale of a gate and to shorten a detection time by providing one n-bit comparator, functioning a priority order for respective bits and selecting the group of data whose priority is the highest when n-bits are compared. CONSTITUTION:The coincidence of data Ai and Bi (i=1-m) of two seqences whose data length in n-bits is compared n a coincidence circuit 30 for respective bits. Then, a comparison result is informed to a decoder 31. Since '0' is outputted, if dissidence occurs even by one bit for respective groups of data in the decoder 31, only one n-bit comparator is required. Then, the group of data whose priority is high is selected when n-bits are compared by functioning priority for respective bits. Thus, the scale of the gate is reduced and the detection time can be shortened.

Description

[Detailed Description of the Invention] [Summary] Regarding an n-bit comparison circuit with priority, the purpose of this is to reduce the gate scale and shorten the detection time. -1
-m) are inputted to a matching circuit that matches bit by bit for each corresponding data set, and the output of the matching circuit for each data set, and if there is a mismatch in even one bit among the n bits of data, " a decoder that outputs "0", a priority circuit that outputs a signal for selecting a data set with a high priority when there are multiple data sets that match the output of the decoder, and m sets of outputs of the matching circuit. a selector that receives the output of the selector and selects one according to the output of the priority circuit; a comparison circuit that receives the selector output and outputs a carry signal when all n bits of data match; and an output of the comparison circuit. The device is composed of a protection circuit that protects the device by receiving it, and a control circuit that controls each of these components.

[Industrial application field] The present invention relates to a prioritized n-bit comparison circuit.

[Conventional Technology] FIG. 4 is a block diagram of a conventional data transmission/reception system. 1 is a transmitting device, and 2 is a receiving device. The data a that has entered the transmitting device l is CRC (Cyclic Re
dundancy Check) CR by calculator 1a
After performing the C calculation, it is transmitted as data b. on the other hand,
Data a is also transmitted as is. The receiving device 2 receives these two data a and b, and performs a CRC calculation on the data a using the CRC calculator 2a. Let B be the data that entered the receiving side as it is, and let A be the data that has been subjected to CRC calculation.

Comparator 2b compares these two data A and B bit by bit. However, since the timing at which the CRC calculator 2a starts the CRC calculation changes, it is difficult to match the data A and B. Therefore, as shown in FIG. 5, it may be possible to provide a plurality of CRC calculators 2a on the receiving side and select the CRC calculator that outputs data Ai that matches data B. In other words, each CRC calculator 2
The output data Ai of a is compared with data B, and matching data is selected by the selector 2c.

FIG. 6 is a block diagram of a conventional circuit, showing the configuration of the receiving device 2 shown in FIG. In other words, data B in Figure 5
An example of the configuration of a comparison circuit after data Ai is shown. In the figure, 10 is two sets of m data (bit length n) A
This is a comparison unit that compares t and Bt (i-1 to m) bit by bit. Note that, as shown in FIG. 5, the data Ai and Bi may be the same data (B in the figure) or may not be the same.

l1 is a priority circuit that outputs a signal to select one of the sets based on a predetermined priority when there are multiple sets in which all bits match in the comparison result output from the comparison unit 10; Reference numeral 12 denotes an m-1 selector that receives m data comparison results and selects one set based on the output of the priority circuit 11. A protection circuit 13 receives the output of the selector 12.

The protection circuit 13 does not immediately switch the data series to another series even if a state in which all bits of data do not match occurs once, and the state in which all bits of data do not match continues for a predetermined number of times. It sometimes closes to switch the data series. 14 is a control circuit that controls the comparator 10, the priority circuit 11, and the protection circuit 13. The operation of the circuit configured as described above will be explained as follows.

All bits of the data (A system, B system) input to the comparison section 10 are compared for each set. FIG. 7 is a diagram showing an example of the conventional configuration of the comparing section 10. In the figure, only one set is shown, but in reality, there are as many circuits as there are m sets. The data Ai, Bi of each system that entered the serial/parallel converter 20.21 is converted into n parallel data Di, D2.
．． ...Converted to Dn. The converted data is compared bit by bit by a comparator 22, and the comparison result is sent to an OR circuit 23. The OR circuit 23 outputs "0" if there is a mismatch in even one of the outputs of the n comparators 22. Outputs “1°” only when all bits match.

The priority circuit 11 receives the m comparison results sent from each system and checks for sets in which all bits match.

If there are a plurality of sets in which all bits match, a signal is output to the selector 12 to select the set with the highest priority among them according to a predetermined priority order. The selector 12 selects one set according to the selection signal from the priority circuit 11 and outputs it. The output result is the protection circuit l3
to go into.

[Problems to be Solved by the Invention] In the conventional n-bit comparison circuit with priorities, it is necessary to prepare circuits for comparing whether or not all bits match or do not match, as shown in FIG. 7, for only m data series sets. The gate size becomes extremely large, and since the one with the highest priority is selected after comparing n bits, there are problems in that the detection time becomes long.

The present invention has been made in view of these problems, and an object of the present invention is to provide an n-bit comparison circuit that can reduce the gate scale and shorten the detection time.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 6 are designated by the same reference numerals. In the figure, 30
is two series of data At and Bi(i-1
- m) are matching circuits that match bit by bit for each corresponding data set, and 31 is a matching circuit 3 for each data set.
A decoder that inputs an output of 0 and outputs "O" if there is a mismatch in even one bit among n bits of data. 11 has a high priority when there are multiple sets of data that match the output of the decoder 31. A priority circuit outputs a signal for selecting a set of data; 12 is a selector that receives the m sets of outputs from the coincidence circuit 30 and selects one according to the output of the priority circuit 11; 32 is the selector; 33 is a protection circuit that receives the output of the comparison circuit 32, and 34 is a control circuit that controls each of these components. m shown in the figure indicates the number of bits of the signal.

[Action matching circuit 30 matches the bit serial data for each data set and sequentially sends it to the decoder 31. The decoder 31 normally outputs "1" (if the data match) for each set of input data, and outputs "0" if a mismatch occurs. The output of the decoder 31 is sent to the priority circuit 11, and the priority circuit 11 outputs a signal for selecting a data set to output "1" from among the outputs of the decoder 31 in a predetermined priority order. do.

The selector 12 selects a data set according to the selection signal from the priority circuit 11 and sends it to the comparison circuit 32.

When a data mismatch occurs in the set selected by the priority circuit 11, the priority circuit 11 outputs a signal to select the data set with the next highest priority from among the data sets of output "1". do. The selector 12 sends such data sets to the comparison circuit 32 while switching them one after another. The comparator circuit 32 counts the serial data in synchronization with the clock, and
When the digit counter carries out, it indicates that there is one set of data in which all of the n bits match. The output of the comparison circuit 32 is sent to the protection circuit 33.
will be sent to and protected.

The output of the protection circuit 33 becomes the detection output DET.

According to the present invention, the coincidence circuit 30 compares the coincidence of data Ai and Bi bit by bit, and informs the decoder 31 of the comparison result. Since "0" is output, only one n-bit comparison circuit is required. Therefore, the gate scale can be reduced. Furthermore, by making the priority order work for each bit, the data set with the highest priority is selected at the time when n bits are compared, so that the detection time can be shortened.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

Components that are the same as those in FIG. 1 are designated by the same reference numerals.

The embodiment shown in the figure shows a case where there are four sets of data A and B and the bit length is six. The coincidence circuit 30 is composed of four EXNOR gates operated by two people. Therefore, when the two inputs Ai and Bi match, the gate output is “
1″.

The decoder 31 includes four sets of AND gates 31a and D-type flip-flops 31b. One input of the AND gate 31a receives the gate output of the coincidence circuit 30, and the other input receives the Q output of the flip-flop 3lb.

The output of the AND gate 31a enters the D input of the flip-flop 3lb. flip flop 3lb
The clock input CK of the control circuit 34 contains the clock from the control circuit 34, and the preset input P thereof contains the preset number a from the control circuit 34.

The U power of each flip-flop 3lb of the decoder 31 is designated as D1 to D4, respectively, and these outputs D1 to D4 enter the latch llg of the priority circuit l1.

The clock from the control circuit 34 enters the AND gate 11b, and the output of the AND gate 11b enters the clock input CK of the latch lla. Among the outputs of the decoder 31, S1 is the output with D1 latched, 82 is the output with D2 latched, 83 is the output with D3, and D4 is the latched output.
If the latched output is 84, these latch outputs 81 to S4 are connected to AND gates 11c to 11 as shown in the figure.
e and orgatellf. A gate circuit consisting of a combination of llg is entered.

The gate circuits are arranged in order of priority (Sl>S2>S3
>S4) is held as "1" and output. For example, first, if S1 is outputting "1", then
If 1 falls to "0" (if a mismatch occurs), then S2, which has the next highest priority, becomes "1". In this way, signals with higher priorities are sequentially selected.

The outputs of the priority circuit 11 are designated as SLI to SL4, respectively.

The selector 12 selects the outputs H1 to H1 of each gate of the coincidence circuit 30.
It is composed of a latch 12a that latches H4, AND gates 12b to 12e that receive the respective outputs Q1 to Q4 of the latch 12a, and an OR gate 12f that receives the outputs of these AND gates 12b to 12e. and gate 12b
The outputs SLI to SL4 of the corresponding priority circuits 11 are input to the other inputs of the filters 12e and 12e, respectively.

The comparison circuit 32 includes an AND gate 32a which receives the output Q of the selector l2 at one input, a feedback signal at the other input, and an octal counter 32b (CNTR2) which receives the output of the AND gate 32a at an enable input EN.
) and a D-type flip-flop 32c which receives the carry-out output CO of the counter 32b.

An octal preset value "1" is input to the counter 32b, and the preset value is set by the load pulse TLO2 from the control circuit 34.
The clock b is given from the control circuit 34. The flip-flop 32C converts the carry output CO of the counter 32b into a latch pulse (C
MPCK). Then, the latched signal becomes COPM. This COMP signal is input to the other input of the gate llb.

The control circuit 34 receives the timing signal TiM and the master clock MCK, and outputs the clock . Initial value load pulse T
Create LO2 and latch pulse (CMPCK). The control circuit 34 includes D type flip-flops 34a to 34d.
, an octal counter 34e (CNTRI), and an AND gate 34f. The operation of the circuit configured as described above will be explained below with reference to the timing chart of FIG.

The control circuit 34 receives a master clock MCK as shown in (a) and a timing signal TiM as shown in (b), and outputs control signals TLOI and TLO2 as shown in (c) and (d), respectively. . The counter 34e is (
Perform the heptadium count (actually 6 counts from the initial value 1) as shown in e), and calculate the carryout CT I C
O has a shape as shown in (f).

The outputs H1 to H4 of each gate of the coincidence circuit 30 are respectively (
It is assumed that the conditions are as shown in h) to (k). 1
For the bit, all sets are "1". The decoder 31 latches these data H1 to H4 using a clock, and its outputs D1 to D4 are all "1" as shown in (IQ) to (0).
It is. When the priority circuit 11 receives these signals D1 to D4, it latches them with a clock and outputs latch outputs 81 to S4.
are as shown in (p) to (s).

Output SL1 of the gate circuit receiving these outputs 81 to S4
~SL4 will be as shown in (t) ~(w),
A signal is given to the selector 12 to select H1 having the highest priority. Selector 12 selects H1,
Output as Q shown in (X).

Next, it is assumed that a mismatch occurs between Al and Bl at the second bit. As a result, the corresponding gate output H1 falls to "0" as shown in (h). The decoder 31 decodes this data, and the output D1 is "g" in synchronization with the clock.
It falls to “0” as shown in . This data D1 is latched in synchronization with the clock, and the output S1 of the latch 11a is (p
) falls to “0” as shown.

The gate circuit in the priority circuit 11 receives the output of the latch 11a and sets the SLI to “0” as shown in (1) to (W).
°, and instead outputs a select signal to the selector 12 in which the next signal SL2 becomes "11".The output Q of the selector 12 is as shown in (x) when Q1 of the latch 12a is "0".
After falling to 0, it falls to ``0'' until the next clock, but at the same time as H2 is selected, it rises to ``1'' again.

Next, there is a mismatch between A2 and 82 at the 6th bit, and H2 becomes (
Assume that the value falls to "0" as shown in i). In response to this, the output D2 of the decoder 31 is (m
), it falls to “0”. When D2 falls to "0", S2 falls to "0" in synchronization with the next clock as shown in (q). As a result, the gate circuit of the priority circuit 11 outputs a select signal to the selector 12 to select H3, which has the next highest priority.

As a result, the selector 12 selects and outputs H3. As a result, the output of the selector 12 temporarily drops to "O" as shown in (X), but rises to "1" again at the same time as H3 is selected. In this way, in the circuit shown in the figure, the data set with the highest priority among the matching data sets Ai and Bi is always selected and sent to the comparison circuit 32.

The comparator circuit 32 starts clock counting from the initial value "1" and outputs a carry-out CO when the count is up. The output Q of the selector 12 is an AND gate 3
2a to the enable manual input EN of the counter 32b, and counts the clock while EN is "1". The output Q of the selector 12 continues to output "1" as long as there is a matching data set among the data sets, so as long as there is a data set that matches all 6 bits, the counter 3
2b counts 6 clocks from the initial value 1 and outputs carry-out CO. This CO is a latch pulse CMPCK as shown in (z) output from the control circuit 34.
is latched by and output as a COMP signal as shown in (2-).

As described above, according to the present invention, the matching circuit 30 and the decoder 31 can sequentially check whether or not the pit serial data matches bit by bit for each data set. A parallel converter is no longer required, and the gate scale can be reduced. Further, by controlling the priority order for each bit, the data set with the highest priority is selected by the selector 12 at the time of 6-bit comparison, so that the detection time can be shortened.

In the above embodiment, the data set (m) is 4 and the bit length (n
) is 6, but it goes without saying that the present invention is not limited to this. The present invention can be applied to data of any bit length in any data set.

[Effects of the Invention] As described above in detail, according to the present invention, the matching circuit 30 compares the coincidence of data Ai and Bi bit by bit, and the comparison result is notified to the decoder 31. Since the circuit outputs "O°" if even one bit of mismatch occurs in each data set, only one n-bit comparison circuit is required. Therefore, the gate scale can be reduced. In addition, by using the priority order for each bit, the data set with the highest priority is selected when n bits are compared.
Detection time can be shortened.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the invention, Fig. 3 is a timing chart showing the operation of each part, and Fig. 4 is a configuration block of a conventional data transmission/reception system. 5 is a configuration block diagram of a conventional data transmission/reception system, FIG. 6 is a configuration block diagram of a conventional circuit, and FIG. 7 is a diagram showing an example of a conventional configuration of a comparison section. In FIG. 1, 11 is a priority circuit, 12 is a selector, 30 is a matching circuit, 31 is a decoder, 32 is a comparison circuit, 33 is a protection circuit, and 34 is a control circuit.

Claims (1)

[Claims] Two series of data Ai and Bi (i=1
~m) are inputted to a matching circuit (30) that matches bit by bit for each corresponding data set, and inputs the output of the matching circuit (30) for each data set, and matches one of the n bits of data.
A decoder that outputs “0” if there is a bit mismatch (
31), a priority circuit (11) that outputs a signal for selecting a data set with a high priority when there are multiple data sets that match the output of the decoder (31), and the matching circuit (30). Priority circuit (11)
A selector that selects one depending on the output of (
12), and a comparison circuit (32) which receives the output of the selector (12) and outputs a carry signal when all n bits of data match.
), a protection circuit (33) that receives and protects the output of the comparison circuit (32), and a control circuit (34) that controls each of these components.