JPH03216863A - Magnetic recorder - Google Patents

Abstract

PURPOSE:To copy a data just as it is with a simple constitution by sharing a clock signal for a recording system and a reproducing system. CONSTITUTION:Recording and reproducing systems in two systems are controlled by one system control circuit 2 in the subject digital audio tape recorder. That is, a control data DCONT and a clock signal EXCK are generated by the system control circuit 2 with a reference of a synchronizing signal SBSY to be outputted from a digital signal processing circuit 4, and are outputted to digital signal processing circuits 6 and 4. Now, the digital signal processing circuits 6 and 4 are connected in cascade, where the control data DCONT inputted to the digital signal processing circuit 6 is transmitted to the following digital signal processing circuit 4, and the control data DCONT inputted in the digital signal processing circuit 4 is fed back to the system control circuit 2. By this method, the regenerative signal processing circuit 6 and the digital signal processing circuit 4 are operated under synchronization, and hence a recording data DADT can be copied simply.

Description

[Detailed Description of the Invention] The present invention will be explained in the following order. 8. Industrial fields of application B. Overview of the invention C. Conventional technology D. Problems to be solved by the invention E. Means for solving the problems (Fig. 1) F. Effects (Fig. 1)
Figure) G Embodiment (Figures 1 to 7) (Gl) First Embodiment (G2) Other Embodiments H Effect of the Invention Applicable to tape recorders.

B. Summary of the Invention The present invention enables a magnetic recording device to use a clock signal in common with the reproducing system to convert reproduced recorded data into a recorded signal, thereby making it possible to copy data in its entirety with a simple method. C. Prior Art Conventionally, some magnetic recording and reproducing apparatuses (hereinafter referred to as digital audio table recorders) are capable of recording and reproducing digital audio signals using a rotating drum.

In such a digital audio table recorder, audio signals can be recorded at high density while effectively avoiding deterioration in sound quality.

D Problems to be Solved by the Invention Incidentally, this type of digital audio tape recorder is capable of recording various information such as time information and editing information of the audio signal in addition to the audio signal. Furthermore, still images and the like can also be recorded using a predetermined subcode area.

Therefore, if this information can be copied in its entirety along with the audio data, it is thought that the usability of the digital audio table recorder can be further improved. Furthermore, if the audio data can be copied exactly as a digital signal without converting it into an analog signal, it is considered that deterioration in sound quality during copying can be effectively avoided.

In this case, it is thought that copying can be easily performed if two systems of recording and reproducing systems are built into one housing, like a conventional tape recorder using a fixed head, so that complete copying can be performed.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a magnetic recording device that can perform complete copying with a simple configuration.

E Means for Solving Problems In order to solve these problems, in the present invention, based on predetermined clock signals CKSEXCK, EXSY,
a reproduction signal processing circuit 6 for reproducing the recorded data DADT;
An error detection and correction code for the recording data DADT is generated based on predetermined clock signals CK, EXCK, and EXSY, and the recording data DADT and the error detection and correction code are used as the recording signal s. a digital signal processing circuit 4 that converts the signal into C and outputs it to the magnetic heads 16A and 16B, and the magnetic head 16A.
, 16B is rotated at a predetermined speed, and the magnetic tape 2 is wound around the rotating drum 12.
0 runs at a predetermined speed, the reproduction signal processing circuit 6, and the digital signal processing circuit 4.
The clock signal generation circuit 4 outputs K, EXCK, and EXSY.

Clock signal CK generated by F-action clock signal generation circuit 4
, EXCK, EXSY are outputted to the reproduction signal processing circuit 6 and the digital signal processing circuit 4, and the clock signals CK,
Based on EXCK, EXSY? When the recorded data DATA is reproduced and the recorded data DATA is converted into the recorded signal S, the reproduced signal processing circuit 6 and the digital signal processing circuit 4 are operated synchronously to easily reproduce the recorded data DADT.
can be copied.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) First Embodiment In FIG. 1, 1 indicates a digital audio table recorder as a whole, and one system control circuit 2 controls two recording and reproducing systems.

That is, the system control circuit 2 generates control data D cost and a clock signal EXCK based on the synchronization signal SBSY output from the digital signal processing circuit 4, and outputs them to the digital signal processing circuits 6 and 4. Here, the digital signal processing circuits 6 and 4 are connected in cascade, and the digital signal processing circuit 4 continues the control data Dco+<t input manually to the digital signal processing circuit 6.
The control data DCONT input to the digital signal processing circuit 4 is fed back to the system control circuit 2. As shown in FIG. 2, the control data DCOIIT is composed of continuous 8-bit serial data in synchronization with the clock signal EXCK, and the entire data is repeated in an interleave cycle in synchronization with the synchronization signal SBSY.

At this time, the control data D CONT assigns the first 8 bits to the master mode byte and the following 8 bits to the slave mode byte, and switches the digital signal processing circuits 4 and 6 set to the master mode and slave mode, respectively, to the master mode. Set the specified operating mode using the byte and slave mode byte. In other words, as shown in FIG. 3, in the master mode byte and slave mode byte, the upper two bits are assigned the mechanism information of the controlled object set to the master mode and slave mode, respectively, and are assigned to the mechanism information of the rotating drums 12 and 10, respectively. diameter and the magnetic heads 16A, 16B and 14A, 14 mounted on the rotating drums 12 and 10.
Four types of mechanism information are transmitted depending on the positional relationship of B.
As a result, in the servo circuits (not shown) to be controlled that are set to master mode and slave mode, winding is performed around rotating drums l2 and 10 and rotating drums 12 and 10, respectively, according to the following 6-bit data. The magnetic tapes 20 and 18 are driven at a predetermined speed. On the other hand, when setting the digital audio tape recorder 1 to the test signal recording mode, the third bit is set to "1". Furthermore, when setting the playback operation or its stop state, set the 4th bit to "O".
or "l", and when setting the recording operation or its standby state, set the fifth bit to "1" or "0", respectively. In addition, there is a normal mode that records and plays at normal playback speed.
In the double speed mode in which recording and reproduction are performed at twice the speed of the normal mode, the sixth bit is switched.

As a result, when the master mode byte and slave mode byte are r-OL-0-J and r-ooooooo J, the controlled objects set to master mode and slave mode, respectively, are set to normal mode recording and playback mode, and the It is set to a state where it can be copied.

On the other hand, when the master mode byte and slave mode byte are r-OL-1-J and r-000100 J, the controlled objects set to master mode and slave mode, respectively, are set to double-speed recording and playback mode. It is set to a state where it can be copied exactly at twice the speed of normal mode.

Note that here the mode byte is r-OL-0-J or [0
1--1-J indicates recording start or recording standby state, respectively.

On the other hand, in the control data D COHT, the bit following the slave mode byte contains frame data etc. (
(hereinafter referred to as recorded information).

At this time, when the digital signal processing circuit 4 or 6 is set to the reproduction mode, the system control circuit 2 stops outputting the recorded information. Instead, the digital signal processing circuit 4 or 6 set to the playback mode outputs recording information, and the entire digital audio tape recorder 1 operates based on the subdata of the magnetic tape 18 or 20. ing.

That is, the 32 bits following the slave mode byte are allocated to format data, and the format data related to the audio signal to be recorded and played back is transmitted. Furthermore, the following 64 bits are allocated to sub ID data, and the program pick-up (PN O l =
P N 0 3 ), data ID (DATA
ID), pack ID (PACK ID), and control 10 (CTL ID).

The next 72 bits are allocated to main ID data, and the subcode data of the main data area is transmitted. In other words, the first 8 bits are assigned to the main ID flag, and the following 16 bits are assigned to the main ID flag, which sequentially represents the format.
D(M[DO), main I that identifies emphasis processing
D (MIDI) and frame address data (FRAM
E ADRS).

Furthermore, the following <16 bits are sequentially displayed: Main ID (MID2) representing the sampling frequency, Main 10 (MfD3) representing the number of signal channels, Main tD (MtD4) identifying the quantization process, Main ID representing the track pitch of the recording track. (MID5), the following 16 bits are assigned to the main ID (MID6) indicating copy prohibition, and the following 1
Assign 6 bits to the main ID (MID7) for back. On the other hand, data related to back data is transmitted in the 112 bits following the main ID data. Note that in the control data D cost, sub ID data and main ID data can be assigned to each recording track having a positive and negative azimuth angle, respectively.

In this manner, the system control circuit 2 repeatedly outputs the entire serial data at the interleave period using the synchronization signal EXSY as a reference, thereby making it possible to switch the operation of the digital audio tape recorder 1 as a whole at the interleave period.

The selection circuit 24 switches contacts according to the master mode byte and slave mode byte, and the externally input audio signal D1 is converted into a digital signal by the analog signal conversion circuit 26. Alternatively, a selection signal of the digital audio signal DADT output from the digital signal processing circuit 6 is output.

That is, as shown in FIG. 4, when the digital signal processing circuits 4 and 6 on the master mode side and the slave mode side are set to the recording mode and the recording standby mode, respectively, the selection circuit 24 selects the contact B and outputs the digital signal. The audio signal DAtlIN is output to the digital signal processing circuit 4. On the other hand, the digital signal processing circuits 4 and 6 on the master mode side and the slave mode side are set to the recording and playback modes, respectively, and the digital signal processing circuit 4 on the master mode side is transferred from the digital signal processing circuit 6 on the slave mode side to the digital signal processing circuit 4 on the master mode side. When copying the audio signal, the selection circuit 24 selects the contact A and outputs the digital audio signal DADT to the digital signal processing circuit 4.

Thereby, the selection circuit 24 selectively inputs the digital audio signal DALIIN or DADT to the digital signal processing circuit 4 according to the operation mode of the digital audio tape recorder l, and outputs the desired digital audio signal DALIIN to the magnetic tape 20. or D.A.D.
It is designed to be able to record T.

On the other hand, the selection circuit 2 switches the contacts according to the master mode byte and slave mode byte, and selectively outputs the digital audio signal DADT output from the digital signal processing circuit 4 or 6 to the digital signal conversion circuit 30, Thereby, the digital audio signal DADT is converted into an analog signal and output.

That is, when setting the digital signal processing circuit 4 on the master mode side to the dubbing mode, playback mode, or recording mode, the selection circuit 28 selects the contact A and selects the digital audio signal 1' output from the digital signal processing circuit 4.
The signal DADT is sent to the outside.

On the other hand, when setting the digital signal processing circuits 4 and 6 on the master mode side and slave mode side to the recording standby state and playback mode, contact B is selected and the digital audio signal output from the digital signal processing circuit 6 is set. Send DADT to the outside.

This allows the digital signal processing circuits 4 and 6 to output their reproduced outputs to the outside as required.

On the other hand, the selection circuit 32 switches the contacts in the same manner as the selection circuit 28, and selects the AES/EBU format? output from the digital signal processing circuits 4 and 6. The selected output of the digital audio signal TX is sent to the outside.

As a result, the digital signal processing circuits 4 and 6 can output the AES/EBU format digital audio signal TX to the outside in addition to the digital audio signal DADT, if necessary.

As shown in FIG. 5, digital signal processing circuits 4 and 6
In the data input/output circuit 40, the system control circuit 2
Control data D, output from. N? is input and stored in a predetermined area of the memory circuit 47.

On the other hand, during reproduction, the data input/output circuit 40 inputs the demodulated subcode data (
In other words, SDSO (consisting of recorded information) is converted into control data Dco
, lT and output.

As a result, the digital signal processing circuits 4 and 6 switch their operations based on the control data DCONT, and when recording, convert the digital audio signal ADDT into the recording signal S■0.
On the other hand, during playback, the playback signal S1 is demodulated and a digital audio signal DADT is output.

That is, as shown in FIG. 6, the data input/output circuit 40 provides control data Dl:l)l to the mode byte register circuit 42 and the data register circuit 43 via the shift register circuit 41. Mode byte register circuit 42
selectively takes in the master mode byte or slave mode byte based on the mode byte clock signal output from the selection circuit 44.

That is, by counting the clock signal EXCK, the clock generation circuits 45M and 45S generate control data D CON? Generates a mode byte clock signal whose signal level rises in synchronization with. The selection circuit 44 selects a mode setting signal SIIIODI (Sκ
oni), the clock generation circuits 45M and 453
Selects and outputs the mode byte clock signal output from. : In the case of the generous embodiment, the mode setting signal S. of the digital signal processing circuits 4 and 6 is . Il+ and S MOD2 are held at rH level and "L" level, respectively, and are adapted to take in master mode and slave mode data into the mode byte register circuit 42, respectively.

The mode byte register circuit 42 outputs the captured mode byte data to the data DTmus, thereby storing the mode byte data in the memory circuit 47.

As a result, the mode byte register circuit 42 sets the digital signal processing circuits 4 and 6 to the operating mode determined by the mode byte. That is, in the first operation mode of the digital audio tape recorder 1 (FIG. 4), the master mode byte is set to playback mode or dubbing mode, and the slave mode byte is set to recording standby.

From this point on, in the digital audio tape recorder 1, the AES/'EBU format digital audio signal TX and the digital audio signal [)
auout is output from the digital signal processing circuit 4, and in the post-recording mode, the magnetic tape 20 can be post-recorded.

On the other hand, in the second operating mode of the digital audio table recorder I, the master mode byte is set to the recording mode, and the slave mode byte is set to a recording standby state. From this point on, in the digital audio tape recorder 1, AES/EBU
The digital audio signal RX or the digital audio signal DAIJIN in this format is sequentially input to the digital signal processing circuit 4 and recorded. On the other hand, in the third operation mode of the digital audio tape recorder 1, the master mode byte is set to a recording standby state, and the slave mode byte is set to a playback mode. From now on, in this digital audio tape recorder, AES/EBU
The digital audio signal RX and the digital audio signal Dma of the same format can be outputted from the digital signal processing circuit 6.

On the other hand, in the fourth operation mode of the digital audio tape recorder 1, the master mode byte is set to the recording mode and the slave mode byte is set to the playback mode. Digital signal processing circuit 6
reproduces the magnetic tape 18 and sends the resulting digital audio signal DADT to the digital signal processing circuit 4.
The information is recorded on the magnetic tape 20 via the magnetic tape 20.

That is, during recording, the data register circuit 43 sequentially takes in data SDSI other than the mode byte of the control data Dcowt and outputs it to the data bus DTius, thereby storing the data SDSI in the memory circuit 47. Also, during dubbing, the data SDS I import operation is stopped. On the other hand, the data register circuit 48 stops operating during recording, but during playback and after-recording, the data path DTmo from the memory circuit 47
Recorded information output to s (i.e. control data D CO
SDSO (matches data other than the mode byte of Mτ)
Import and output. The selection circuit 49 receives the output data of the data register circuit 48 that is input via the selection circuit 50 and the register circuit 51, and the control data D that is input to the shift register circuit 41.
,. Sends a selection output of 1.

As a result, when the digital signal processing circuit 4 or 6 is set to recording mode, the information SDS I necessary for recording is sequentially transferred to the memory circuit in accordance with the control data D COll'r inputted via the shift register circuit 41. The control data DCONY stored in the shift register circuit 47 and input to the shift register circuit 41 is transferred to the following system control circuit 2 or digital signal processing circuit 4 via a selection circuit 49.

On the other hand, when the digital signal processing circuit 4 or 6 is set to the playback mode, the recording force DsO obtained by playing back the magnetic tape 20 or 18 is added to the mode byte and output. The system control circuit 2 or digital signal processing circuit 4 following the digital signal processing circuit 4 or 6 receives the mode byte and recording information SDS.
Control data D, formed by combining O. It is designed to transfer NT.

This allows the system control circuit 2 to perform digital signal processing! By setting one of the digital signal processing circuits 4 or 6 to a recording standby state and setting the other one to a recording mode, the system control circuit 2 generates and outputs recording information SDSI, thereby selectively controlling the digital signal processing circuit 4 or 6. The externally input digital audio signal is converted into the recorded information S.
It can be recorded based on DSI.

On the other hand, if the digital signal processing circuits 4 and 6 are set to the recording and reproducing states, respectively, and the system control circuit 2 stops generating the recording information SDS I, the digital signal processing circuit 4 and the digital signal processing circuit 6 The digital signal DADT output from the digital signal processing circuit 6 can be recorded based on the recorded information SDSo reproduced by the digital signal processing circuit 14.
and 6 are set to the recording side and the reproduction side, respectively, so that an exact copy can be made.

Thus, if the control data [)coMt is transferred together with the recording information SDSO and SDS I as necessary,
By cascading transmission lines with cot<t, the data of the master mode byte and slave mode byte can be transmitted simultaneously, and the data can be easily recopied with a simpler configuration than the conventional one.

Further, at this time, by transmitting the control data D COHT as serial data together with the recording information SDSO and SDS I, the data necessary for recording can be easily transmitted, thereby obtaining the digital audio tape recorder 1 having a simpler configuration as a whole. be able to. Furthermore, the data input/output circuit 40 of the digital signal processing circuit 4 includes a crystal oscillation element X1.
By selectively dividing the oscillation output signals of , X2 and Necessary synchronization signal S
BSY, a clock signal EXSY whose signal level is inverted at the interleave period is generated.

On the other hand, the data input/output circuit 4fC of the digital signal processing circuit 6 inputs the plurality of clock signals CK and EXSY generated in the digital signal processing circuit 4 as the operation reference clock signal of the digital signal processing circuit 6, This allows it to operate in synchronization with the digital signal processing circuit 4.

In this way, when a digital signal is copied between the digital signal processing circuits 4 and 6, the operations of the digital signal processing circuits 4 and 6 can be easily synchronized.

Therefore, digital signals can be transmitted and easily processed.

Furthermore, at this time, the oscillation circuit for clock signal generation can be omitted on the digital signal processing circuit 6 side, and the overall configuration can be simplified accordingly.

Thus, with a simple configuration, it is possible to copy the entire magnetic table 18 using digital signals.

Furthermore, at this time, in the data input/output circuit 40, by switching the frequency division ratio of the clock signal in the normal mode and the double speed mode, part of the frequency of the clock signal EXSY and the clock signal CK in the double speed mode is switched to a higher frequency than in the normal mode. I can return it.

As a result, the digital signal processing circuits 4 and 6 operate at twice the speed in the double speed mode as in the normal mode by operating on the basis of the clock signals EXSY and CK.

In this embodiment, the data input/output circuit 40 transfers output data Do of the shift register circuit 4l to external equipment via tri-state buffer circuits 52 and 53.
The uT and the selection circuit 50 are configured to be capable of inputting and outputting the manual data D0, thereby controlling the operations of the digital signal processing circuits 4 and 6 with the external equipment, thereby simplifying, for example, editing work. ing. The input/output circuit 54 converts the digital audio signal output from the digital signal input/output circuit 55 into AES/EBU.
The digital audio signal TX is converted into a digital audio signal TX and output.

In addition, the input/output circuit 54 on the digital signal processing circuit 4 side converts the AES/EBtJ format digital audio signal RX input to the digital audio tape recorder 1 into a predetermined format digital audio signal and inputs the digital signal. Output circuit 55
Output to.

As a result, the digital audio tape recorder 1
is capable of outputting an AES/EBU format digital audio signal TX in addition to an analog audio signal. The digital signal input/output circuit 55 operates in synchronization with the system clock signal generated by the data input/output circuit 40 of the digital signal processing circuit 4, and operates in synchronization with the system clock signal generated by the data input/output circuit 40 of the digital signal processing circuit 4.
By loading the mode byte output from 7 to the data path DT-us, the operation is switched based on the mode byte.

Furthermore, the digital signal input/output circuit 55 resets a built-in counter circuit using the clock signal EXSY as a reference, and then sequentially counts a predetermined clock signal to create a rotating drum reference signal DREF that is repeated at an interleave period. At this time, the digital signal input/output circuit 55 sets the period of the rotating drum reference signal DREF to 30 (s+sec) and 60 (msec) in the normal mode and long-time mode, respectively, whereas in the double hesitation mode are the rotating drum reference signal DREF in the standard mode and long-time mode, respectively.
Set the period to 15 (msec) and 30 [so sec]. On the other hand, in the servo circuit, the rotating drums 10 and 12 are rotationally driven in synchronization with the rotating drum reference signal DREF, and the magnetic tapes 118 and 20 are rotated.
run at a predetermined speed.

That is, in the servo circuit, the drum motor is driven so that the rotating drums 10 and 12 rotate once in one cycle of the rotating drum reference signal DREF. Furthermore, when reproducing a magnetic tape recorded in a long-time mode, the long-time mode is detected based on the recording information SDSO, and the rotating drums 10 and 12 are controlled to rotate twice in one cycle of the rotating drum reference signal DREF. .

Furthermore, in the servo circuit, the rotating drum reference signal DR
The cab stan motor is driven so that the magnetic tables 18 and 20 travel by two track pitches in one period of EF.

As a result, in the servo circuit, in the double speed mode, the rotating drums 10 and 1 operate at twice the speed of the normal mode.
2. It is adapted to drive the magnetic tapes 18 and 20.

? Furthermore, when reproducing a magnetic tape recorded in the long-time mode, the reproduction signal S is maintained at the same transmission speed as when reproducing a magnetic tape recorded in the standard mode.

Further, during recording, the digital signal input/output circuit 55 selectively inputs the digital audio signal output from the human output circuit 54 or the digital audio signal ADDT output from the analog signal conversion circuit 26, and converts the selectively input digital audio signal into a counter. Blocks are created at an interleave period based on the circuit count value. In other words, in the normal mode, 30
(Digital audio signals are divided into blocks at Il313CE cycles, whereas in long-time mode,
Blocking is performed at a cycle of 0 (■sec).

On the other hand, in the double speed mode, the digital audio signal is divided into blocks at half the period of the standard mode and long time mode, respectively. At this time, the digital signal input/output circuit 55 sequentially outputs the digital audio signal to the memory circuit 47 based on the count value of the counter circuit, thereby interleaving the digital audio signal that has been divided into blocks for each block ( (hereinafter referred to as input audio data).

On the other hand, during playback, the digital signal output circuit 55 sequentially loads the playback audio data stored in the memory circuit 47, and at this time, by loading the playback audio data based on the count value of the counter circuit. , the reproduced audio data is deinterleaved and converted into a digital audio signal D0, and then output to the input/output circuit 54 and the digital signal conversion circuit 30. At this time, in the double speed mode, the digital signal input/output circuit 55 outputs the digital audio signal at half the period of the normal mode. It is designed to output an audio signal.

? The error detection and correction circuit (ECC) 56, like the digital signal input/output circuit 55, switches its operation according to the data of the mode byte.

At this time, the error detection and correction circuit 56 sequentially loads the input audio data stored in the memory circuit 47 during recording, and blocks by block the inner code and outer code (Cl) for error correction.
After generating the inner code and C2 code, the inner code and outer code are stored in the memory circuit 47.

At the same time, the error detection and correction circuit 56 sequentially loads subcode data to be recorded in the subdata area from the memory circuit 47 (i.e., consisting of recording information of control data D, .1), and generates an error detection and correction code (Cl code). and stored in the memory circuit 47.

On the other hand, during playback, the error detection and correction circuit 56 sequentially loads the playback data DPI stored in the memory circuit 47, performs error detection and error correction on the playback data D and stores it in the memory circuit 47. .

Furthermore, the error detection and correction circuit 56 is generated by the data input/output circuit 40 of the digital signal processing circuit 4. It operates in synchronization with the system clock signal, thereby switching the error detection and correction code generation processing speed and error detection and correction processing speed in normal mode and double speed mode, respectively. Like the digital signal input/output circuit 55, the recording signal generation circuit 60 operates in synchronization with the system clock signal and switches its operation according to the data of the mode byte. That is, during recording, the recording signal generation circuit 60 is connected to the memory circuit 4.
The input audio data, inner code, outer code, etc. stored in .tau.7 are loaded one by one to generate a recording signal S.sub.2, while the operation is stopped during playback.

At this time, the recording signal generation circuit 60 generates a recording signal S■ based on a predetermined clock signal generated by the data input/output circuit 40 of the digital signal processing circuit 4. By generating the recording signal S■ at a predetermined transmission speed in the normal mode, the standard mode, and the long-time mode. In contrast, in the double speed mode, the transmission speed of the recording signal S■0 is changed to no? Switch to twice the normal mode. As a result, in the digital signal processing circuit 4, after converting the input digital audio signal into audio data, the recording signal S■,
The digital audio signal is converted into a digital audio signal and outputted to the magnetic heads 16A and 16B, and the digital audio signal is sequentially recorded according to a format standardized for the digital audio table recorder. At this time, when selecting and copying contacts A of the selection circuits 24, 28 and 32, by switching the frequency of the system clock signal in double speed mode,
Processes the input digital audio signal at twice the processing speed of the normal mode, generates a recording signal S0 with twice the transmission speed, and operates the rotating drum 12 and magnetic tape 20 at twice the processing speed of the normal mode. By operating the recording signal s■e to the magnetic heads 16A and 16B, the digital audio signal can be recorded at twice the speed of the normal mode. can.

On the other hand, in the reproduction mode, the clock signal extraction circuit 62 controls the magnetic heads 14A, 14B (16A, 16B).
), and outputs the reproduced clock signal to the reproduced signal processing circuit 58 together with the reproduced signal S0.

The reproduced signal processing circuit 58 is a digital signal input/output circuit 5
5, it operates in synchronization with the system clock signal,
While the operation is stopped during recording based on the control data [)coHt, during playback, the playback signal S■ is demodulated by 10-8 based on the playback clock signal, and the resulting playback data DPI is output to the memory circuit 47.

The reproduced data D■ demodulated in this way is once stored in the memory circuit 47, then error-corrected in the error detection and correction circuit 56, and sequentially outputted via the digital signal input/output circuit 55. It is possible to play back digital audio signals recorded on 20. ? When the contacts A of the selection circuits 24, 28, and 32 are selected for copying, in the double speed mode, the rotating drum 10 and the magnetic tape 18 are operated at twice the speed of the normal mode. A reproduced signal SIIF maintained at twice the transmission speed can be obtained.

Therefore, by switching the frequency of the system clock signal, the reproduced signal S is maintained at twice the transmission speed.
By processing the IF, it is possible to reproduce digital audio signals at twice the transmission speed of normal mode.

Therefore, the digital audio signal is converted into a recording signal Sll! by the digital signal processing circuit 4. By converting the signal into C and recording it, the digital audio signal recorded on the magnetic tape 18 can be copied to the magnetic tape 20 at twice the speed of the normal mode.

On the other hand, among the demodulated reproduced data D■, the subcode data recorded in the subdata area is once stored in the memory circuit 47, and then is there an error? The error is corrected by the output correction circuit 56 and outputted via the data input/output circuit 40, so that the recorded information SDSO can be transferred and copied in its entirety. That is, as shown in FIG. 7, the clock signal E generated by the data input/output circuit 40 of the digital signal processing circuit 4
Based on XSY (FIG. 7(A)), the digital signal input/output circuit 55 of the digital signal processing circuit 6 generates the rotating drum reference signal DREF1 (FIG. 7(B)),
The rotating drum 10 is driven in synchronization with the rotating drum reference signal DREFI. As a result, in the digital signal processing circuit 6, the reproduction signal S■(
7(C)) can be obtained, and the reproduced signal S is sequentially processed and delayed by two interleaves to generate the digital audio signal DADT (FIG. 7(D)) and the recorded information SDSO (FIG. 7(D)). E)) can be reproduced.

Note that the numbers 1, 2, . . . are appended here to represent the frame numbers of the digital audio signal DADT and the recorded information.

As a result, the digital signal processing circuit 4 generates the recording signal S*tc (FIG. 7(H)) based on the digital audio signal ADDT (FIG. 7(F)) and the recording information SDSI (FIG. 7(G)). The magnetic tape 20
can copy digital audio signals exactly.

Thus, in this embodiment, the digital signal processing circuit 6 generates a digital audio signal DA consisting of recording data based on the clock signals CK, EXCK, and EXSY.
In contrast to configuring the reproduction signal processing circuit that reproduces DT,
The digital signal processing circuit 4 receives clock signals CK and EX.
An error detection and correction code for recording data DADT is generated based on CKXEXSY, and the recording data DADT and error detection and correction code are used as a recording signal S. A digital signal processing circuit is configured to convert the signal into C and output it to the magnetic heads 16A and 16B.

Furthermore, the digital signal processing circuit 4 supplies clock signals CK and E to the reproduced signal processing circuit and the digital signal processing circuit.
A clock signal generation circuit that outputs XCK and EXSY is configured.

In the above configuration, the digital signal processing circuit 4 switches its operation according to the master mode byte of the control data Dcos, whereas the digital signal processing circuit 6
The operation is switched according to the slave mode byte, and each input control data D. Transfer 0.41.

Correspondingly, if the digital signal processing circuit 4 or 6 is not set to the playback mode after the mask mode byte and slave mode byte are consecutive, the system control circuit 2 outputs the continuous control data Dcon of the recording information SDS I.
A is output to digital signal processing circuits 4 and 6 connected in cascade.

As a result, the control data I) cost is sequentially transferred to the digital signal processing circuits 6 and 4, and the operation modes of the digital signal processing circuits 6 and 4 are set to slave mode and master mode height.

That is, in the first operation mode of the digital audio tape recorder l, when the system control circuit 2 sets the master mode byte to playback mode or dubbing mode and the slave mode byte to recording standby, the digital signal processing circuit 4 starts playback. mode or post-recording mode, and the digital signal processing circuit 4 switches to the A
A digital audio signal TX and a digital audio signal DADT in the ES/EBU format are output, and in the post-recording mode, subcode data can be post-recorded.

On the other hand, in the second operation mode of the digital audio tape recorder 1, when the system control circuit 2 sets the master mode byte and slave mode byte to the recording mode and recording standby state, respectively, the AE
Digital audio signal R in S/EBU format
X or the digital audio signal ADDT are sequentially input to the digital signal processing circuit 4 and recorded on the magnetic tape 20.

On the other hand, in the third e operation mode of the digital audio tape recorder l, when the system control circuit 2 sets the master mode byte and slave mode byte to the recording standby and playback modes, respectively, the digital signal processing circuit 6 starts the playback mode. mode, AES/E
A digital audio signal RX and a digital audio signal DADT in BU format are output from the digital signal processing circuit 6.

On the other hand, in the fourth operation mode of the digital audio tape recorder 1, when the system control circuit 2 sets the master mode byte and slave mode height to the recording mode and the playback mode, respectively, the digital signal processing circuits 4 and 6 Switches to recording mode and playback mode, respectively.

Therefore, in the digital audio table recorder 1, the digital audio signal DADT recorded on the magnetic tape 18 via the digital signal processing circuit 6 is
can be obtained, and the digital audio signal DA
DT is connected to the magnetic tape 2 via the digital signal processing circuit 4.
Recorded as 0.

At this time, the digital signal processing circuit 6 uses the clock signals CK and E generated by the digital signal processing circuit 4.
By operating on the basis of Outputs signal DADT.

On the other hand, the digital signal processing circuit 4 converts the digital audio signal DADT outputted from the digital signal processing circuit 4 into a recording signal SIIIC together with the recording information SDSO, and outputs it to the magnetic heads 16A and 16B. At this time, the digital signal processing circuit 4 outputs the clock signal CK to the digital signal processing circuit 6 for synchronization, thereby easily processing the digital audio signal DADT output from the digital signal processing circuit 6 and converting it to the magnetic tape. 20 can be copied exactly.

According to the above configuration, by synchronizing the digital signal processing circuits 4 and 6 of the recording system and the reproduction system by sharing the clock signal, it is possible to record the reproduced digital audio signal with a simple configuration. Digital audio signals can be easily recopied.

(G2) Other Embodiments Although the above-mentioned embodiment describes the case where control data is transmitted in the form of serial data, the present invention is not limited to this, and the control data is transmitted in parallel data in units of 8 bits, for example. Even in this case, by cascading, the overall configuration can be simplified compared to the conventional one.

Furthermore, in the above-mentioned embodiment, a case was described in which two systems of recording and reproducing systems were controlled by one system control circuit, but the present invention is not limited to this, and in short, the present invention can be applied to the case where a plurality of recording and reproducing systems are controlled. Can be widely applied.

In this case, second and third master mode bytes may be provided.Furthermore, in the above embodiment, by sharing the clock signal, the clock signal generation circuit is omitted in the digital signal processing circuit 6 on the reproduction side. Although the case has been described, the present invention is not limited to this, and the clock signal generation circuit may be provided on the reproduction side and the clock signal generation circuit on the recording side may be omitted.

Furthermore, in the above-described embodiment, the case where the present invention is applied to a digital audio tape recorder equipped with two recording/playback systems is described, but the present invention is not limited to this, and the present invention is not limited to this. It can be widely applied when controlling two recording/reproducing systems. Further, in the above-described embodiment, a case was described in which two magnetic tapes were used for recording and reproducing, but the present invention is not limited to this, but can be widely applied, such as when copying digital signals from a compact disc player. ．． Effects of the Invention As described above, according to the present invention, by sharing the clock signal between the recording system and the reproducing system, data reproduced by the reproducing system can be recorded in the recording system with a simple configuration. It is possible to obtain a magnetic recording device that can make exact copies with a similar configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a digital audio table recorder according to an embodiment of the present invention, FIG. 2 is a schematic diagram for explaining its control data, FIG. 3 is a schematic diagram for explaining mode bytes, and FIG. Fig. 4 is a schematic diagram explaining the overall operation of the digital audio table recorder, Fig. 5 is a block diagram showing the digital signal processing circuit, Fig. 6 is a block diagram showing the data input/output circuit, and Fig. 7 is a copying operation. FIG. 2 is a signal waveform diagram for explaining.

Claims (1)

[Claims] A reproduction signal processing circuit that reproduces recorded data based on a predetermined clock signal; and a reproduction signal processing circuit that reproduces recorded data based on a predetermined clock signal; a digital signal processing circuit that converts the data and the error detection and correction code into a recording signal and outputs it to the magnetic head; and a rotating drum equipped with the magnetic head that rotates at a predetermined speed, and a magnetic tape that is wound around the rotating drum. What is claimed is: 1. A magnetic recording device comprising: a drive circuit that causes a drive circuit to run at a predetermined speed; and a clock signal generation circuit that outputs the clock signal to the reproduction signal processing circuit and the digital signal processing circuit.