JPH03217046A - Automatic wiring method - Google Patents

Abstract

PURPOSE:To reduce the area of a chip and to contribute to performance of 100% of wiring rate by including data of equivalent terminal to be inserted and replaced to cells in terminal data, replacing the terminal if wirings temporarily connected to the terminals of the same cell are crossed to each other, and performing wiring between the cells. CONSTITUTION:In an automatic wiring method for wiring between cells by a computer based on cell disposition data, terminal data of the cells and connection data between the cells on a semiconductor substrate, the data of equivalent terminal to be replaced in the cells are included in the terminal data, the terminals are temporarily connected 1 based on the cell disposition data, the terminal data and the connection data, and if the wirings temporarily connected to the terminal of the same cell are crossed to each other, the terminals are replaced 3, and wirings 4 are made between the cells. Thus, the crossing of the wirings is avoided to narrow a necessary wiring region. Accordingly, in the case of full-custom LSI, the area of the chip can be reduced, while in the semi-custom LSI, it contributes to the performance of 100% of wiring rate.

Description

[Detailed description of the invention] 【overview】

Regarding automatic wiring methods using computers in the chip design of semiconductor integrated circuits, the purpose of this document is to reduce the chip area or contribute to the achievement of 100% wiring efficiency, and to provide information on cell placement data on semiconductor substrates, In an automatic wiring method for wiring between cells by a computer based on terminal data of and connection data between the cells, the terminal data includes data of equivalent terminals that can be exchanged with each other for each cell, and the terminal data includes data of equivalent terminals that can be exchanged with each other for each cell, , temporarily connect the equivalent terminals based on the terminal data of the cell and the connection data between the cells, and when the wirings temporarily connected to the equivalent terminals of the same cell cross each other,
The equivalent terminals are exchanged with each other to wire between the cells.

[Industrial Application Field 1] The present invention relates to an automatic wiring method using a computer in chip design of a semiconductor integrated circuit. 2. Description of the Related Art In chip design, in order to shorten the development period, a library of cells that can be used as a standard is used, and a computer automatically arranges the cells and automatically wires between the cells. This automatic wiring is performed to satisfy design rules and given electrical characteristics, and is performed with the goal of optimizing the chip size or achieving a wiring rate of 100%.

[Problem to be solved by the invention]

Hereinafter, problems with conventional automatic wiring will be explained using a logic circuit as shown in FIG. 6 as an example. This logic circuit connects the terminal S1 of the inverter 10 to the wiring N1.
is connected, wiring N2 is connected to terminal S1 of inverter 12, and terminal S2 of inverter 10 and NAND gate 14 are connected.
The terminal S1 of the inverter 12 and the terminal S2 of the NAND gate 14 are connected by a wiring N4, and the terminal S3 of the NAND gate 14 is connected to the wiring N4. Assume that as a result of automatically arranging this logic circuit, inverters 10 and 12 are arranged side by side on both sides of NAND gate 14, as shown in FIG. In this case, when automatic wiring is performed based on the logic circuit shown in FIG. 6, as a result of automatic placement, wirings N3 and N4 intersect. Although wires N3 and N4 are equivalent terminals that can be interchanged, the reason why such wires cross is that it is unclear how the cells will be arranged at the logic circuit design stage. Ru. FIG. 8 shows the wiring pattern of this circuit. This wiring intersection increases the wiring area, causing an increase in the chip area in the case of a full custom LSI, and causing a decrease in the wiring ratio in the case of a semi-custom LSI. In view of these problems, an object of the present invention is to provide an automatic wiring method that can reduce the chip area or contribute to achieving a wiring rate of 100%.

[Means to solve the problem]

FIG. 1 shows the basic configuration of the automatic wiring method according to the present invention. The present invention has the following steps 1-4. (1) Equivalent terminals are determined by a computer based on cell arrangement data on the semiconductor substrate, terminal data of the cells (including data on equivalent terminals that can be replaced with each other for each cell), and connection data between the cells. Make a temporary connection. (2) Determine whether the wires temporarily connected to equivalent terminals of the same cell intersect with each other; (3) If they intersect, the equivalent terminals are interchanged. (4) Next, the computer wires the cells based on the cell placement data, cell terminal data, and connection data between the cells.

[Effect]

According to the method of the present invention, for example, in the case of the logic circuit shown in FIG. 6, the wiring is done as shown in FIGS. Because it is narrower, the chip area can be reduced in the case of a full custom LSI, and the chip area can be reduced in the case of a semi-custom LSI.
In this case, it contributes to achieving a wiring rate of 100%.

[Embodiment 1] An embodiment of the present invention will be described below based on the drawings. FIG. 2 shows the hardware configuration of automatic wiring. This automatic wiring is performed by the computer 20. The computer 20 reads out a netlist (or logic circuit diagram data) indicating connections between cells from the external storage device 21, and reads out the cell data in the cell library and the cells obtained as a result of automatic placement from the external storage device 22. The layout data is read and automatic wiring is performed so as to satisfy the design rules and given electrical characteristics, and with the goal of optimizing the chip size or achieving a wiring rate of 100%. Then, =6 layout data, which is the result of automatic placement and wiring, is written to the external storage device 23. This cell data includes cell shape data, cell terminal data, and equivalent terminal data. Here, equivalent terminal data refers to interchangeable terminals for each cell. for example,
In the case of a logic circuit as shown in FIG. 6, the circuit configuration remains the same even if the terminals S1 and S2 of the NAND gate 14 are interchanged, and the terminals S1 and 82 of the NAND gate 14 are equivalent terminals. Next, the automatic wiring procedure will be explained based on FIG. (30) Read each of the above items from the external storage devices 21 and 22. (32) For each cell, check whether there is an equivalent terminal, and if an equivalent terminal exists, (34) roughly wire between the equivalent terminal and other terminals connected to it. This general wiring is a temporary wiring. (36) Determine whether the schematic wirings connected to equivalent terminals of the same cell intersect with each other. (38) If they intersect, both equivalent terminals are exchanged. For example, as shown in FIG. 7, if the wires N3 and N4 connected to the terminals S1 and S2 of the NAND gate 14 intersect, the terminals in the netlist corresponding to the terminals S1 and S2 of the NAND gate 14 in FIG. replace each other. (40) Next, wires are connected between cells in the same manner as in the conventional method, and layout data is created. (42) Next, save this layout data to the external storage device 2.
Write in 3. In this way, for example, in the case of the logic circuit shown in FIG. 6, the wiring is done as shown in FIGS. 4 and 5, and the wiring N3
Since the intersection of N4 and N4 is avoided and the required wiring area becomes narrower, the chip size can be reduced or contribute to achieving a wiring ratio of 100%. In the above process, even if step 40 is performed after steps 32 to 38 are performed for all automatically placed cells, or steps 32 to 38 are performed before each wiring in the middle of wiring between cells. You may also perform the following processing. If the wiring of the equivalent terminals is corrected so that they do not intersect after all the wiring between the cells is completed, the effects of the present invention cannot be obtained because the wiring in the vicinity thereof is not corrected. Effects of the Invention As explained above, according to the automatic wiring method according to the present invention, the wiring area connected to interchangeable equivalent terminals can be avoided and the required wiring area can be narrowed, so that full custom-LSI In this case, the chip area can be reduced, and in the case of a semi-custom LSI, this has an excellent effect of contributing to achieving a wiring rate of 100%.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the principle structure of the automatic wiring method according to the present invention. 9. FIGS. 2 to 5 relate to one embodiment of the present invention, FIG. 2 is a block diagram showing the hardware configuration of automatic wiring, FIG. 3 is a flow chart showing the automatic wiring procedure, and FIG. 4 is a flow chart showing the automatic wiring procedure. FIG. 5 is an inter-cell connection diagram of the circuit shown in the figure, and FIG. 5 is a wiring pattern diagram of the circuit shown in FIG. FIG. 6 is a block diagram showing an example of a logic circuit using cells having equivalent terminals. 7 and 8 relate to a conventional example. FIG. 7 is an inter-cell connection diagram of the circuit shown in FIG. 6, and FIG. 8 is a wiring pattern diagram of the circuit shown in FIG. In the figure, 10 and 12 are the inverter 14, the NAND gates N1 to N5 are the wirings 81 to S3, the terminals 20 are the computers 21, 22, and 23 are the external storage devices 10, 10, 12: inverter 14: the NAND gates 1 and 81 to S3: Terminals N1 to N5: Wiring Figure 4 Connection between cells of the circuit shown in Figure 6

Claims (1)

[Claims] In an automatic wiring method for wiring between cells by a computer based on cell placement data on a semiconductor substrate, terminal data of the cells, and connection data between the cells, the terminal data is set for each cell. Temporarily connect the equivalent terminals based on the above cell placement data, the terminal data of the cell, and the connection data between the cells (1), including the data of the equivalent terminals that can be exchanged with each other, and temporarily connect the equivalent terminals of the same cell. If the wires cross each other (2), replace the equivalent terminals with each other (3)
, an automatic wiring method characterized by (4) wiring between cells.