JPH03217058A - Negative resistance type semiconductor element - Google Patents

Negative resistance type semiconductor element

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Publication number
JPH03217058A
JPH03217058A JP1289690A JP1289690A JPH03217058A JP H03217058 A JPH03217058 A JP H03217058A JP 1289690 A JP1289690 A JP 1289690A JP 1289690 A JP1289690 A JP 1289690A JP H03217058 A JPH03217058 A JP H03217058A
Authority
JP
Japan
Prior art keywords
semiconductor region
region
semiconductor
junction
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1289690A
Other languages
Japanese (ja)
Other versions
JP3007647B2 (en
Inventor
Yasuo Hasegawa
長谷川 泰男
Mikio Kawarasaki
河原崎 幹男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP2012896A priority Critical patent/JP3007647B2/en
Publication of JPH03217058A publication Critical patent/JPH03217058A/en
Application granted granted Critical
Publication of JP3007647B2 publication Critical patent/JP3007647B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To obtain a low avalanche breakdown voltage with substantially no influence on the characteristics of such as holding current or trigger current by forming a PN junction for starting the breakdown at a voltage lower than the breakdown voltage of a main PN junction in parallel with the main junction. CONSTITUTION:In a semiconductor device in which a second conductivity type second semiconductor region 2 formed on one main surface of a first conductivity type semiconductor substrate 1 for forming a first semiconductor region 1', a first conductivity type third semiconductor region 4 surrounded by the region 2, and a second conductivity type fourth semiconductor region 3 formed on the other main surface of the substrate 1 are provided, and carriers are injected to the regions 2, 4 by an avalanche current after an avalanche breakdown of a main PN junction J1 formed of the regions 1', 2, a breakdown starting region 10 for forming a PN junction J4 determining the starting voltage of avalanche breakdown between the first region is formed across the region 2, and the junction J4 is disposed at a shallower position than the junction J1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、PNPN構造、又はNPNPN構造の負性抵
抗形半導体素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a negative resistance type semiconductor element having a PNPN structure or an NPNPN structure.

〔従来の技術〕[Conventional technology]

一般に通信線及び各種電気機器の制御ラインなどにおい
ては、自然雷の直撃や誘導、或いは負荷の開閉などによ
ってサージ電圧が生じ、特に通信装置、他の電子機器な
どの高密度モジュール化の進展に伴い、サージ電圧や過
電圧に極めて弱いIC.LSIffi子などが多用され
ているため、電子機器にサージが侵入する前にサージア
プソーバでもってサージを吸収する必要が多くなってい
る。
In general, surge voltages occur in communication lines and control lines for various electrical devices due to direct strikes or induction of natural lightning, or the switching of loads.In particular, surge voltages occur as a result of high-density modularization of communication devices and other electronic devices. , ICs that are extremely susceptible to surge voltages and overvoltages. Since LSIffi devices and the like are frequently used, it is increasingly necessary to absorb surges with surge absorbers before the surges enter electronic equipment.

この様なサージアブソーバとしては種々な種類があるが
、低損失なものとしてPNPN構造、又はNPNPN構
造の素子が知られている。これは基本的には4層ダイオ
ードとして以前から広く知られており、設定電圧以上の
電圧が両端に印加されるとアパランシェブレークダウン
を起こし、その両端の電圧が急減ずるところに特徴があ
る。
There are various types of such surge absorbers, but elements with a PNPN structure or an NPNPN structure are known as low-loss ones. This has basically been widely known as a four-layer diode, and is characterized in that when a voltage higher than the set voltage is applied to both ends, apalanche breakdown occurs, and the voltage at both ends rapidly decreases.

このような構造をもった従来のサージ電圧吸収用半導体
素子を第7図により説明すると、N導電型シリコン半導
体基板1の両主面からP導電型の不純物をドープするこ
とによりP導電型の半導体領域2、3がそれぞれ形成さ
れ,半導体領域2には環状のN導電型の半導体領域4が
形成されている。半導体基板lにより形成されるN導電
型の半導体領域1′とP導電型の半導体領域2は主PN
接合J1を形成し、P導電型の半導体領域2とN導電型
の半導体領域4とは別のPN接合J2を形成する。P導
電型の半導体領域2はN導電型の半導体領域4に四囲を
囲まれ、電極5とオーミソクコンタクトを形成する短絡
部2aを備えている。
A conventional surge voltage absorbing semiconductor element having such a structure will be explained with reference to FIG. Regions 2 and 3 are formed, respectively, and an annular N-conductivity type semiconductor region 4 is formed in the semiconductor region 2. The N conductivity type semiconductor region 1' and the P conductivity type semiconductor region 2 formed by the semiconductor substrate l are mainly PN.
A junction J1 is formed, and a PN junction J2 separate from the P conductivity type semiconductor region 2 and the N conductivity type semiconductor region 4 is formed. The P-conductivity type semiconductor region 2 is surrounded by the N-conductivity type semiconductor region 4, and includes a short circuit portion 2a forming an ohmic contact with the electrode 5.

また、N導電型の半導体領域1′はP導電型の半導体領
域3と第2の主PN接合J,を形成している。
Further, the N conductivity type semiconductor region 1' forms a second main PN junction J with the P conductivity type semiconductor region 3.

この構造のサージ電圧吸収用半導体素子では、?極5と
6間にアバランシェブレークダウン電圧v8■以上の電
圧が印加されると、第1の主PN接合J,がアバランシ
ェプレークダウンを起こし、アバランシェブレークダウ
ン後の電流は第1の主PN接合J1側から半導体領域2
の短絡部2aを通して電極5へ流れる。このときP導電
型の半導体領域2における横方向抵抗などによる電圧降
下が第1の主PN接合J.の閾値を超えると、この素子
はターンオンし、低抵抗状態に移行する。この素子の電
圧一電流特性は第6図に示すようになる。
What about the surge voltage absorbing semiconductor element with this structure? When a voltage equal to or higher than the avalanche breakdown voltage v8 is applied between poles 5 and 6, the first main PN junction J causes avalanche breakdown, and the current after the avalanche breakdown flows to the first main PN junction J1. Semiconductor area 2 from the side
flows to the electrode 5 through the short-circuit portion 2a. At this time, a voltage drop due to lateral resistance in the P conductivity type semiconductor region 2 occurs at the first main PN junction J. When a threshold of 2 is exceeded, the device turns on and enters a low resistance state. The voltage-current characteristics of this element are shown in FIG.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、このような従来の負性抵抗形のサージ電
圧吸収用半導体素子にあっては、P導電型の半導体領域
2の不純物拡散プロフィールでアバランシェブレークダ
ウン電圧V+++、}リガ電流、保持電流などの大きさ
が決まってしまうような構造であったので、低いアバラ
ンシェブレークダウン電圧vIl1を有すると同時に、
大きなトリガ電流値と保持電流値をもつサージ電圧吸収
用半導体素子を製作するのは難しかった。
However, in such a conventional negative resistance type semiconductor device for absorbing surge voltage, the impurity diffusion profile of the P-conductivity type semiconductor region 2 causes large avalanche breakdown voltage V+++, trigger current, holding current, etc. Since the structure was such that the voltage was determined, it had a low avalanche breakdown voltage vIl1, and at the same time
It has been difficult to fabricate semiconductor devices for absorbing surge voltages that have large trigger current values and holding current values.

本発明は、保持電流およびトリガ電流などの特性にほと
んど影響を与えることなく、従来のものに比べて低いア
バランシェブレークダウン電圧をもつ負性抵抗形の半導
体素子を製作し易い半導体構造を提供することを目的と
している。
The present invention provides a semiconductor structure that makes it easy to manufacture a negative resistance type semiconductor element that has a lower avalanche breakdown voltage than conventional ones without having almost any effect on characteristics such as holding current and trigger current. It is an object.

〔問題を解決するための手段〕[Means to solve the problem]

前述のような従来の半導体デバイスの欠点を除去し、こ
の目的を達成するために本発明では、主PN接合のアバ
ランシェプレークダウン電圧よりも低い電圧でアパラン
シェブレークダウンを開始するPN接合を前記主PN接
合と等価回路的に並列に形成したことを特徴としている
In order to eliminate the disadvantages of conventional semiconductor devices as mentioned above and to achieve this objective, the present invention provides a PN junction that initiates avalanche breakdown at a voltage lower than the avalanche breakdown voltage of the main PN junction. It is characterized by being formed in parallel with the PN junction in terms of an equivalent circuit.

〔作用〕[Effect]

この発明による負性抵抗形半導体素子では、主PN接合
と直列に形成されたPN接合が、主PN接合のアパラン
シスブレークダウン電圧より低い設定電圧でアバランシ
ェブレークダウンを開始することにより、主PN接合も
アバランシェブレークダウンを起こすので、従来よりも
負性抵抗形半導体素子のアバランシェブレークダウン電
圧を低くできる。
In the negative resistance type semiconductor device according to the present invention, the PN junction formed in series with the main PN junction starts avalanche breakdown at a set voltage lower than the aparansis breakdown voltage of the main PN junction. Since the junction also causes avalanche breakdown, the avalanche breakdown voltage of the negative resistance type semiconductor element can be lowered than in the past.

(実施例〕 以下第1図乃至第4図に従って本発明の各実施例につい
て説明するが、これら図において第7図に示した記号と
同一の記号は相当する半導体領域又は部材を示すものと
する。
(Embodiments) Each embodiment of the present invention will be described below according to FIGS. 1 to 4. In these figures, the same symbols as those shown in FIG. 7 indicate corresponding semiconductor regions or members. .

先ず第1図において、P導電型の半導体領域2はN導電
型の半導体領域4に四囲を囲まれた複数の細孔よりなる
短絡部2aを備えており、半導体領域2は短絡部2aに
より直接電極5に電気的に結合されている。
First, in FIG. 1, a P-conductivity type semiconductor region 2 is provided with a short-circuit portion 2a consisting of a plurality of pores surrounded by an N-conductivity type semiconductor region 4, and the semiconductor region 2 is directly connected to the short-circuit portion 2a. It is electrically coupled to electrode 5.

半導体領域2の四囲にはこれと同一の導電型で不純物濃
度の高いP゛型半導体領域lOが形成される。このP′
型半導体領域10は半導体領域2よりも浅く形成され、
したがって主PN接合Jとは等価回路的に並列配置では
あるが、主PN接合よりも浅い位置にPN接合J4を形
成ずる。
A P' type semiconductor region IO having the same conductivity type and high impurity concentration is formed around the semiconductor region 2. This P'
The type semiconductor region 10 is formed shallower than the semiconductor region 2,
Therefore, although it is arranged in parallel with the main PN junction J in terms of an equivalent circuit, the PN junction J4 is formed at a shallower position than the main PN junction.

このような構造の負性抵抗形サージ電圧吸収用半導体素
子にあっては、電極6と5間の電圧が上昇する過程で、
第5図と第6図に示すように従来のブレークダウン電圧
VBIより低いブレークダウン電圧VB2で半導体領域
lOと半導体領域1′との間に形成されたPN接合J4
がアバランシェブレークダウンを起こし、このとき流れ
るアパランシェ開始電流I.はP導電型の半導体領域2
を横方向に流れ、更にその短絡部2aを通って電極5へ
流れる。このとき、半導体領域2とその短絡部2′に生
じる電圧降下が半導体領域2と半導体領域4により形成
されるPN接合J2で決まるスレソシュホールドを超え
ると、PN接合J2は順バイアスされて導通し、主PN
接合J1のアバランシェブレークダウンによるアバラン
シェ電流の多くはPN接合J2を通って流れ、このデバ
イスの電圧降下は急激に小さくなる。このときの電流値
がトリガ電流である。
In the negative resistance surge voltage absorbing semiconductor device having such a structure, in the process of increasing the voltage between the electrodes 6 and 5,
As shown in FIGS. 5 and 6, a PN junction J4 is formed between the semiconductor region IO and the semiconductor region 1' at a breakdown voltage VB2 lower than the conventional breakdown voltage VBI.
causes avalanche breakdown, and the avalanche starting current I. is a P conductivity type semiconductor region 2
flows laterally, and further flows to the electrode 5 through the short-circuit portion 2a. At this time, when the voltage drop occurring in the semiconductor region 2 and its short circuit 2' exceeds the threshold determined by the PN junction J2 formed by the semiconductor region 2 and the semiconductor region 4, the PN junction J2 is forward biased and becomes conductive. The main PN
Most of the avalanche current due to avalanche breakdown of junction J1 flows through PN junction J2, and the voltage drop across this device decreases rapidly. The current value at this time is the trigger current.

したがって、このサージ電圧吸収用半導体デバイスの構
造によれば、他の特性に影響を与えることなく、従来の
同様なデバイスに比べて低い電圧でサージ吸収動作を行
うので、広@囲のサージ電圧の吸収が可能である。また
、保持電流1k.}リガ電流の大きさなど諸特性に大き
な影響を与える半導体領域2とは別にアパランシェブレ
ークダウン電圧の大きさを決定する半導体領域10を備
えているので、従来の斯かる半導体デバイスの構造では
相反するアバランシェブレークダウン電圧の低減と保持
電流の増大化を同時に行える。このデバイスが電子回路
におけるサージ吸収に用いられるとき、保持電流の大き
い方がサージ吸収した後に自己消弧し易いので,このサ
ージ電圧吸収用半導体デバイスを回路に挿入したことに
よるその回路の信号電圧に対する影響を小さくできる。
Therefore, according to the structure of this semiconductor device for surge voltage absorption, the surge absorption operation is performed at a lower voltage than conventional similar devices without affecting other characteristics, so it can be used for surge voltage absorption over a wide range. Absorption is possible. In addition, the holding current is 1k. }In addition to the semiconductor region 2, which has a large effect on various characteristics such as the magnitude of the trigger current, the semiconductor region 10 that determines the magnitude of the aparanche breakdown voltage is provided, so that the structure of such a conventional semiconductor device would be contradictory. It is possible to reduce the avalanche breakdown voltage and increase the holding current at the same time. When this device is used to absorb surges in electronic circuits, the one with a larger holding current is more likely to self-extinguish after absorbing the surge. The impact can be reduced.

なお、7、8は絶縁膜である。Note that 7 and 8 are insulating films.

次に第2図に本発明に係る負性抵抗形サージ電圧吸収川
半導体素子の第2の実施例を示す。
Next, FIG. 2 shows a second embodiment of a negative resistance type surge voltage absorbing semiconductor device according to the present invention.

同図において第1図に示した記号と同一の記号は相当す
る部材を示すものとする。この実施例は半導体基板lの
双方の主面側から同一構造の半導体領域を形成したもの
であり、半導体基板lの厚さ方向の中央線を中心に対称
的な構造となっている。
In this figure, the same symbols as those shown in FIG. 1 indicate corresponding members. In this embodiment, semiconductor regions having the same structure are formed from both main surfaces of the semiconductor substrate l, and the structure is symmetrical about the center line in the thickness direction of the semiconductor substrate l.

この実施例のデバイスによれば双方向のサージ電圧を吸
収でき、また双方向とも低い電圧でスイソチング動作で
きる。
The device of this embodiment can absorb surge voltages in both directions, and can perform switching operations at low voltages in both directions.

次に第3図により本発明に係る負性抵抗形半導体素子の
第3の実施例を説明すると、これはアバランシヱブレー
クダウン開始用の半導体領域lOの周I&部にガードリ
ング領域11を備えたことを特徴としている。このガー
ドリング領域11は半導体領域lOと同一の導電型であ
り、アバランシエブレークダウン開始電圧の精度を高め
る作用を行う。
Next, a third embodiment of the negative resistance type semiconductor device according to the present invention will be explained with reference to FIG. It is characterized by This guard ring region 11 has the same conductivity type as the semiconductor region IO, and functions to improve the accuracy of the avalanche breakdown start voltage.

次に第4図により本発明の第4の実施例を説明すると、
アバランシェブレークダウン開始用の半導体領域10は
P導電型の半導体領域2においてN導電型の半導体領域
4間に形成される。半導体領域lOにおけるアバランシ
ェブレークダウン開始電流はP導電型の半導体領域2を
図面左右方向に拡がり、その夫々の短絡部2aを通って
電極5へ流れる。この実施例では設計通りのアバランシ
ェブレークダウン開始電圧を比較的得易い。
Next, a fourth embodiment of the present invention will be explained with reference to FIG.
The semiconductor region 10 for starting avalanche breakdown is formed between the N-conductivity type semiconductor regions 4 in the P-conductivity type semiconductor region 2 . The avalanche breakdown starting current in the semiconductor region IO spreads through the P-conductivity type semiconductor region 2 in the left-right direction in the drawing, and flows to the electrode 5 through the respective short-circuit portions 2a. In this embodiment, it is relatively easy to obtain the designed avalanche breakdown start voltage.

なお、以−Lの実施例において保持電流を大きくしたい
場合には半導体領域2の短絡部2′に金又は白金のよう
なライフタイムキーを拡散しても可能である。
In the embodiment described below, if it is desired to increase the holding current, it is also possible to diffuse a lifetime key such as gold or platinum into the short circuit portion 2' of the semiconductor region 2.

[発明の効果〕 以上述べたように本発明によれば、保持電流の大きさな
ど諸特性に大きな影響を与える半導体領域2とは別にア
バランシェブレークダウン電圧の大きさを決める半導体
領域10を備えたので、従来の半導体デバイスの構造で
は相反するアバランシェブレークダウン電圧の低減と保
持電流の増大化を同時に行えるばかりでなく、各半導体
領域の■ l ディメンションの設定が容易になり、歩留が向上する。
[Effects of the Invention] As described above, according to the present invention, the semiconductor region 10 that determines the magnitude of the avalanche breakdown voltage is provided separately from the semiconductor region 2 that has a large influence on various characteristics such as the magnitude of the holding current. Therefore, not only is it possible to reduce the avalanche breakdown voltage and increase the holding current at the same time, which are contradictory in the conventional semiconductor device structure, but also it becomes easy to set the 1 dimension of each semiconductor region, and the yield is improved.

また、アパランシェブレークダウンが浅い半導体領域1
0で生じてこの電流で半導体デバイスがターンオンする
ので、ターンオン時の電流の拡がりが速くなり、di/
dt@#量が大きくなるという効果もある。
In addition, semiconductor region 1 with shallow aparanche breakdown
Since the semiconductor device turns on with this current, the current spreads quickly at turn-on, and di/
This also has the effect of increasing the amount of dt@#.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第4図は本発明に係る負性抵抗形半導体素子
の異なる4つの実施例を示し、第5図は本発明に係る負
性抵抗形半導体素子の特性を示す図、第6図は第7図に
示す従来の負性抵抗形半導体素子の特性を示す図である
。 1・・・N導電型の半導体基板 2,3・・・P導電型の半導体領域 2a・・・半導体領域2の短絡部 4・・・N導電型の半導体領域 5.6・・・電極 7.8・・・絶縁N ■ 2 10・・・アバランシェブレークダウン開始用の半導体
領域
1 to 4 show four different embodiments of the negative resistance type semiconductor device according to the present invention, FIG. 5 is a diagram showing the characteristics of the negative resistance type semiconductor device according to the present invention, and FIG. 6 7 is a diagram showing the characteristics of the conventional negative resistance type semiconductor element shown in FIG. 7. FIG. 1... Semiconductor substrates of N conductivity type 2, 3... Semiconductor region 2a of P conductivity type... Short circuit part of semiconductor region 2... Semiconductor region of N conductivity type 5.6... Electrode 7 .8...Insulation N ■ 2 10...Semiconductor region for starting avalanche breakdown

Claims (6)

【特許請求の範囲】[Claims] (1)第1の半導体領域を形成する第1の導電型の半導
体基板、該半導体基板の一方の主面側に形成された第1
の導電型と反対導電型の第2の導電型の第2の半導体領
域、該第2の半導体領域に囲繞されるよう形成された第
1の導電型の第3の半導体領域、及び前記半導体基板の
他方の主面側に形成された第2の導電型の第4の半導体
領域を少なくとも備え、前記第1の半導体領域と第2の
半導体領域とにより形成れされた主PN接合のアバラン
シエブレークダウン後のアバランシエ電流により、前記
第2の半導体領域と第3の半導体領域へキャリアを注入
させる半導体装置において、アバランシエブレークダウ
ンの開始電圧を決定するPN接合を前記第1の半導体領
域との間に形成するブレークダウン開始領域を前記第2
の半導体領域にかかるよう形成し、前記PN接合が前記
主PN接合より浅い位置にあることを特徴とする負性抵
抗形半導体素子。
(1) A semiconductor substrate of a first conductivity type forming a first semiconductor region, a first semiconductor substrate formed on one main surface side of the semiconductor substrate;
a second semiconductor region of a second conductivity type opposite to that of the conductivity type; a third semiconductor region of the first conductivity type formed to be surrounded by the second semiconductor region; and the semiconductor substrate. an avalanche break of the main PN junction formed by the first semiconductor region and the second semiconductor region, including at least a fourth semiconductor region of the second conductivity type formed on the other main surface side of the In a semiconductor device in which carriers are injected into the second semiconductor region and the third semiconductor region by an avalanche current after down, a PN junction that determines the starting voltage of avalanche breakdown is connected to the first semiconductor region. The breakdown start region formed in the second
1. A negative resistance type semiconductor device, characterized in that the PN junction is formed so as to extend over a semiconductor region, and the PN junction is located at a shallower position than the main PN junction.
(2)前記ブレークダウン開始領域が前記第2の半導体
領域の周囲に形成されることを特徴とする請求項(1)
に記載の負性抵抗形半導体素子。
(2) Claim (1) characterized in that the breakdown start region is formed around the second semiconductor region.
Negative resistance type semiconductor device according to.
(3)前記ブレークダウン開始領域が前記第3の半導体
領域間に存在することを特徴とする請求項(1)に記載
の負性抵抗形半導体素子。
(3) The negative resistance type semiconductor device according to claim (1), wherein the breakdown start region exists between the third semiconductor regions.
(4)前記ブレークダウン開始領域の外周にガードリン
グ半導体領域を備えたことを特徴とする負性抵抗形半導
体素子。
(4) A negative resistance type semiconductor device, characterized in that a guard ring semiconductor region is provided on the outer periphery of the breakdown start region.
(5)前記第1の半導体領域において、前記第2の半導
体領域と前記第3の半導体領域と対称の位置にこれら領
域と同等な第5の半導体領域と第6の半導体領域を備え
たことを特徴とする負性抵抗形半導体素子。
(5) In the first semiconductor region, a fifth semiconductor region and a sixth semiconductor region, which are equivalent to the second semiconductor region and the third semiconductor region, are provided at positions symmetrical to these regions. Negative resistance type semiconductor device with special features.
(6)前記ブレークダウン開始領域に、金又は白金等の
ライフタイムキラーが拡散されていることを特徴とする
請求項(1)に記載の負性抵抗形半導体素子。
(6) The negative resistance type semiconductor device according to claim (1), wherein a lifetime killer such as gold or platinum is diffused in the breakdown initiation region.
JP2012896A 1990-01-23 1990-01-23 Negative resistance semiconductor device Expired - Fee Related JP3007647B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012896A JP3007647B2 (en) 1990-01-23 1990-01-23 Negative resistance semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012896A JP3007647B2 (en) 1990-01-23 1990-01-23 Negative resistance semiconductor device

Publications (2)

Publication Number Publication Date
JPH03217058A true JPH03217058A (en) 1991-09-24
JP3007647B2 JP3007647B2 (en) 2000-02-07

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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