JPH03217114A - Glitch preventing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to digital circuit technology for information logic systems in general.

In particular, in complex and large-scale circuits with control mechanisms, multiphase clocks and multiple timing signals are used, and slight gaps are intentionally created between each clock and timing signal to eliminate overlap. A commonly used method is to leave it as is. However, on the other hand, it is often necessary to combine a plurality of reference clocks or timing signals using an OR circuit or the like to generate a new clock. When generating new clocks as described above, a problem is glitches that occur because the respective reference clocks do not overlap, and the present invention relates to a glitch prevention circuit that efficiently removes the glitches.

2. Prior Art FIG. 5 shows a conventional glitch prevention circuit for two input signals, FIG. 6 is a timing waveform diagram showing its operation, and FIG. 7 shows a conventional glitch prevention circuit for multiple input signals.

In FIG. 5, the glitch prevention circuit is ORed with input signal 1.
A delay circuit 3 such as a multi-stage buffer is provided to the circuit 70 input signal 2.
2 whose input is the output signal 5 and whose output is the output signal 6.
It is constructed by inserting a manual OR circuit 7.

In FIG. 7, this is for a plurality of non-overlapping clocks or timing signals 7, 8, 9, 10, and the same number of delay circuits 11, 12 as the number of input signals are provided in multiple stages, and each input signal is It is constructed by integrating using OR circuits 13, 14, and 15.

Next, the operation of the conventional glitch prevention circuit will be explained.

In order to prevent spike-like glitches that occur frequently at the moment when the "H" and "L" levels of input signal 1.2 switch,
It is necessary to delay input signal 2 with respect to input signal 1.

For this purpose, in the past, as shown in FIG. 5, a delay circuit 3 such as a CR circuit or a multi-stage buffer is provided to
This means that the "H" level of the input signal 2 is overlapped with the "H" level at the time when the "H" level becomes "H" level, thereby preventing the occurrence of glitches.

This is for multiple non-overlapping input signals. First, as in the case of two-person input, a glitch-free OR signal is generated for the first two input signals, and a delay circuit is provided for this generated signal. , and the next input signal to generate a new glitch-free OR signal as before. Similar circuit operation is performed for all input signals. This is a means of obtaining a glitch-free signal by performing a glitch-free signal.

Problems to be Solved by the Invention In recent years, the circuits of electronic devices have become increasingly complex and large-scale, and the control circuits thereof are also becoming increasingly complex and large-scale. In view of the current situation, when using such a glitch prevention circuit according to the prior art, it is necessary to provide a delay circuit using a buffer, CR, etc., which makes the circuit complex and increases its scale, resulting in the following disadvantages: Ta. Furthermore, since a delay circuit is used, the rise time of the desired signal itself is significantly delayed, which causes problems in the entire circuit system.

Means for Solving the Problems The present invention provides two non-overlapping input signals with a slight gap between them, one input signal is input to the source of one transistor of a pair of transistors whose drains are mutually coupled, and the other input signal is input to the source of one transistor of a transistor pair whose drains are mutually coupled. One input signal is input to the gate of each of the transistor pairs, the source of the transistor on the other side of the transistor pair is connected to the ground potential, and the drain output of the transistor pair and the gate of the transistor pair are connected to the source of the transistor on the other side of the transistor pair. This is a glitch prevention circuit constructed by connecting the input waveform to a two-man OR circuit.

Also, for multiple non-overlapping input signals,
This is a glitch prevention circuit constructed by connecting the circuits shown above in multiple stages equal to the number of input signals.

According to the present invention, it is possible to prevent the occurrence of glitches with a simple and small-scale circuit, and especially in a complex circuit where a plurality of input signals are present, it is possible to prevent the occurrence of glitches with a simple configuration. , it is possible to achieve a revolutionary reduction in the size of the circuit compared to the conventional technology. Further, the rise time of the desired signal itself can be minimized, and a glitch prevention circuit is obtained which does not cause problems in terms of circuit operation speed.

EXAMPLE Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a glitch prevention circuit according to a first embodiment of the present invention, which is composed of two transistors 21 and 22 and an OR circuit 23. In FIG.

In two non-overlapping input signals 24.25, the input signal 24 is input to the source of one side of the transistor 21 of the transistor pair 21.22 whose drains are interconnected, and the input signal 25 is input to the gate of each transistor pair 21.22. shall be entered in Also, transistor 2
The source of 2 is connected to ground potential 26. It is constructed by inputting the output signal 27 and input signal 25 of the common drain of the transistor pair 21 and 22 to a two-man OR circuit 23.

6 Next, the operation of this circuit will be explained in detail. FIG. 2 shows a timing waveform diagram representing the operation.

First, the input signal 24 is at "L" level, and the input signal 25 is at "L" level.
In the case of "H" level, the P-channel transistor 21 is turned off and the N-channel transistor 22 is turned on.
The drain output signal 27 becomes "L" level, and the output signal 28 of OR circuit 23 becomes "H" level. Next, input waveform 2
5 changes to the "L" level, the P-channel transistor 21 turns on, the N-channel transistor 22 turns off, and the drain output signal 27 maintains the "L# level. Therefore, the output signal 28 goes to the "L" level. Become.

After a certain period of time has elapsed, when the input signal 24 changes to the "H" level, the drain output signal 27 also immediately changes to the "H" level, and the output signal 28 also changes to the "H" level in accordance with the change. Then, when the input signal 24 changes to the "L" level, the drain output signal 27 also tries to change to the "L" level. However, since the transistor 21 is a P-channel transistor, this change in the drain output signal 27 progresses very slowly due to its characteristics.

If the input signal 25 changes to the "H" level before the drain output signal 27 reaches the "L" level, the output signal 28 can be held at the "H" level.

Two input waveforms 24 with a slight gap in this way.
At step 25, by newly generating a drain output signal 27 using the circuit of the first embodiment, this drain output signal 27 and input signal 25 overlap, and no glitch occurs.

FIG. 3 shows a second embodiment of the present invention for n consecutive non-overlapping input signals 31 to 35, and two consecutive input signals for all input signals 31 to 35. (n-1) circuits 36 to 39 of the first embodiment are used in order to generate (n-1) drain output signals 41, 42, and 43, respectively, and all these drain output signals are 40, 41, 42 and the final input signal 35 in terms of timing, the OR circuit 4
3.

Next, the operation of the circuit of the second embodiment will be explained. FIG. 4 shows a timing waveform diagram representing the operation.

The operation of the second embodiment of the present invention is similar to that shown in the first embodiment, and even for n consecutive input waveforms with no overlap, a desired glitch can be generated. It is possible to obtain a new output waveform without

Effects of the Invention As is clear from the above explanation, the present invention provides an efficient glitch prevention circuit that is simpler and has a much smaller circuit scale than the conventional one, and also has a very small delay time for the desired signal. This makes it possible to simplify and increase the density of electronic equipment systems.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the glitch prevention circuit of the present invention, FIG. 2 is a timing waveform diagram showing its operation, and FIG.
The figure shows a circuit diagram of the second embodiment of the glitch prevention circuit of the present invention, Figure 4 is a timing waveform diagram showing its operation, Figure 5 is a diagram of a glitch prevention circuit according to the prior art, and Figure 6 shows its operation. FIG. 7 is a timing waveform diagram showing a glitch prevention circuit diagram for a plurality of input signals according to the prior art. 1.2, 7, 8, 9, 10, 24, 25, 31.32,
33, 34.35... Input terminal, 5, 16.2
8,24...Output signal, 6,23.43・Old-
OR circuit, 21...P channel type transistor, 22...N channel type transistor, 2
6. Old... Ground terminal, 27, 40, 41. 42...
...Drain output terminal.

Claims (1)

[Claims] A first input signal is input to the source of a first transistor of a pair of transistors whose drains are interconnected, and a second input signal is input to the gate of each of said pair of transistors, and a second input signal is input to the source of a first transistor of a pair of transistors whose drains are interconnected. A glitch prevention circuit comprising: a source of the transistor pair connected to ground potential, and an output signal of a common drain of the transistor pair and the second input signal connected to an OR circuit.