JPH03217125A - oscillation circuit - Google Patents

Abstract

PURPOSE:To miniaturize a device, to reduce the number of parts, and to reduce the cost by providing a frequency dividing circuit in the feedback loop of one reference frequency oscillator circuit, zero or more frequency dividing circuits, and a phase fixing loop circuit. CONSTITUTION:A reference frequency fs is divided to fs/m by a frequency dividing circuit 102. The oscillation output signal obtained by a voltage controlled oscillating circuit 105 has the frequency divided to 1/n by a frequency dividing circuit 107 to have a frequency fo/n. A phase comparing circuit 103 compares phases of two oscillator outputs with each other, and the result is fed back to the voltage controlled oscillator circuit 105 through a low pass filter 104. Thus, the stable oscillator output whose frequency is n/m times as high as the reference frequency is obtained in an oscillator output terminal 106.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an oscillation circuit.

[Summary of the Invention] The present invention provides an oscillation circuit that uses an oscillation output signal generated from a reference frequency oscillation circuit or a frequency-divided output signal thereof, and an output signal that frequency-divides a free-run oscillation output signal of a voltage controlled oscillation circuit. This makes it possible to stabilize the 7-rerun oscillation output signal of the voltage controlled oscillator circuit at a frequency that is a real number multiple of the reference frequency, making it possible to obtain oscillation outputs at multiple different frequencies. be.

[Conventional technology] Traditionally, electronic devices with oscillation circuits use an oscillation circuit that outputs the required frequency itself, or an oscillation circuit that oscillates at an integer multiple of the required frequency, and a frequency dividing circuit. A reference frequency output signal was realized.

FIG. 2 shows an example of a conventional information processing device, in which 201,
210~21! I is an oscillation circuit, 201 is 32MHz,
210 is 24 MHz, 1.8432 MHz, 212 is 25.175 MHz, and 213 is 28.322 MHz. 202 is an MPU, 203 is a part of memory, 204
is a floppy disk drive control section, 205 is a serial communication control section, 206 is a display signal control section, and 208 is a keyboard control section. Since the necessary reference frequency is 8 MHz, the 32 MHz of 201 is set by a 2070 frequency dividing circuit.
8MHz by dividing the oscillation output signal by 1/4
I am getting . The display signal control unit 206 controls two types of CRTs, 640 dots and 720 dots.
We need different reference frequencies. 209 is a system bus.

[Problem to be solved by the invention] Until now, the frequency that can be derived from one oscillation output signal is only an integer fraction of the reference frequency using a frequency divider circuit or an integer multiple of the reference frequency using a phase-locked loop. Met. Therefore, as shown in the example shown in Figure 2, most of the required reference frequencies require their own oscillation circuits, resulting in a large number of components (and the area occupied by the oscillation path on the printed wiring board). [Means for Solving the Problem] Therefore, the oscillation circuit of the present invention has the following features:
It is characterized by having one reference frequency oscillation circuit followed by zero or more frequency dividing circuits, a phase locked loop circuit, and a frequency dividing circuit in its feedback loop.

Further, as claimed in claim 2, the present invention is characterized in that it has one reference frequency oscillation circuit, a plurality of frequency dividing circuits and a phase locking no-hig circuit, and has output terminals for a plurality of different frequencies.

Further, as described in item 6, the frequency dividing ratio of the frequency dividing circuits 102 and 107 in FIG. 1 is made variable.

[Operation] In the oscillation circuit configured as shown in Fig. 1, the frequency division ratio of the 102 frequency division circuit is set to 1/771, the frequency division ratio of the 107 frequency division circuit is set to 1/n, and the reference frequency of 101 is set to 1/771. /s, 106
Letting the output frequency of IO be IO, the output frequency fo is expressed by the following equation.

fo'' f8 m Since 詣 and 夷 are positive integers, the resulting output frequency f is a positive real number multiple of the reference frequency f6.

[Example] FIG. 1 is a conceptual diagram in claim 1 of the present invention. 1
01 is a reference frequency oscillation circuit. The frequency dividing circuit 102 divides the reference frequency f8 into f8/m. The oscillation output signal obtained by the voltage controlled oscillation circuit 105 is frequency-divided by 1/3 by the 1070 frequency divider circuit, so that the frequency is f. /rL. The phase comparison circuit 103 compares the phases of the two oscillation outputs, and the result is fed back to the voltage controlled oscillation circuit 105 through a low pass filter 104. As a result, a stable oscillation output rL/m times the reference frequency is obtained at the 1060 oscillation output terminal.

FIG. 3 shows an embodiment according to claim 1 of the present invention in which the oscillation frequency f8 of the reference frequency oscillation circuit 101 is set to 25.175MH.
z, and the frequency division ratio of the frequency dividing circuit 102 is assumed to be lz/e. Also, the free run oscillation frequency f of the voltage controlled oscillation circuit 105. By setting 28.322MHZ and setting the frequency division ratio of the 107 frequency divider circuit to 1/9, 28.
An oscillation output of 322 MHz is obtained, and by using it together with the reference frequency of 2.5.175 MHz obtained from the output terminal 108, the oscillation frequency necessary for the display signal control circuit in the conventional example shown in Fig. 2 can be obtained at the same time. .

FIG. 4 shows an embodiment related to claim 2K of the present invention in which the oscillation frequency/s of the reference frequency oscillation circuit 101 is set to 51. 4
69 MHz, and the frequency division ratio of the frequency dividing circuit 102 is 1.
/10. Then, the 7-rerun oscillation frequency f of the voltage controlled oscillation circuit 105 in the first phase-locked loop. 2
8.322. MHz, and the frequency division ratio of the frequency dividing circuit 107 is 1/9. Also, the 7-rerun oscillation frequency f of the voltage controlled oscillation circuit 105α in the second phase-locked loop. 25
．． 175MHz, and the frequency division ratio of the frequency divider circuit 107α is 1/
8, the output terminal 106 will have 28. ! 122M
A stable frequency of 25.175 MHz is obtained at Hz, 106α. Further, by providing a frequency dividing circuit 102a with a frequency division ratio of 1/4 at the next stage of the fundamental frequency oscillation circuit 101, an oscillation frequency of 7.9 MHZ can be obtained at the output terminal 109.

FIG. 5 is a block diagram when the embodiment shown in FIG. 4 is applied to the prior art shown in FIG. 2.

Reference numeral 301 denotes an oscillator of the present invention, the contents of which are the same as those shown in FIG. 4 above. 202 is MPU, 20? ) is part of the memory, 20
4 is a floppy disk drive control unit, 210 is 24
MHZ oscillation circuit, 205 is a serial communication control unit, 21
1 is a 1.8432 MHZ oscillation circuit, 206 is a display signal control section, and 208 is a keyboard control section. 209 is
The system path 302 is 7. 9 MH 2 signal, 3
03 is a 51.5MHz signal, 304 is 25.175M
Hz signal, 305 is 2 8. 3 2 2 MH
This is the signal of z. Comparing with the conventional example Fig. 2, 201,
The oscillation circuits 212 and 213 and the frequency dividing circuit 207 are no longer necessary.

FIG. 6 shows an embodiment related to claim 3 of the present invention, in which the oscillation frequency f8 of the reference frequency oscillation circuit 101 is set to 31.469M.
Hz, and the division ratio of the frequency dividing circuit 1020 is 1/10.

Then, the free run oscillation frequency of the voltage controlled oscillation circuit 105 is changed from 25.175 MHz to 28. 322 MH
Z and wide《take. The frequency dividing circuit 110 can select a frequency division ratio of 1/8 or 1/9 using a terminal 111. When the frequency division ratio is 1/8, fθ/8=3 1.4 6 9/1
0, and 25.175 MHZ appears at the output terminal 106. When the division ratio is 1/9, f e /
9 = 5 1. 469/10, and 28.322 MHz appears at the output terminal 106.

[Effects of the Invention] As explained above, the present invention provides a frequency divider circuit in the phase-locked loop, so 1, stable oscillation is possible at a frequency different from that of the reference frequency oscillation circuit, and one reference frequency oscillation circuit is provided. This enables the output of multiple different frequencies, making it possible to miniaturize equipment, reduce the number of parts, and reduce costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram in claim 1 of the present invention. FIG. 2 is a block diagram of a conventional information processing device. FIG. 3 is a diagram of an embodiment according to claim 1 of the present invention. FIG. 4 is a diagram of an embodiment according to claim 2 of the present invention. FIG. 5 is a diagram of an application example according to claim 2 of the present invention. FIG. 6 is a diagram of an embodiment according to claim 3 of the present invention. 1... Reference frequency oscillation circuit 2... Frequency divider circuit 3... Phase comparison circuit 4... Low pass filter 5... Voltage controlled oscillation Circuit 6... Oscillation output terminal 7... Frequency divider circuit 8... Oscillation output terminal 9... Oscillation output' terminal 0... Minute Variable frequency dividing circuit 1...Dividing rate setting terminal 20 20 20 20 20 20 20 20 1...Oscillation circuit 2...MPU 3... Part of memory 4...Floppy disk drive 5...
Serial communication control unit 6... Display signal control unit 7... Frequency division circuit 8... Keyboard control unit B control unit 209... System node 210 ~213...Oscillation circuit 1...Multi-output oscillation circuit 2 of the present invention...
Oscillation signal output 7.9MHz3... Oscillation signal output 31.5MH4... Oscillation signal output 25.175
MHZ5...Oscillation signal output 28.322MHz
Below

Claims (3)

[Claims] (1) An oscillation circuit characterized by having one reference frequency oscillation circuit followed by zero or more frequency dividing circuits, a phase locked loop circuit, and a frequency dividing circuit in its feedback loop. (2) The oscillation circuit according to claim 1, wherein the oscillation circuit has a plurality of oscillation output terminals of different frequencies. (3) The oscillation circuit according to claim 1, wherein in the oscillation circuit, the frequency division ratio of the frequency divider circuit is variable.