JPH09294071A - PLL synthesizer circuit - Google Patents

Abstract

(57) An object of the present invention is to reduce the spurious of a PLL synthesizer circuit that switches a plurality of variable oscillators having different frequency variable ranges to control an oscillation frequency in a wide band. SOLUTION: In a PLL synthesizer circuit that switches a plurality of variable oscillators having different frequency variable ranges and controls the oscillation frequency in a wide band, the oscillation signal of the variable oscillator is a power line,
It is input to the data latch circuit 130 via a switch and the like. When the data latch circuit 130, the programmable divider 70, the phase comparator 30 and the like are mounted at a high density in a small area such as the inside of the PLLIC, this oscillation signal is transmitted to the programmable divider 70, the phase comparator 30 and the like. The filters 100 and 110 having frequency characteristics that suppress the induced oscillation signal are provided because they are induced and generate spurious near the desired frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL synthesizer circuit that switches a plurality of variable oscillators having different frequency variable ranges to control an oscillation frequency in a wide band.

[0002]

2. Description of the Related Art In recent years, there has been a demand for an oscillator having a wide frequency variable range with low phase noise in digital broadcasting and communication. Therefore, a PLL synthesizer circuit that controls a frequency by switching a plurality of variable oscillators with one PLL circuit is used.

FIG. 3 shows a conventional PLL synthesizer circuit.

In the figure, 10 is a reference oscillator, 20 is a reference divider, 30 is a phase comparator, 40 is a loop filter, 50 is a variable oscillator, 60 is a variable oscillator, 70 is a programmable divider, 80 is a switch, and 90 is a switch. , 120 is a power supply circuit, 130 is a data latch circuit, 1
Reference numeral 40 is a control circuit, and 150 is a control data input terminal.

The PLL synthesizer circuit of FIG. 3 supplies power to only one of the variable oscillator 50 and the variable oscillator 60 having different frequency variable ranges to control the frequency in a wide band. In FIG. 3, there are only two variable oscillators 50 and 60, but when controlling three or more variable oscillators with different frequency variable ranges, similarly, power is supplied to only one variable oscillator and Control over a wide band.

The variable oscillators 50 and 60 are controlled by a control signal input from the control data input terminal 150 so as to oscillate at a desired frequency.

First, the PLL synthesizer circuit is controlled to oscillate at a frequency within the frequency variable range of the variable oscillator 50.

The control circuit 140 has a control data input terminal 1
The frequency division ratio N of the programmable divider 70 is set based on the control data input to the switch 50, and the switch 80
The data latch circuit 130 is controlled so that is turned on and the switch 90 is turned off. When the switches 80 and 90 are turned on, the power from the power supply circuit 120 is supplied to the variable oscillation circuits 50 and 6.
0, respectively, to operate, and when off, stop operation. Therefore, at this time, the variable oscillation circuit 50 operates and the variable oscillation circuit 60 stops operating.

The phase comparator 30 receives the oscillation signal of stable frequency from the reference oscillator 10 as the reference divider 20.
And the frequency divided by 1 / R (R is a natural number) with the frequency divided by the programmable divider 70 into the frequency of 1 / N (N is a natural number). A signal proportional to the phase difference is supplied to the loop filter 40. The loop filter 40 is the phase comparator 30.
Is smoothed, and the oscillation frequency of the variable oscillator 50 is controlled so that the phase difference between the signal from the reference divider 20 and the signal from the programmable divider 70 becomes zero.

When controlling the PLL synthesizer circuit so as to oscillate at a frequency within the frequency variable range of the variable oscillator 60, the control circuit 140 controls the control data input terminal 150.
The frequency division ratio N of the programmable divider 70 is set on the basis of the control data input to the data latch circuit 130, and the data latch circuit 130 is controlled so that the switch 80 is turned off and the switch 90 is turned on. The PLL synthesizer circuit controls the oscillation frequency of the variable oscillator 60 so that the phase difference between the signal from the reference divider 20 and the signal from the programmable divider 70 becomes zero.

[0011]

A data latch circuit, a programmable divider, a phase comparator, etc. are, for example, PL
If the variable oscillator is oscillated at a high frequency by the PLL synthesizer circuit when it is mounted at a high density in a small area such as the inside of the LIC, the oscillation signal of the variable oscillator is induced in the power supply line and the data latch circuit is passed through the switch. Is input to the programmable divider, the phase comparator, etc., spurious is generated in the vicinity of the desired frequency, and the phase noise is deteriorated.

An object of the present invention is to provide a PLL synthesizer circuit having a function of suppressing this spurious.

[0013]

In the present invention, a filter is inserted in the line from the switch to the data latch circuit in FIG. 3 to suppress the oscillation signal induced in the power source line of the variable oscillator, the programmable divider, and the phase comparison. Prevents malfunction of devices and suppresses spurious.

[0014]

1 is a block diagram showing a PLL synthesizer circuit as an embodiment of the present invention. In the figure, 51 is a power supply terminal of the variable oscillation circuit, and 61 is a power supply terminal of the variable oscillation circuit.

The PLL synthesizer circuit of FIG. 1 supplies power to only one of the variable oscillator 50 and the variable oscillator 60 having different frequency variable ranges to control the frequency in a wide band. In FIG. 1, only two variable oscillators, 50 and 60, exist, but when controlling three or more variable oscillators with different frequency variable ranges, similarly, power is supplied to only one variable oscillator to control the frequency. Control over a wide band.

The variable oscillators 50 and 60 are controlled by a control signal input from the control data input terminal 150 so as to oscillate at a desired frequency.

First, the PLL synthesizer circuit is controlled so as to oscillate at a frequency within the variable frequency range of the variable oscillator 50.

The control circuit 140 has a control data input terminal 1
The frequency division ratio N of the programmable divider 70 is set based on the control data input to the switch 50, and the switch 80
The data latch circuit 130 is controlled so that is turned on and the switch 90 is turned off. When the switches 80 and 90 are turned on, the power from the power supply circuit 120 is supplied to the variable oscillators 50 and 60.
Supply to each of them to operate, and when off, stop the operation. Therefore, at this time, the variable oscillation circuit 50 operates and the variable oscillation circuit 60 stops.

The phase comparator 30 receives the oscillation signal of the stable frequency from the reference oscillator 10 as the reference divider 20.
At a frequency of 1 / R and the oscillation signal from the variable oscillator 50 at a frequency of 1 / N by the programmable divider 70 are compared, and a signal proportional to the phase difference is loop-filtered. Supply to 40. The loop filter 40 smoothes the signal from the phase comparator 30 and controls the oscillation frequency of the variable oscillation circuit 50 so that the phase difference between the signal from the reference divider 20 and the signal from the programmable divider 70 becomes zero.

At this time, if the variable oscillation circuit 50 is oscillating at a high frequency, the oscillation signal induced in the power supply terminal 51 of the variable oscillation circuit passes through the switch 80 and is input to the data latch circuit 130. Further, depending on the implementation of the circuit of FIG. 1, although the variable oscillator 50 is oscillating, the oscillation signal hangs up on the printed circuit board, is induced in the power supply terminal 61 of the variable oscillation circuit, and passes through the switch 90. It may be input to the data latch circuit 130. When the data latch circuit 130, the programmable divider 70, the phase comparator 30 and the like are mounted at a high density in a small area such as the inside of a PLLIC, this oscillation signal causes the programmable divider 70 and the phase comparator 30 to output. And so on. This is a path different from the path of the signal considered in the original PLL synthesizer.
The synthesizer circuit causes spurious near the desired frequency and deteriorates the phase noise.

Therefore, the filters 100 and 110 having frequency characteristics that suppress the induced oscillation signal.
Is provided to prevent the oscillation signal induced in the data latch circuit 130 from being input. This suppresses spurious of the PLL synthesizer circuit and reduces phase noise.

When controlling the PLL synthesizer circuit so as to oscillate at a frequency within the frequency variable range of the variable oscillator 60, the control circuit 140 controls the control data input terminal 150.
The frequency division ratio N of the programmable divider 70 is set based on the control data input to the data latch circuit 130, and the data latch circuit 130 is controlled so that the switch 80 is turned off and the switch 90 is turned on. The PLL synthesizer circuit controls the oscillation frequency of the variable oscillator 60 so that the phase difference between the signal from the reference divider 20 and the signal from the programmable divider 70 becomes zero. Also at this time, spurious of the PLL synthesizer circuit is suppressed by the filter 100 and the filter 110, and the phase noise is reduced.

FIG. 2 shows an example of the PLL synthesizer circuit shown in FIG. In the figure, reference numeral 160 denotes a PLLIC, which includes a reference divider 20, a phase comparator 30, a programmable divider 70, a data latch circuit 130, and a control circuit 140.
And so on. Inside the PLLIC 160, the reference divider 20, the phase comparator 30, the programmable divider 70, the data latch circuit 130, the control circuit 1
Since 40 and the like are mounted in a small area with high density, when the oscillation signals of the variable oscillators 50 and 60 are oscillating at high frequency, they are induced in the power supply terminals 51 and 61 of the variable oscillation circuit, respectively, and the above-mentioned paths are generated. After that, it jumps into the PLLIC 160 and is guided to the programmable divider 70, the phase comparator 30, and the like. Capacitors are inserted as the filter 80 and the filter 90 to suppress the oscillation signal on the other path, suppress spurious near the desired frequency, and reduce phase noise. It should be noted that spurious can be suppressed similarly when three or more variable oscillators are used.

[0024]

When the data latch circuit, the programmable divider, the phase comparator, etc. are mounted at a high density in a small area such as the inside of the PLLIC, the variable frequency oscillator is oscillated at a high frequency by the PLL synthesizer circuit. At this time, the oscillation signal of the variable oscillator is induced in the power supply line, is input to the data latch circuit through the switch, is induced in the programmable divider, the phase comparator, etc., and causes spurious near a desired frequency to deteriorate the phase noise. The present invention suppresses spurious and suppresses phase noise of the oscillator by suppressing the oscillation signal that passes through this separate path.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment.

FIG. 2 is a circuit diagram of an embodiment.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of Codes] 10 ... Reference Oscillator, 20 ... Reference Divider, 30
... phase comparator, 40 ... loop filter, 50 ... variable oscillator, 51 ... variable oscillation circuit power supply terminal, 60 ... variable oscillator, 61 ... variable oscillation circuit power supply terminal, 70 ... programmable divider, 80 ... switch, 90 ... switch 10,
0 ... filter, 110 ... filter, 120 ... power supply circuit,
130 ... Data latch circuit, 140 ... Control circuit, 150
Control data input terminal, 160 ... PLLIC.

Continuation of the front page (72) Inventor Toshio Nagashima 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Multimedia system development headquarters

Claims (2)

[Claims] 1. A reference oscillator, a reference divider for dividing the oscillation frequency of the reference oscillator, a first variable oscillator, a second variable oscillator, and an oscillation frequency of the first or second variable oscillator. A programmable divider that divides the frequency by a dividing ratio, a switch that supplies power to only one of the first and second variable oscillators according to a desired oscillation frequency, and a data latch circuit that controls the switch. ,
A control circuit for controlling the data latch circuit and the programmable divider; a control data input terminal for inputting data for oscillating the first or second variable oscillator at a desired oscillation frequency to the control circuit; and the reference divider. And a phase comparator that compares the phases of the output signals of the programmable dividers and outputs a signal proportional to the error, a loop filter that smoothes the output signal of the phase comparator, and oscillates with the output signal of the loop filter. P for controlling the oscillation frequency of the first or second variable oscillator
A PLL synthesizer circuit, wherein a filter is provided between the switch and the data latch circuit in the LL synthesizer circuit. 2. A PLL synthesizer circuit using a low-pass filter as the loop filter according to claim 1.