JPH03218024A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including self-aligned transistors.

Conventional technology Semiconductor devices have been becoming more and more densely packed in recent years.
A need has arisen to form emitters that are smaller than patterns formed by photolithography.

A conventional method for manufacturing a semiconductor device will be described below.

FIGS. 2A to 2D show process cross-sectional views of a conventional semiconductor device manufacturing method. First, as shown in FIGS. Then, as shown in FIG. 2(b), using the resist as a mask, boron is implanted only into the base formation region using an ion implantation method at an acceleration energy of about 100 KeV. After implantation, annealing is performed for about 30 minutes in a nitrogen atmosphere at about 900° C. to form a p-type silicon base 107. Next, as shown in FIG. Using the resist as a mask, arsenic is implanted into the base 107 region by ion implantation at an acceleration energy of about 40 KeV, and boron is implanted into the external base region by ion implantation using the resist as a mask at an acceleration energy of about 100 KeV, followed by a nitrogen atmosphere at about 980°C. After about 20 minutes of annealing inside, Emisota 108
and form an external base 109. Next, Figure 2 fdl
As shown in FIG.
emitter electrodes 110- on each shaped silicon substrate 101.
1. Base electrode 110-2 and collector electrode 110-3
form. In this conventional example, an n-type silicon substrate 101 is used as a collector.

Problems to be Solved by the Invention However, the conventional method described above has the disadvantage that the width of the emitter is slightly larger than the size of the contact window opening pattern formed by photolithography, and it is not possible to form an emitter narrower than that. had.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that enables the formation of an emitter having a narrower emitter width than a pattern formed by photolithography.

Means for Solving the Problems To achieve this object, the method for manufacturing a semiconductor device of the present invention includes the steps of forming a first convex conductivity type semiconductor region on a one conductivity type semiconductor substrate, and then oxidizing the above-mentioned semiconductor region. 1st
forming a second one-conductivity type semiconductor region smaller than the convex one-conductivity type semiconductor region.

Effect: This manufacturing method allows a smaller pattern to be formed than a pattern formed by photolithography, so that a finer transistor can be formed.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 (al to ge) shows process cross-sectional views of a method for manufacturing a semiconductor device in an embodiment of the present invention. First, as shown in FIG. 1(a), a silicon oxide film 2 is formed to a thickness of about 200 layers and a silicon nitride film 3 is formed to a thickness of about 1000 layers on the surface of an n-type silicon substrate 1, and then a normal photolithography technique is used. Using etching technology, a silicon oxide film 2 and a silicon nitride film 3 are formed only on the emitter formation region of the transistor.
form. Next, as shown in FIG. 1(b), using the silicon oxide film 2 and the silicon nitride film 3 as an etching mask,
The n-type silicon substrate 1 is selectively etched by approximately 5,000 etches to form a first n-type silicon convex region 4 on the n-type silicon substrate 1. Next, as shown in FIG. 1C, using the silicon oxide film 2 and the silicon nitride film 3 as masks, the side surfaces of the n-type silicon substrate 1 and the n-type silicon convex region 4 are selectively oxidized, and a second A convex region 5 of n-type silicon and a selectively oxidized silicon film 6 are formed to a thickness of about 1 μm. Next, as shown in FIG. 1(d), after removing the silicon oxide film 2 and the silicon nitride film 3, boron is implanted into the lower part of the convex region 5 of the second n-type silicon by ion implantation with an acceleration energy of 100 KeV. Thereafter, annealing is performed for about 30 minutes in a nitrogen atmosphere at about 900° C. to form a p-type silicon base 7. Next, as shown in FIG. 1(e), a second n-type silicon convex region 5 is formed.
Arsenic is implanted into the upper part of the film by ion implantation with an acceleration energy of 100 KeV, and then annealing is performed for about 20 minutes in a nitrogen atmosphere at about 980° C. to form an n-type silicon emitter 8. After that, the selective oxide silicon film 6 A contact window of the n-type silicon substrate 1 and a base contact window are formed in the vicinity of the base 7 at predetermined positions by etching, and boron is diffused only in the base contact window by ion implantation or the like, and the base 7 is etched. An external base 9 is formed which is connected to the external base 9. Then the emitter 8 as shown in Figure 1 (fl)
, an emitter electrode 10-1, a base electrode 10-2, and a collector electrode 10-3 are formed on the external base 9 and the n-type silicon substrate 1, respectively. In this embodiment, an n-type silicon substrate 1 is used as a collector.

Note that a p-type silicon substrate may be used and the collector formed of an n-type buried layer or an n-type epitaxial layer may be formed.

Effects of the Invention As described above, the present invention defines the operating area of a transistor by etching, and further oxidizes the operating area to form a finer transistor operating area. can be manufactured.

[Brief explanation of drawings]

1 fa) to (fl are process cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 (al to (d)
1 is a process cross-sectional view of a conventional method for manufacturing a semiconductor device. 1... N-type silicon substrate, 2... Silicon oxide film, 3... Silicon nitride film, 4...
...First n-type silicon convex region, 5...Second n-type silicon convex region, 6...Selective silicon oxide film, 7...Base , 8...Emitter, 9...External head, 101...
Emitter electrode, 10-2...Base electrode, 10
-3...Collector electrode, 101...n
shaped silicon substrate, 102... silicon oxide film,
107...Base, 108...Emitter, 109...External base, 110-1...
... Emitter electrode, 1102 ... Base electrode, 110-3 ... Collector electrode.

Claims (1)

[Claims] forming a first convex one-conductivity type semiconductor region on the one-conductivity type semiconductor substrate by selectively etching the one-conductivity type semiconductor substrate; forming a second convex one-conductivity type semiconductor region smaller than the first convex one-conductivity type semiconductor region formed at the end of the etching by oxidizing the side surface of the semiconductor device. manufacturing method.