JPH03218034A - Semiconductor mounting board - Google Patents

Semiconductor mounting board

Info

Publication number
JPH03218034A
JPH03218034A JP2013412A JP1341290A JPH03218034A JP H03218034 A JPH03218034 A JP H03218034A JP 2013412 A JP2013412 A JP 2013412A JP 1341290 A JP1341290 A JP 1341290A JP H03218034 A JPH03218034 A JP H03218034A
Authority
JP
Japan
Prior art keywords
semiconductor element
bumps
substrate
board
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013412A
Other languages
Japanese (ja)
Inventor
Katsunori Nishiguchi
勝規 西口
Atsushi Miki
淳 三木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2013412A priority Critical patent/JPH03218034A/en
Priority to AU69822/91A priority patent/AU645283B2/en
Priority to CA002034703A priority patent/CA2034703A1/en
Priority to US07/644,587 priority patent/US5214308A/en
Priority to EP91100818A priority patent/EP0439134A2/en
Priority to KR91001104A priority patent/KR950001365B1/en
Publication of JPH03218034A publication Critical patent/JPH03218034A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07221Aligning
    • H10W72/07227Aligning involving guiding structures, e.g. spacers or supporting members
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the time and the cost necessary for mounting by forming recessed parts accepting at least the tip parts of bumps on a semiconductor, on a semiconductor element mounting board at electrode terminals. CONSTITUTION:A plurality of bumps 2 are formed on a semiconductor element 1 so as to protrude from the surface. On a board 3 on which the element 1 is mounted, a plurality of electrode terminals 5 are formed so as to correspond with the bumps 2. In order to form the terminal 5, a recess is formed at a part where the terminal 5 of the board 3 is formed, and the recess has a size capable of accepting at least the tip part of the bump 2. Said recess is selectively plated, thereby forming the terminal 5. Hence the bumps 2 on the element 1 can be accurately aligned with the terminals 5 on the board 3, only by pushing the element 1 on the board 3 after rough alignment, so that the time and the cost necessary for mounting can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ICチップ等の半導体素子が実装される半導
体素子実装用基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor element mounting substrate on which a semiconductor element such as an IC chip is mounted.

〔従来の技術〕[Conventional technology]

IC等の半導体素子を基板上に実装する場合に、半導体
素子の電極パッド上に凸状のバンプを形成し、このバン
プを基板上に形成されている電極端子上に直接接続する
ことが行われている。
When mounting a semiconductor element such as an IC on a substrate, a convex bump is formed on the electrode pad of the semiconductor element, and this bump is directly connected to the electrode terminal formed on the substrate. ing.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

基板上の電極端子は、従来、平坦に形成されていた。こ
のため、半導体素子上のバンプを基板上の電極端子に正
確に位置合せしなければ、バンプ材料が電極端子の周辺
部にはみ出し、隣接する電極端子同士を短絡させるおそ
れがあった。
Conventionally, electrode terminals on a substrate have been formed flat. For this reason, unless the bumps on the semiconductor element are accurately aligned with the electrode terminals on the substrate, there is a risk that the bump material will protrude to the periphery of the electrode terminals, causing a short circuit between adjacent electrode terminals.

また、半導体素子の集積度が高くなるほど、基板上に形
成される電極端子のサイズ及びピッチ間隔は小さくなる
。このため、高集積化が進むほどバンプと電極端子とを
非常に高い精度で位置合せする必要が生ずる。
Furthermore, the higher the degree of integration of semiconductor elements, the smaller the size and pitch of the electrode terminals formed on the substrate. Therefore, as the degree of integration increases, it becomes necessary to align bumps and electrode terminals with extremely high precision.

しかし、そのような高い精度での位置合せには、それな
りの時間が必要であり、実装に要する時間が長くなると
共に、高精度で高価な位置合せ装置を必要とする。この
ため、実装コストが高いものとなっていた。
However, alignment with such high precision requires a certain amount of time, increases the time required for implementation, and requires a highly accurate and expensive alignment device. For this reason, the implementation cost has been high.

そこで、上述の事情に鑑み、本発明は実装に要する時間
を短縮すると共に、実装コストを低減することを目的と
している。
Therefore, in view of the above-mentioned circumstances, the present invention aims to shorten the time required for implementation and reduce the implementation cost.

〔課題を解決するための手段〕[Means to solve the problem]

上述の目的を達成するため、本発明による半導体素子実
装用基板においては、基板上の電極端子に半導体素子上
のバンプの少なくとも頂部を受容する四部が形成されて
いることを特徴としている。
In order to achieve the above object, the substrate for mounting a semiconductor element according to the present invention is characterized in that an electrode terminal on the substrate is formed with four parts that receive at least the tops of bumps on the semiconductor element.

〔作用〕[Effect]

このようにすることにより、大まかな位置合せ後に半導
体素子を基板に押し付けるだけで、半導体素子上のバン
プが基板上の電極端子に対して正確に位置合せされる。
By doing so, the bumps on the semiconductor element can be accurately aligned with the electrode terminals on the substrate simply by pressing the semiconductor element against the substrate after rough alignment.

〔実施例〕〔Example〕

以下、本発明の実施例について第1図及び第2図を参照
しつつ、説明する。
Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

第1図は本発明による半導体素子実装用基板とその電極
端子に対して大まかに位置合せされた半導体素子とを示
しており、第2図は実装後の状態を示している。
FIG. 1 shows a substrate for mounting a semiconductor element according to the present invention and a semiconductor element roughly aligned with its electrode terminals, and FIG. 2 shows the state after mounting.

図示したように、半導体素子1にはその表面から突出し
て複数のバンプ2が形成されている。
As shown in the figure, a plurality of bumps 2 are formed on the semiconductor element 1 so as to protrude from the surface thereof.

他方、半導体素子1か実装される基板3には、半導体素
子1上のバンプ2に対応して複数の電極端子5が形成さ
れている。この電極端子5は、例えば次のようにして形
成される。まず、基板3の電極端子5が形成される部分
に窪みを形成する。
On the other hand, a plurality of electrode terminals 5 are formed on the substrate 3 on which the semiconductor element 1 is mounted, corresponding to the bumps 2 on the semiconductor element 1. This electrode terminal 5 is formed, for example, as follows. First, a depression is formed in a portion of the substrate 3 where the electrode terminal 5 is to be formed.

この窪みは半導体素子1上に形成されているバンプ2の
少なくとも頂部(図では下端部)を受容し得る程度の大
きさに形成される。そして、この窪みに選択的にメッキ
を施すなどして電極端子5が形成される。このようにし
て形成された電極端子5は、その表面にバンプ2の少な
くとも頂部を受容する凹部4を有している。なお、この
凹部4の最も深い位置(最も低い位置)に電極端子5の
中心が一致していることが好ましい。
This depression is formed in a size large enough to receive at least the top (lower end in the figure) of the bump 2 formed on the semiconductor element 1. Then, the electrode terminal 5 is formed by selectively plating the depression. The electrode terminal 5 thus formed has a recess 4 on its surface for receiving at least the top of the bump 2. Note that it is preferable that the center of the electrode terminal 5 coincides with the deepest position (lowest position) of the recess 4.

このように形成された基板3に対して、半導体素子1を
実装する場合、半導体素子1上のバンプ2と基板3上の
電極端子5との位置合せが図示しない位置合せ装置によ
り行われるが、この位置合せは、第1図に示したように
、バンプ2の頂部が電極端子5の凹部4内からはみ出さ
ない程度の大まかな位置合せで足りる。なぜなら、バン
プ2の頂部が電極端子5の四部4内に納まる範囲内に位
置合せされていれば、この位置合せの後に半導体素子1
を基板3に対して軽く押し付けることにより、第2図に
示したように、バンプ2は電極端子5の四部4の表面に
沿って案内されて電極端子5の中央部に自動的に移動し
、バンプ2と電極端子5とが互いに正確に位置合せされ
るからである。
When mounting the semiconductor element 1 on the substrate 3 formed in this way, the bumps 2 on the semiconductor element 1 and the electrode terminals 5 on the substrate 3 are aligned by an alignment device (not shown). As shown in FIG. 1, this alignment may be done roughly to the extent that the tops of the bumps 2 do not protrude from the recesses 4 of the electrode terminals 5. This is because if the top of the bump 2 is aligned within the range that fits within the four parts 4 of the electrode terminal 5, then after this alignment the semiconductor element 1
By lightly pressing the bump 2 against the substrate 3, the bump 2 is guided along the surfaces of the four parts 4 of the electrode terminal 5 and automatically moves to the center of the electrode terminal 5, as shown in FIG. This is because the bump 2 and the electrode terminal 5 are accurately aligned with each other.

このようにして正確な位置合せが行われた後、基板3を
加熱してバンプ2を溶融し、バンプ2と電極端子5とが
互いに接続される。このように、バンプ2を溶融させる
場合には、溶融したバンプ材の表面張力がバンプ2の形
成されている半導体素子1上の電極パッド(図示せず)
と基板3上の電極端子5との間で、バンプ材の表面積を
できるだけ小さくする方向に作用する。したがって、こ
の表面張力はバンプ2が形成されている半導体素子1上
の各電極パッドと基板3上の各電極端子5との総合的な
位置ズレを最も小さくする方向に作用し、半導体素子1
は各バンプ材の表面張力が互いに釣り合う位置に誘導さ
れる。すなわち、この表面張力によって、より一層正確
な位置合せが自動的に行われるのである。なお、電極端
子に予備ハンダを施しておき、これをリフローした場合
にも、溶融したハンダの表面張力が同様に作用する。
After accurate alignment is performed in this way, the substrate 3 is heated to melt the bumps 2, and the bumps 2 and the electrode terminals 5 are connected to each other. In this way, when the bumps 2 are melted, the surface tension of the melted bump material is applied to the electrode pads (not shown) on the semiconductor element 1 on which the bumps 2 are formed.
and the electrode terminal 5 on the substrate 3, the surface area of the bump material is reduced as much as possible. Therefore, this surface tension acts in a direction that minimizes the overall positional deviation between each electrode pad on the semiconductor element 1 on which the bump 2 is formed and each electrode terminal 5 on the substrate 3, and
are guided to a position where the surface tensions of each bump material balance each other. In other words, this surface tension automatically achieves even more accurate alignment. Note that even if preliminary solder is applied to the electrode terminal and this is reflowed, the surface tension of the molten solder acts in the same way.

なお、バンプ2を溶融させる代わりに、硬化すると収縮
する絶縁性の接着剤を半導体素子1と基板3の相互間に
充填し、接着剤の硬化収縮力でバンプ2を電極端子5に
押し付け、バンプ2と電極端子5相互間の電気的導通を
とるようにしてもよい。
Note that instead of melting the bumps 2, an insulating adhesive that shrinks when cured is filled between the semiconductor element 1 and the substrate 3, and the bumps 2 are pressed against the electrode terminals 5 by the curing shrinkage force of the adhesive. 2 and the electrode terminal 5 may be electrically connected to each other.

半導体素子1上に形成されるバンプ2のサイズを直径8
0μm1高さ約30μmとし、また、基板3上の電極端
子5のサイズを直径100μm1その凹部4の外径を電
極端子の直径とほぼ等しくし、その四部4の深さを約1
0μmとして、半導体素子1を基板3に実装した。この
場合に、実装後のバンプ2と電極端子5の位置ズレを±
10μm以内に納めるために、位置合せ装置に要求され
る位置合せ精度は±50μmであった。これに対して、
上述の例と同寸法の平坦な電極端子が形成された従来の
基板に、上述した例と同じ半導体素子を実装したところ
、位置合せ装置に同様に要求される精度は±10μmで
あった。この結果を下表に示す。
The size of the bump 2 formed on the semiconductor element 1 is 8 in diameter.
The size of the electrode terminal 5 on the substrate 3 is 100 μm in diameter, the outer diameter of the recess 4 is approximately equal to the diameter of the electrode terminal, and the depth of the four parts 4 is approximately 1 μm.
The semiconductor element 1 was mounted on the substrate 3 with a thickness of 0 μm. In this case, the positional deviation between bump 2 and electrode terminal 5 after mounting should be
In order to keep the alignment accuracy within 10 μm, the alignment accuracy required of the alignment device was ±50 μm. On the contrary,
When the same semiconductor element as in the above example was mounted on a conventional substrate on which flat electrode terminals with the same dimensions as in the above example were formed, the accuracy required for the alignment device was ±10 μm. The results are shown in the table below.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば従来のように高精
度で高価な位置合せ装置を必要とせず、比較的安価な位
置合せ装置を用いることができる。
As described above, according to the present invention, a relatively inexpensive alignment device can be used instead of requiring a highly accurate and expensive alignment device as in the prior art.

また、位置合せ装置による位置合せは、大まかなもので
足りるので、位置合せ装置による精密な位置合せを必要
としていた従来に比し、位置合せ装置による位置合せに
必要とされる時間が短くなる。
Furthermore, since only rough alignment is required by the alignment device, the time required for alignment by the alignment device is shorter than in the past, which required precise alignment by the alignment device.

したがって、実装に要する時間及びコストを低減するこ
とができる。
Therefore, the time and cost required for implementation can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による半導体素子実装用基板とその電極
端子に対して大まかに位置合せされた半導体素子とを示
した図、第2図はそれらの実装後の状態を示した図であ
る。 1・・・半導体素子、2・・・バンプ、3・・・基板、
4・・・凹部、5・・・電極端子。
FIG. 1 is a diagram showing a substrate for mounting a semiconductor element according to the present invention and a semiconductor element roughly aligned with its electrode terminal, and FIG. 2 is a diagram showing the state after mounting them. 1... Semiconductor element, 2... Bump, 3... Substrate,
4... Recessed portion, 5... Electrode terminal.

Claims (1)

【特許請求の範囲】 表面にバンプを有する半導体素子が実装される基板であ
って、 前記バンプが接続される電極端子を有しており、前記電
極端子には前記バンプの少なくとも頂部を受容する凹部
が形成されていることを特徴とする半導体素子実装用基
板。
[Scope of Claims] A substrate on which a semiconductor element having bumps on the surface is mounted, comprising an electrode terminal to which the bump is connected, and the electrode terminal has a recess for receiving at least the top of the bump. 1. A substrate for mounting a semiconductor element, characterized in that: is formed.
JP2013412A 1990-01-23 1990-01-23 Semiconductor mounting board Pending JPH03218034A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2013412A JPH03218034A (en) 1990-01-23 1990-01-23 Semiconductor mounting board
AU69822/91A AU645283B2 (en) 1990-01-23 1991-01-22 Substrate for packaging a semiconductor device
CA002034703A CA2034703A1 (en) 1990-01-23 1991-01-22 Substrate for packaging a semiconductor device
US07/644,587 US5214308A (en) 1990-01-23 1991-01-23 Substrate for packaging a semiconductor device
EP91100818A EP0439134A2 (en) 1990-01-23 1991-01-23 Substrate for packaging a semiconductor device, packaging structure and method
KR91001104A KR950001365B1 (en) 1990-01-23 1991-01-23 Substrate for packaging a semiconductor device, packaging structure and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013412A JPH03218034A (en) 1990-01-23 1990-01-23 Semiconductor mounting board

Publications (1)

Publication Number Publication Date
JPH03218034A true JPH03218034A (en) 1991-09-25

Family

ID=11832423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013412A Pending JPH03218034A (en) 1990-01-23 1990-01-23 Semiconductor mounting board

Country Status (1)

Country Link
JP (1) JPH03218034A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8503025B2 (en) 2009-03-18 2013-08-06 Ricoh Company, Limited Image processing apparatus, image processing method, and computer program product
US9837657B2 (en) 2014-12-11 2017-12-05 Toyota Jidosha Kabushiki Kaisha Assembled battery

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8503025B2 (en) 2009-03-18 2013-08-06 Ricoh Company, Limited Image processing apparatus, image processing method, and computer program product
US9837657B2 (en) 2014-12-11 2017-12-05 Toyota Jidosha Kabushiki Kaisha Assembled battery

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