JPH03218035A - Semiconductor element mounting board - Google Patents
Semiconductor element mounting boardInfo
- Publication number
- JPH03218035A JPH03218035A JP2013413A JP1341390A JPH03218035A JP H03218035 A JPH03218035 A JP H03218035A JP 2013413 A JP2013413 A JP 2013413A JP 1341390 A JP1341390 A JP 1341390A JP H03218035 A JPH03218035 A JP H03218035A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- bumps
- substrate
- bump
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07221—Aligning
- H10W72/07227—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ICチップ等の半導体素子が実装される半導
体素子実装用基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor element mounting substrate on which a semiconductor element such as an IC chip is mounted.
IC等の半導体素子を基板上に実装する場合に、半導体
素子の電極パッド上に凸状のバンプを形成し、このバン
プを基板上に形成されている電極端子上に直接接続する
ことが行われている。When mounting a semiconductor element such as an IC on a substrate, a convex bump is formed on the electrode pad of the semiconductor element, and this bump is directly connected to the electrode terminal formed on the substrate. ing.
基板上の電極端子は、従来、平坦に形成されていた。こ
のため、半導体素子上のバンプを基板上の電極端子に正
確に位置合せしなければ、バンプ材料が電極端子の周辺
部にはみ出し、隣接する電極端子同士を短絡させるおそ
れがあった。Conventionally, electrode terminals on a substrate have been formed flat. For this reason, unless the bumps on the semiconductor element are accurately aligned with the electrode terminals on the substrate, there is a risk that the bump material will protrude to the periphery of the electrode terminals, causing a short circuit between adjacent electrode terminals.
また、半導体素子の集積度が高くなるほど、基板上に形
成される電極端子のサイズ及びピッチ間隔は小さくなる
。このため、高集積化が進むほどバンプと電極端子とを
非常に高い精度で位置合せする必要が生ずる。Furthermore, the higher the degree of integration of semiconductor elements, the smaller the size and pitch of the electrode terminals formed on the substrate. Therefore, as the degree of integration increases, it becomes necessary to align bumps and electrode terminals with extremely high precision.
しかし、そのような高い精度での位置合せには、それな
りの時間が必要であり、実装に要する時間が長くなると
共に、高精度で高価な位置合せ装置を必要とする。この
ため、実装コストが高いものとなっていた。However, alignment with such high precision requires a certain amount of time, increases the time required for implementation, and requires a highly accurate and expensive alignment device. For this reason, the implementation cost has been high.
そこで、上述の事情に鑑み、本発明は実装に要する時間
を短縮すると共に、実装コストを低減することを目的と
している。Therefore, in view of the above-mentioned circumstances, the present invention aims to shorten the time required for implementation and reduce the implementation cost.
上述の目的を達成するため、本発明による半導体素子実
装用基板においては、その表面に外周部から中央部に向
かって徐々に深くなると共に、半導体素子上のバンプの
少なくとも頂部を受容する凹部が形成されており、この
凹部の中央部にバンプと接続される電極端子が形成され
た構成となっている。In order to achieve the above object, in the substrate for mounting a semiconductor element according to the present invention, a recess is formed on the surface of the substrate, the recess gradually deepening from the outer periphery toward the center and receiving at least the top of the bump on the semiconductor element. An electrode terminal connected to the bump is formed in the center of the recess.
このようにすることにより、大まかな位置合せ後に半導
体素子を基板に押し付けるだけで、半導体素子上のバン
プが基板上の電極端子に対して正確に位置合せされる。By doing so, the bumps on the semiconductor element can be accurately aligned with the electrode terminals on the substrate simply by pressing the semiconductor element against the substrate after rough alignment.
以下、本発明の実施例について第1図及び第2図を参照
しつつ、説明する。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.
第1図は本発明による半導体素子実装用基板とその電極
端子に対して大まかに位置合せされた半導体素子とを示
しており、第2図は実装後の状態を示している。FIG. 1 shows a substrate for mounting a semiconductor element according to the present invention and a semiconductor element roughly aligned with its electrode terminals, and FIG. 2 shows the state after mounting.
図示したように、半導体素子1にはその表面から突出し
て複数のバンプ2が形成されている。As shown in the figure, a plurality of bumps 2 are formed on the semiconductor element 1 so as to protrude from the surface thereof.
他方、半導体素子1が実装される基板3には、半導体素
子1上のバンプに対応して複数の凹部4が形成されてお
り、この凹部4の中央部に電極端子5が形成されている
。凹部4は半導体素子1上に形成されているバンプ2の
少なくとも頂部(図では下端部)を受容し得る程度の大
きさに形成され、その外周部から電極端子5が形成され
る中央部に向かって徐々に深くなるように形成されてい
る。なお、図示したように、凹部4は階段状に徐々に深
くなっていてもよいし、外周部から中央部にかけて平滑
な面で徐々に深くなっていてもよい。On the other hand, a plurality of recesses 4 are formed in the substrate 3 on which the semiconductor element 1 is mounted, corresponding to the bumps on the semiconductor element 1, and an electrode terminal 5 is formed in the center of the recess 4. The recess 4 is formed in a size large enough to receive at least the top (lower end in the figure) of the bump 2 formed on the semiconductor element 1, and extends from the outer periphery toward the center where the electrode terminal 5 is formed. It is formed so that it gradually becomes deeper. In addition, as shown in the figure, the recess 4 may be gradually deepened in a step-like manner, or may be a smooth surface that gradually becomes deeper from the outer periphery to the center.
そして、電極端子5は、例えばこの凹部4の中央部に選
択的にメッキを施すことにより形成される。The electrode terminal 5 is formed, for example, by selectively plating the center of the recess 4.
このように凹部4及び電極端子5が形成された基板3に
対して、半導体素子1を実装する場合、半導体素子1上
のバンプ2と基板3上の電極端子5との位置合せが図示
しない位置合せ装置により行われるが、この位置合せは
、第1図に示したように、バンプ2の頂部が凹部4内に
からはみ出さない程度の大まかな位置合せで足りる。な
ぜなら、バンプ2の頂部が凹部4内に納まる範囲内に位
置合せされていれば、この位置合せの後に半導体素子1
を基板3に対して軽く押し付けることにより、第2図に
示したように、バンプ2は凹部4の表面に案内されて電
極端子5が形成されている凹部4の中央部に自動的に移
動し、バンプ2と電極端子5とが互いに正確に位置合せ
されるからである。When mounting the semiconductor element 1 on the substrate 3 in which the recess 4 and the electrode terminal 5 are formed in this way, the bumps 2 on the semiconductor element 1 and the electrode terminal 5 on the substrate 3 are aligned at a position not shown. This alignment is carried out by an alignment device, but as shown in FIG. 1, rough alignment is sufficient to prevent the top of the bump 2 from protruding into the recess 4. This is because if the top of the bump 2 is aligned within the range that fits within the recess 4, then after this alignment the semiconductor element 1
By lightly pressing the bump 2 against the substrate 3, the bump 2 is guided by the surface of the recess 4 and automatically moves to the center of the recess 4 where the electrode terminal 5 is formed, as shown in FIG. This is because the bump 2 and the electrode terminal 5 are accurately aligned with each other.
このようにして正確な位置合せが行われた後、基板3を
加熱してバンプ2を溶融し、バンプ2と電極端子5とが
互いに接続される。このように、バンプ2を溶融させる
場合には、溶融したバンプ材の表面張力がバンプ2が形
成されている半導体素子1上の電極パッド(図示せず)
と基板3上の電極端子5との間で、バンプ材の表面積を
できるだけ小さくする方向に作用する。したがって、こ
の表面張力はバンプ2が形成されている半導体素子1上
の各電極パッドと基板3上の各電極端子5との総合的な
位置ズレを最も小さくする方向に作用し、半導体素子1
は各バンプ材の表面張力が互いに釣り合う位置に誘導さ
れる。すなわち、この表面張力によって、より一層正確
な位置合せが自動的に行われるのである。After accurate alignment is performed in this way, the substrate 3 is heated to melt the bumps 2, and the bumps 2 and the electrode terminals 5 are connected to each other. In this way, when the bumps 2 are melted, the surface tension of the melted bump material is applied to the electrode pads (not shown) on the semiconductor element 1 on which the bumps 2 are formed.
and the electrode terminal 5 on the substrate 3, the surface area of the bump material is reduced as much as possible. Therefore, this surface tension acts in a direction that minimizes the overall positional deviation between each electrode pad on the semiconductor element 1 on which the bump 2 is formed and each electrode terminal 5 on the substrate 3, and
are guided to a position where the surface tensions of each bump material balance each other. In other words, this surface tension automatically achieves even more accurate alignment.
なお、バンプ2を溶融させる代わりに、硬化すると収縮
する絶縁性の接着剤を半導体素子1と基板3の相互間に
充填し、接着剤の硬化収縮力でバンプ2を電極端子5に
押し付け、バンプ2と電極端子5相互間の電気的導通を
とるようにしてもよい。Note that instead of melting the bumps 2, an insulating adhesive that shrinks when cured is filled between the semiconductor element 1 and the substrate 3, and the bumps 2 are pressed against the electrode terminals 5 by the curing shrinkage force of the adhesive. 2 and the electrode terminal 5 may be electrically connected to each other.
半導体素子1上に形成されるバンプ2のサイズを直径8
0μm1高さ約30μmとし、また、基板3に形成され
る凹部4の中央部に形成される電極端子5のサイズを直
径100μmとして、半導体素子1を基板3に実装した
。この場合に、実装後のバンプ2と電極端子5の位置ズ
レを±10μm以内に納めるために、位置合せ装置に要
求される位置合せ精度は基板3に形成された凹部4の外
周半径程度(±50μm以上)であった。これに対して
、上述の例と同寸法の平坦な電極端子が形成された従来
の基板に、上述した例と同じ半導体素子を実装したとこ
ろ、位置合せ装置に同様に要求される精度は±10μm
であった。この結果を下表に示す。The size of the bump 2 formed on the semiconductor element 1 is 8 in diameter.
The semiconductor element 1 was mounted on the substrate 3 with a height of 0 μm and a height of about 30 μm, and an electrode terminal 5 formed in the center of the recess 4 formed in the substrate 3 with a diameter of 100 μm. In this case, in order to keep the positional deviation between the bump 2 and the electrode terminal 5 after mounting within ±10 μm, the alignment accuracy required of the alignment device is approximately the outer radius of the recess 4 formed on the substrate 3 (± 50 μm or more). On the other hand, when the same semiconductor element as in the above example was mounted on a conventional substrate on which flat electrode terminals with the same dimensions as in the above example were formed, the accuracy required for the alignment device was ±10 μm.
Met. The results are shown in the table below.
以上説明したように、本発明によれば従来のように高精
度で高価な位置合せ装置を必要とせず、比較的安価な位
置合せ装置を用いることができる。As described above, according to the present invention, a relatively inexpensive alignment device can be used instead of requiring a highly accurate and expensive alignment device as in the prior art.
また、位置合せ装置による位置合せは、大まかなもので
足りるので、位置合せ装置による精密な位置合せを必要
としていた従来に比べ、位置合せ装置による位置合せに
必要とされる時間が短くなる。Furthermore, since only rough alignment is required by the alignment device, the time required for alignment by the alignment device is shorter than in the past, which required precise alignment by the alignment device.
したがって、実装に要する時間及びコストを低減するこ
とができる。Therefore, the time and cost required for implementation can be reduced.
第1図は本発明による半導体素子実装用基板とその電極
端子に対して大まかに位置合せされた半導体素子とを示
した図、第2図はそれらの実装後の状態を示した図であ
る。
1・・・半導体素子、2・・・バンプ、3・・・基板、
4・・・凹部、5・・・電極端子。FIG. 1 is a diagram showing a substrate for mounting a semiconductor element according to the present invention and a semiconductor element roughly aligned with its electrode terminal, and FIG. 2 is a diagram showing the state after mounting them. 1... Semiconductor element, 2... Bump, 3... Substrate,
4... Recessed portion, 5... Electrode terminal.
Claims (1)
って、 その表面に外周部から中央部に向かって深くなると共に
、前記バンプの少なくとも頂部を受容する凹部が形成さ
れており、 この凹部の中央部に前記バンプと接続される電極端子が
形成されていることを特徴とする半導体素子実装用基板
。[Scope of Claims] A substrate on which a semiconductor element having bumps on the surface is mounted, wherein a recess is formed in the surface, the recess deepening from the outer periphery toward the center and receiving at least the top of the bump. A substrate for mounting a semiconductor element, wherein an electrode terminal connected to the bump is formed in the center of the recess.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013413A JPH03218035A (en) | 1990-01-23 | 1990-01-23 | Semiconductor element mounting board |
| AU69822/91A AU645283B2 (en) | 1990-01-23 | 1991-01-22 | Substrate for packaging a semiconductor device |
| CA002034703A CA2034703A1 (en) | 1990-01-23 | 1991-01-22 | Substrate for packaging a semiconductor device |
| US07/644,587 US5214308A (en) | 1990-01-23 | 1991-01-23 | Substrate for packaging a semiconductor device |
| EP91100818A EP0439134A2 (en) | 1990-01-23 | 1991-01-23 | Substrate for packaging a semiconductor device, packaging structure and method |
| KR91001104A KR950001365B1 (en) | 1990-01-23 | 1991-01-23 | Substrate for packaging a semiconductor device, packaging structure and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013413A JPH03218035A (en) | 1990-01-23 | 1990-01-23 | Semiconductor element mounting board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03218035A true JPH03218035A (en) | 1991-09-25 |
Family
ID=11832452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013413A Pending JPH03218035A (en) | 1990-01-23 | 1990-01-23 | Semiconductor element mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03218035A (en) |
-
1990
- 1990-01-23 JP JP2013413A patent/JPH03218035A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5214308A (en) | Substrate for packaging a semiconductor device | |
| JP3233535B2 (en) | Semiconductor device and manufacturing method thereof | |
| US4957882A (en) | Method for manufacturing semiconductor device | |
| US6759737B2 (en) | Semiconductor package including stacked chips with aligned input/output pads | |
| KR970067801A (en) | Semiconductor device and manufacturing method thereof | |
| US5952717A (en) | Semiconductor device and method for producing the same | |
| KR100367955B1 (en) | Semiconductor device having reinforced coupling between solder balls and substrate | |
| US7893550B2 (en) | Semiconductor package comprising alignment members | |
| US6593652B2 (en) | Semiconductor device reinforced by a highly elastic member made of a synthetic resin | |
| JPH05144880A (en) | Electrode structure of wiring board | |
| JPH03218034A (en) | Semiconductor mounting board | |
| JPH03218035A (en) | Semiconductor element mounting board | |
| JPH08203956A (en) | Electronic component manufacturing method and electronic component | |
| JPH03218039A (en) | Mounting method of semiconductor element | |
| KR20010014797A (en) | Semiconductor device and method of making the same | |
| JPH03218037A (en) | Semiconductor element mounting board | |
| JPH03218036A (en) | Semiconductor element mounting board | |
| US6229222B1 (en) | Semiconductor device and method of fabricating the same | |
| JP2001284400A (en) | Flip chip mounting parts | |
| KR101716253B1 (en) | Method for fabricating a flip chip package and a flip chip package using the same | |
| US20090321120A1 (en) | Printed circuit board and electronic device | |
| KR100309460B1 (en) | Stack chip size package and manufacturing method thereof | |
| JPH0737932A (en) | Semiconductor device and mounting method thereof | |
| JP3745106B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR19980043253A (en) | Chip on Board Semiconductor Chip Packages |