JPH03218050A - gallium arsenide diode - Google Patents
gallium arsenide diodeInfo
- Publication number
- JPH03218050A JPH03218050A JP2014124A JP1412490A JPH03218050A JP H03218050 A JPH03218050 A JP H03218050A JP 2014124 A JP2014124 A JP 2014124A JP 1412490 A JP1412490 A JP 1412490A JP H03218050 A JPH03218050 A JP H03218050A
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- chip
- diode
- substrate
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Dicing (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、発光ダイオード，高速ダイオードまたは容量
可変ダイオード等に利用されるガリウムヒ素ダイオード
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a gallium arsenide diode used as a light emitting diode, a high speed diode, a variable capacitance diode, or the like.
従来の技術
第２図は、従来のガリウムヒ素（以下ＧａＡｓと記す）
ダイオードのチップを示したもので、１１はＧａＡｓ基
板、１２は電極で、１３はスクライブラインテあり、Ｇ
ａＡｓ基板１１の［０ １ １］および［０ １ １１
方向に、平行に形成されている。Conventional technology Figure 2 shows conventional gallium arsenide (hereinafter referred to as GaAs).
This figure shows a diode chip. 11 is a GaAs substrate, 12 is an electrode, 13 is a scribe line, and a G
[0 1 1] and [0 1 11] of the aAs substrate 11
It is formed parallel to the direction.
１４は基板１１のオリエンタルフラット（以下０．Ｆ．
）である。14 is an oriental flat (hereinafter referred to as 0.F.
).
発明が解決しようとする課題
しかしながら従来の構成では、チップをプラスチックパ
ッケージに封入した場合、通常の組み立て方法では、Ｇ
ａ Ａ ｓ基板の臂開方向である［０ １ １Ｆおよ
び［０ １ １１の方向がパッケージの端面に対して平
行になるため、パッケージのたわみ等によるストレスが
、チップのＧａＡｓ基板の臂開方向に対して垂直に加わ
り、チップクラックが発生しやすいという欠点を有して
いた。Problems to be Solved by the Invention However, in the conventional configuration, when a chip is enclosed in a plastic package, the G
Since the [0 1 1F and [0 1 11] directions, which are the directions in which the arms of the a A s substrate open, are parallel to the end face of the package, stress caused by bending of the package, etc., is applied in the direction of the opening of the GaAs substrate of the chip. This has the disadvantage that chip cracks are likely to occur because the chips are applied perpendicularly to the other surface.
本発明は、上記従来の問題点を解決するもので、パッケ
ージに封入時、または封入後のチップに加わるストレス
による故障の発生率を低下させることが可能なＧａＡｓ
ダイオードを提供することを目的とする。The present invention solves the above-mentioned conventional problems, and the present invention uses GaAs that can reduce the incidence of failure due to the stress applied to the chip when it is sealed in a package or after it is sealed.
The purpose is to provide diodes.
課題を解決するための手段
この目的を解決するために本発明のＧａＡｓダイオード
は、スクライブラインの方向がＧａＡｓ基板の［０ １
０］および［０ ０ １１方向に平行な構成を有して
いる。Means for Solving the Problem To solve this object, the GaAs diode of the present invention has a scribe line whose direction is [0 1
0] and [0 0 11 directions.
作用
この構成によって、ＧａＡｓの臂開方向は、パッケージ
に対して４５°回転を行なった方向をなすため、パッケ
ージからの応力が、ＧａＡｓの臂開方向に対して垂直に
加わることを回避することができ、パッケージストレス
によるチップクラックの発生する確率を低減することが
可能である。Effect: With this configuration, the arm-opening direction of GaAs is rotated by 45 degrees with respect to the package, so it is possible to avoid stress from the package being applied perpendicularly to the arm-opening direction of GaAs. This makes it possible to reduce the probability of chip cracks occurring due to package stress.
実施例
以下本発明の一実施例について図面を参照しながら説明
する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図は本発明のＱａＡｓ基板１内に多数含まれるダイ
オードの代表的な、拡大されたダイオード・チップ２を
示すものである。３はダイオード・チップ上に形成され
た電極、４はスクライブラインである。５は基板１の結
晶方向を示すＯ． Ｆ．であり、ＧａＡｓ基板１の［０
１ ０］方向に設けられている。FIG. 1 shows an enlarged diode chip 2 representative of the large number of diodes included in the QaAs substrate 1 of the present invention. 3 is an electrode formed on the diode chip, and 4 is a scribe line. 5 indicates the crystal direction of the substrate 1. F. , and [0
1 0] direction.
以上のように構成されたＧａＡｓダイオードでは、０．
Ｆ．が［０ １ ０］方向に垂直に設けられているため
、従来と全く同一のマスクおよびプロセスを用いて、ス
クライブラインが、［０１０］および［０ ０ １］方
向となるのでＧａＡｓの臂開方向に対して４５°の角度
となり、その結果パッケージストレスによるチップクラ
ックの発生率を低減したＧａＡｓ容量可変ダイオードを
実現することができる。In the GaAs diode configured as described above, 0.
F. is provided perpendicular to the [0 1 0] direction, so using the same mask and process as before, the scribe lines are in the [010] and [0 0 1] directions, so the arm opening direction of GaAs As a result, it is possible to realize a GaAs variable capacitance diode in which the incidence of chip cracks due to package stress is reduced.
なお、通常のウェハを用い、マスク上でパターンを４５
°回転させて形成させた場合およびパターン形成時にウ
ェハを４５°回転させた場合も、同様に本発明のＧａＡ
ｓダイオードが得られることは言うまでもない。In addition, using a regular wafer, the pattern is 45 times thick on the mask.
Similarly, when the wafer is formed by rotating the wafer by 45° and when the wafer is rotated by 45° during pattern formation, the GaA of the present invention
Needless to say, an S diode can be obtained.
発明の効果
以上のように本発明は、スクライブラインを、ＧａＡｓ
基板の［０ １ ０］および［００１コ方向に形成する
ことにより、パッケージストレスによるチップクラック
等の発生率の低減化を図ったＧａＡｓダイオードが実現
できる。Effects of the Invention As described above, the present invention provides a scribe line made of GaAs.
By forming it in the [0 1 0] and [001 co-directions of the substrate, it is possible to realize a GaAs diode in which the incidence of chip cracks and the like due to package stress is reduced.
第１図は本発明の実施例における基板内に形成されたＧ
ａＡｓダイオード・チップの部分拡大図、第２図は従来
の基板内に形成されたＧａＡｓダイオード・チップの部
分拡大図である。
４・・・・・・スクライブライン。FIG. 1 shows G formed in a substrate in an embodiment of the present invention.
FIG. 2 is a partial enlarged view of a GaAs diode chip formed in a conventional substrate. 4...Scribe line.
Claims (1)
あるガリウムヒ素ダイオード。A gallium arsenide diode with scribe lines in the [010] and [001] directions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014124A JPH03218050A (en) | 1990-01-23 | 1990-01-23 | gallium arsenide diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014124A JPH03218050A (en) | 1990-01-23 | 1990-01-23 | gallium arsenide diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03218050A true JPH03218050A (en) | 1991-09-25 |
Family
ID=11852378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014124A Pending JPH03218050A (en) | 1990-01-23 | 1990-01-23 | gallium arsenide diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03218050A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5182233A (en) * | 1989-08-02 | 1993-01-26 | Kabushiki Kaisha Toshiba | Compound semiconductor pellet, and method for dicing compound semiconductor wafer |
| JPH06169014A (en) * | 1992-03-12 | 1994-06-14 | Toshiba Corp | Compound semiconductor device and manufacturing method thereof |
| EP1278235A1 (en) * | 2001-07-09 | 2003-01-22 | Sanyo Electric Co., Ltd. | Manufacturing method of compound semiconductor device |
| EP1278236A1 (en) * | 2001-07-09 | 2003-01-22 | Sanyo Electric Co., Ltd. | Method of dicing a compound semiconductor wafer and compound semiconductor substrate thereby formed |
| US8288842B2 (en) * | 2003-12-01 | 2012-10-16 | Taiwan Semiconductor Manufacturing Co. Ltd | Method for dicing semiconductor wafers |
-
1990
- 1990-01-23 JP JP2014124A patent/JPH03218050A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5182233A (en) * | 1989-08-02 | 1993-01-26 | Kabushiki Kaisha Toshiba | Compound semiconductor pellet, and method for dicing compound semiconductor wafer |
| JPH06169014A (en) * | 1992-03-12 | 1994-06-14 | Toshiba Corp | Compound semiconductor device and manufacturing method thereof |
| EP1278235A1 (en) * | 2001-07-09 | 2003-01-22 | Sanyo Electric Co., Ltd. | Manufacturing method of compound semiconductor device |
| EP1278236A1 (en) * | 2001-07-09 | 2003-01-22 | Sanyo Electric Co., Ltd. | Method of dicing a compound semiconductor wafer and compound semiconductor substrate thereby formed |
| US6897126B2 (en) | 2001-07-09 | 2005-05-24 | Sanyo Electric, Co., Ltd. | Semiconductor device manufacturing method using mask slanting from orientation flat |
| CN100466170C (en) * | 2001-07-09 | 2009-03-04 | 三洋电机株式会社 | Mask and method of manufacturing compound semiconductor device using same |
| US8288842B2 (en) * | 2003-12-01 | 2012-10-16 | Taiwan Semiconductor Manufacturing Co. Ltd | Method for dicing semiconductor wafers |
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