JPH03218255A - Chopper drive circuit for switching power supply - Google Patents

Abstract

PURPOSE:To reduce leak current to the drive circuit side, caused by response lag from ON to OFF of an FET for conducting/interrupting main current, by connecting a common mode choke to a circuit which is connected with the gate and source of the FET in a chopper circuit. CONSTITUTION:During response lag interval of an FET Q1 from ON to OFF (where, Q5 is turned ON and Q1 is not yet turned OFF), a large leak current flows the path of the source of Q1-Lb-D3-Q5 and a leak current also flows through a path of the gate of Q1-La-Q3-D3-Q5. Since the leak current does not reciprocate through a common mode choke CMC, the CMC exhibits a high inductance against the leak current thus reducing the leak current.

Description

DETAILED DESCRIPTION OF THE INVENTION <<Industry> 2. Field of Application> The present invention relates to a chopper control type switching power supply device, and particularly relates to an improvement of a chopper drive circuit that drives a step-down type chopper circuit or a polarity inversion type chopper circuit.

《Prior art》 In step-down chopper circuits and polarity inversion chopper circuits, FETs (field-effect type 1 transistors) are used to interrupt the main current.
This results in a circuit configuration in which the source is floating in potential from the ground line. A typical non-insulated chopper drive circuit for driving this FET on and off using a pulse signal with the ground line as a potential reference has a bootstrap circuit configuration as shown in FIG.

In FIG. 2, FET QI, inductor L1, capacitor C, and diode D1 constitute a well-known step-down chopper circuit. During the ON period of FETQ1, current flows from the input Vin through FETQI, inductor L1, to capacitor C1 and the negative output (connected to output Vout), and when FETQ1 is off, current flows through diode D to inductor L1 and the load circuit. .

A stable output voltage can be obtained by driving the FET Q1 on and off at a sufficiently high frequency and appropriately controlling the duty ratio of the driving pulse.

FET QI of this step-down chopper circuit is turned on and off by the following circuit.

The pulse generation circuit PG is the I of the pulse width control circuit (PWM).
C, and generates a pulse signal using the ground line GND as a voltage reference. This pulse signal is a control signal for FETQI. The pulse generation circuit PG and the circuit that receives its output signal and drives the FETQI are operated by a DC power supply VcC different from the input Vin.

This chopper drive circuit has a first transistor Q2 that injects current into a resistor R1 connecting the gate and source of FETQI to turn on FETQ1, and a first transistor Q2 that almost shorts the gate and source of FETQI to turn FETQ1 from on to off at high speed. and a second transistor Q3 for inverting the output voltage.

The first and second transistors are connected in a complementary manner as shown in the figure, and a control circuit consisting of transistor Q4, FET Q5, resistors R2 and R3, diodes D2, D3, and D4, and capacitor C2 generates pulses. They are turned on and off in a complementary manner in response to a pulse signal output from the circuit PG.

When the FET Q5 is turned on by the output of the pulse generating circuit PG, a current flows from the power supply Vcc in the order of D2-C2→D3→Q5, and the capacitor C2 is charged to a voltage of about 2CC. At the same time, a current flows from D2-R2 to Q5, and the base of transistor Q4 is almost at ground level, transistor Q4 is turned off, and transistor Q2 is also turned off.

At this time, the gate-source voltage v6 of FETQI (voltage across resistor R1) is approximately zero, and FETQ1 is off.

FETQ5 is activated by the output signal from the pulse generation circuit PG.
When is reversed from on to off, the capacitor C2 operates as follows using the charge charged in the capacitor C2 as a power source. The base current of transistor Q4 flows from capacitor C2 through resistor R2, turning Q4 on.

Then, the base potential of transistors Q2 and Q3 rises,
The base current of transistor Q2 flows from the emitter side of transistor Q4, and transistor Q2 is also turned on.

Then, the discharge current of capacitor C2 flows through the loop of collector of Q2→emitter→R1→C2, a voltage is generated across resistor R1, and this voltage is applied between the gate and source of FETQI, turning on FETQI.

Next, the output from the pulse generation circuit PG causes the FETQ5 to
When FETQ5 is reversed from off to on, resistor R2 to FETQ5
Since current flows through the transistor Q4, the transistor Q4 is cut off, and therefore the transistor Q2 is also cut off. This eliminates the current flowing from transistor Q2 to resistor R1, and FE
TQI turns off, but at this time transistor Q
The base potential of FET Q3 decreases and turns on Q3, speeding up the change from on to off of FET Q1. Very FETQI
The gate-source capacitance CCS is charged during the ON period of FETQI, and unless the accumulated charge is quickly discharged, FETQI cannot be quickly turned from ON to OFF. Therefore, the transistor Q3 is turned on at the same time as the transistor Q2 is turned off, the gate and source of the FET Q1 are almost short-circuited by the transistor Q3, and the accumulated charge in the gate-source capacitance CCS is quickly discharged through Q3.

The above operation is repeated in response to a pulse signal from the pulse generation circuit PG to turn on and off the FET Q1 of the chopper circuit.

<<Problems to be Solved by the Invention>> In the conventional circuit shown in FIG. 2, when FETQ5 changes from OFF to ON due to the output of the pulse generation circuit PG, FETQI of the Chotsuba circuit changes from ON to OFF in response to the change. Yes, FET by transistor Q3
Even though it speeds up the change of QI to OFF, F
There remains a small amount of time when ETQ5 is turned on and FETQ1 is not yet turned off. In that minute time, the high voltage input V
Current flows from the in side through the emitter of Q1 → D3 → Q5. At the same time, the Q
Current also flows through the path from the gate of No. 1 to Q3-D3-Q5. These currents are referred to as leakage currents in this specification (the main current of the chopper circuit leaks to the drive circuit side).

The aforementioned leakage current is a pulse current with a minute width that flows every time the FET QI is reversed from on to off, but its peak value is relatively large. Since this leakage current flows to FET Q5, heat generation in Q5 becomes large, so a FET with a large current capacity must be used as Q5, and heat dissipation measures are also required in mounting. Further, the leakage current flowing through FETQ5 results in power loss in the chopper circuit.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to
The purpose of the present invention is to reduce leakage current to the drive circuit side due to a delay in response from ON to OFF of the ET.

<<Means for Solving the Problems>> Therefore, in the present invention, a first transistor is provided to turn on the FET (Ql) by flowing current into a resistor (R1) connecting the gate and source of the FET (Q1) of the chopper circuit. (Q2) and a second transistor (Q) for rapidly inverting the FET (Ql) from on to off by substantially shorting the gate and source of the FET (Ql).
3) and a non-insulated control circuit that turns on and off the first and second transistors (Q2, Q3) in a complementary manner in response to a pulse signal with a ground line as a potential reference, The second transistor (Q
A common mode choke was inserted on the two lines connecting 3) and the gate and source of the FET (Ql).

<<Function>> When turning on the FET (Ql), the current flowing from the first transistor (Q2) to the resistor (R1) flows through the second transistor (Ql), which connects the gate and source of the FET (Ql).
The current flows back and forth through the book line. In addition, the FET (Q
) when the gate-source capacitance is discharged through the second transistor (Q3) is also a current flowing back and forth between the two lines. Therefore, the common mode choke exhibits little inductance for these currents.

On the other hand, the leakage current caused by the delay in the on-off response of the FET (Ql) flows in the same direction through the two lines, and the common mode choke exhibits a large inductance with respect to this current. Reduce leakage current.

<<Embodiment>> FIG. 1 shows an embodiment in which improvements according to the present invention are added to the circuit of FIG. 2 described in detail above. The difference from the circuit of FIG. 2 is that a common mode choke CMC is added. A common mode choke CMC coil La is placed on the line connecting the gate of FETQI and the emitter of transistor 3.
is inserted, and a common mode choke CMC coil Lb is inserted on the line connecting the source of FET QI and the collector of transistor Q3.

The basic operation of this chopper drive circuit will be explained in the previous section. I have already explained this in detail, so I will omit the explanation here.

When FET Q5 is off, the discharge current of capacitor C2 is C 2 −” Q 2 + L a →R 1 →L
b 4 C 2 and the voltage generated across R1 turns on FETQ. At this time, current flows in opposite directions back and forth between La and Lb, and the common mode choke CMC exhibits almost no inductance.

When FETQ5 is reversed from off to on, transistor Q2 turns off, transistor Q3 turns on, and FETQ
A discharge current having a gate-source capacitance ffi C c s of 1 flows from the gate of 1 → La → Q3 → Lb → the source of Q1. This current also becomes a reciprocating current with respect to the common mode choke CMC, and the CMC exhibits almost no inductance.

However, during the on-→off response delay period of FETQI (the period when Q5 is on and Q1 is not yet off), a large leakage current flows in the path from the source of Q1 → Lb-D3 → Q5, and the gate of Q1・-I- L a -1-
Leakage current also flows in the path from Q 3 -* D 3 to Q5. Since this leakage current does not become a round trip current with respect to the common mode choke C0MC, CMC exhibits a large inductance with respect to this current, and these leakage currents are reduced.

<<Effects of the Invention>> As explained in detail above, in this invention, the simple improvement of connecting a common mode choke to the circuit connected to the gate and source of the FET of the chopper circuit achieves the following effects.
It is possible to effectively reduce the leakage current caused by the delay in response from ON to OFF of the FET, without affecting the circuit function that drives the FET on and off, suppressing power loss, and The current capacity of the transistor through which the leakage current flows can be small, and its heat generation becomes less of a problem.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a chopper drive circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional chopper drive circuit. 11 Q1...FETQ2... which intermittents the main current
...First transistor Q3...Second transistor CMC...Common mode choke

Claims (1)

[Claims] A circuit for driving a chopper circuit having a circuit configuration in which the source of an FET that intermittents the main current is floating in potential from a ground line, and for turning on the FET by flowing current into a resistor connecting the gate and source of the FET. a first transistor, a second transistor for rapidly inverting the FET from on to off by substantially shorting the gate and source of the FET, and receiving a pulse signal with the ground line as a potential reference; a non-insulated control circuit that turns on and off the first and second transistors in a complementary manner; and a common mode inserted on two lines connecting the second transistor and the gate and source of the FET. A chopper drive circuit for a switching power supply equipped with a choke.