JPH03218515A - Maximum value/minimum value detector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a maximum value/minimum value detection device,
This device is particularly suitable for devices that detect the maximum or minimum value of a large amount of data at high speed, as well as the position (address) of the maximum or minimum value, particularly in microprocessors, signal processors, etc. Conventional technology In microprocessors and signal processors, this type of maximum value/minimum value detection device subtracts or compares two types of data, uses a sign flag set by the subtraction or comparison result, and uses software The sign flag was determined by the method, and the program was switched using a conditional branch instruction to select the larger or smaller of the two types of data, or its storage address. To detect the maximum value of 50 pieces of data using a conventional general-purpose microprocessor, which used to detect two or more types of maximum value or minimum value or their storage address by repeating the process once or multiple times. An example of a program (hereinafter referred to as "conventional program IJ") is shown below.

AY=1 X=Y(AY) AY=2 100. Z=X-Y(AY) IFZ≧O Go To 200
・Maximum value data register Y (AY)... Data register Z... Arithmetic result (sign flag) To explain this program, 50 pieces of data whose maximum value is to be detected (Even if they are stored in memory (sometimes in registers) at consecutive addresses)
In the first line, the start address of 50 pieces of data is specified.In the second line, the data at address 1 of maximum value data register XL is stored as a temporary maximum value.In the third line, 50
Even if the address of the 2nd address of the data of In the fifth line, the sign of Z is determined, but if the value is negative, then the program in the sixth line is executed and the data Y (AY) is obtained.
If is larger than X, the content of Even if the value is incremented by 1
In the 8th line, the value of data address AY is determined and the value AY
If it is less than 50, the program branches to the 4th line, and if it exceeds 50, the program ends. Lines 4 to 8 of the program are executed 49 times. The maximum value of the 50 pieces of data. is finally set in the maximum value data register Let's say ZkuO ~ Conventional Example of a program for detecting the maximum value data and the address of the maximum value data among 50 pieces of data using a general-purpose microprocessor (hereinafter referred to as "Conventional Program 2") shows.

100 200 However, AY ■
AY) V=AY AY= AY+1 IF AY≦50 GO To 100...
...Data address...Maximum value data address...Maximum value data register...Data register register Z...Arithmetic result (sign flag) This program To explain this, even if the 50 data files whose maximum values are to be detected are stored in memory (sometimes in registers) at consecutive addresses, in the first line, 5
Even if the start address of 0 data is specified, in the second line,
Even if the data at address 1 is stored as a temporary maximum value in the maximum value data register Then, even if the address of address 2 of 50 pieces of data is specified, in the 5th line, the data at addresses 1 and 2 are subtracted by X-Y (AY), and the calculation result Z (Z is set by the calculation result. In the 6th line, even if the sign of Z is determined, even if the value is negative, C'1 The program in the 7th line is executed. data register
&'-Even if the current addressed data Y (AY) is stored, the current data address AY is stored in the maximum value data address register V in the 8th line.In other words, the 7th and 8th lines are It is executed when the sign of Z in the 6th line is negative, and in the 7th line, if the data Y (AY) is greater than X, the contents of X are rewritten to Y (AY).The contents of V in the 8th line is rewritten to AY, and if the sign value of aZ is positive or 0, then the program on line 9 is executed.
) is incremented by 1, the value of data address AY is determined in the 10th line, and if the value is less than 50, the process branches to the 5th line.
The fifth part of the program ends when the number exceeds 50.
The process from line to line 10 is repeated 49 times, and finally the maximum value of the 50 data is set in the maximum value data register X, and even though the maximum value address is set in the maximum value data address register V, the minimum value In the case of detection, the order of the calculations in the 5th line is reversed so that Y (AY) - Problem With such a processing configuration, it takes a considerable amount of time to determine the result of subtracting two data and to switch the program based on the result. Especially in actual general-purpose microprocessors, it takes a long time to determine the result of subtraction between two pieces of data and to switch the program based on the result. Conditional branch processing) cannot be processed in one machine cycle per step, increasing the number of program steps and lengthening the processing time.The present invention solves these problems and enables high-speed processing with simple means. Means for Solving the Problem The maximum value/minimum value detecting device of the first invention comprises: a means for subtracting or comparing two types of data; and a means for subtracting or comparing two types of data. a code flag setting means for setting a code flag according to a subtraction result or a comparison result; a data storage means for storing two types of data; and a designation means for simultaneously specifying two types of data to be stored in the data storage means. , when two types of data are specified simultaneously by this specifying means, depending on the state of the sign flag set by the sign flag setting means,
The maximum value/minimum value detection device line of the second invention, further comprising a selection means for selecting either the larger data or the smaller data of the two types of data; means for comparing; code flag setting means for setting a code flag according to the subtraction result or comparison result by the means; data storage means for storing two types of data; and storing addresses of the two types of data in the data storage means. an address storage means, a specification means for simultaneously specifying two types of data to be stored in the data storage means, and a sign flag set by the sign flag setting means when two types of data are simultaneously specified by the specification means. data selection means for selecting the larger or smaller of the two types of data depending on the state of the data, and the address or address of the larger of the two types of data depending on the state of the sign flag. Even though it is equipped with an address selection means for selecting the address of the smaller data, and a means for storing the address selected by the address selection means in the address storage means, this structure allows two or more kinds of data to be selected in a simple manner. A maximum value/minimum value checking device capable of detecting the maximum value or minimum value of two or more types of data at high speed, and the maximum value or minimum value of two or more types of data, or the address or minimum value of the maximum value data. Embodiment First, an embodiment of the maximum value/minimum value detection device of the first invention will be described using FIG. 1. In the diagram, 10
1 is data RAκ l02, 103 is data bar input 10
4 is the ALU, 105 is the sign flag register, 106 is the selection time 1! &107, 108 are data registers. The ALU 104 compares or increments the data of the data paths 102, 103. The sign of the comparison result or subtraction result by the ALU 104 is set in the sign flag register 105. Selection circuit 10i: Depending on the contents of the L code flag register 105, either the data register 107 or 108 is selected and data is output to the data path 103.
The data output to the data bus 103 is set in the data register 108. 5 When comparing or subtracting in ALU 104, data RAM is connected to data bus 102.
Even if the data of I O 1 is output and the data of the data register 108 is output to the data bus 103, and at the same time the data' register 107 receives the data of the data bus 102, the sign flag register 105 of the comparison or subtraction result of the ALU 104 on the selection circuit 1064 Depending on the content of
Selects the larger data of the contents of the data register 107 (data in RAM 101) or the contents of the data register 108 (maximum value at that time), and outputs the data to the data bus 103. The data is set in the maximum value data register 108. By this method, the data in the data register 108 is set in the data RAM 1.
If the data is larger than 0 1, data register 1
Even if the previous data is retained as it is in 08, the data RA
If the data in M101 is larger than the data in the data register 108, the contents of the data register 108 may be rewritten with the data in the data register 107.
Therefore, the content of the data register 108 is changed to the larger of the previous data in the data register 108 and the data in the data RAMIOI.
By repeating the above process while updating the address of 1 0 1, data RA is stored in the data register 108.
When the maximum value of the two or more types of data stored in the MIOI is stored, In figure a to explain, 10
1 is data RAM. 102 and 103 are Databa people 1
04 is ALU, 105 is code flag register, 106
is selection time 1 & 107, 108 is data register, 20
9 is an address pointer, 210 is an address register,
211 is an address selection circuit. ALU 1.04 compares or subtracts the data on the data bus 102 and 103. The sign of the comparison result or subtraction result by the ALU 104 is stored in the sign flag register 10.
Even if set to 5, the selection circuit 106 selects either data register 107 or 108 according to the contents of the code flag register 105 and outputs data to the data bus 103.aThe data output to the data bus 103 is data. When the data RAMIOI is set in the register 108 and compared or subtracted in the ALU 104, the data of the data RAMIOI is output to the data bus 102.
At the same time, the data register 107 receives the data from the data path 102.The selection circuit 106 outputs the data from the data register 108 to ALUI 04.
The sign flag of the comparison result or the subtraction result depending on the contents of the sign flag register, the contents of the data register 107 (data in RAM 101) or the data register 108
Selects the larger data among the contents (maximum value at that time) and outputs the data to the data path 103. Even if the output data is set in the maximum value data register 108, this process The data set in the data register 108 is compared with the data in the data RAMIOI, and if the data value in the data register 108 is large, the data in the data register 108 remains the previous data, and the data in the data RAMIOI is large. The data in the data register 108 is rewritten to the data in the data register 107. Therefore, the contents of the data register 108 are the same as those in the previous data register 108.
A address selection circuit 2114; LA
Depending on the contents of the sign flag register lO5 of the comparison result or subtraction result of LUl04, the contents of the address pointer 209 (the address of RAM 1 0 1 at that time) or the contents of the address register 210 (the address of the maximum value data at that time) Select one of the address data and output the address data to the address register 210.The output address data is stored in the address register l0.
Even if it is set to 8, this process will cause the data register 210 to
The data set in the address register 210 is compared with the data in the data RAM 101, and if the data value in the data register 108 is large, the data in the address register 210 remains the previous data.
If the data in 01 is large, the top address register 2
10 is rewritten to the address of the address pointer 209. Therefore, the contents of the address register 210 are changed to the larger address data of the data of the data register 108 and the data of the data RAM 101. By repeating the above process while updating the 1 0 1 address, the data register 108 stores the maximum value of two or more types of data stored in the data RAMIOI, and the address register 210 data R
In the microprocessor of the embodiment of the first invention described above, the address of the maximum value data of two or more types of data stored in the AMIOI is stored as follows. An example of a program (hereinafter referred to as the present embodiment program IJ) for detecting is shown below.

100 However, AY X Y (AY) Z W AY= 1
... Data address ... Maximum value data register ... Data register ... Operation result ... Data register (Explaining the X or Riko program, the maximum value Even if the data to be detected is stored in memory (or registers) at consecutive addresses, even if the first address of 50 pieces of data is specified in the first line, 1 is stored in the maximum value data register X in the second line. Although the address data is stored as a temporary maximum value, in the third line, the address of the second address of 50 data is specified, but in the fourth line, the data at addresses 1 and 2 are decremented.
-Y (AY) is performed and the operation result Z (Z may be a sign flag set by the operation result) is obtained.In the fifth line, depending on the state of the operation result Z, the maximum value data register Even if the data of Y (AY) is written to the maximum value data register, if the calculation result Z is positive or O, then the value of the maximum value data register X is written to the maximum value data register X again, and if it is negative, then Number yo The value of data register Y (AY) is written to maximum value data register , to be performed automatically by hardware. In the 6th line, the value of data address AI indicating data register Y (AY) is 1.
In the 7th line, the data address AY is incremented.
If the value of tL, AY is less than 50, the program branches to the 4th line, and if it exceeds 50, the program ends.The program's 4th to 7th lines are executed 49 times. st'lA The maximum value among the 50 pieces of data is finally set in the data register )
-X is an example of a program (
Hereinafter referred to as "Example Program 2") iAY=1 X=Y(AY) V=1 100 However, AY ■ AY=2 (4)Z
Engineering X7Y (AY) (5)X=%
j (6) V=AW
(7)AY=AY+1
(8) IF AY≦50
Go TO 100 (9)...
...Data address... Maximum value data address register Maximum value data register Data register Operation result data register (X or address register (V or AY)) To explain this program, the data that detects the maximum value is continuous. In the first line, the first address of the 50 pieces of data is specified, and in the second line, the data at address 1 is temporarily stored in the maximum value data register X. In the third line, the address of address 1 is stored as the temporary maximum data address in the maximum value data address register V. In the fourth line, the address of address 2 of 50 pieces of data is specified. Also, in the 5th line, the calculation result Z (Z
may also be a sign flag set by the calculation result)
In the sixth line, depending on the state of the operation result Z, the maximum value data register X or data register Y (AY) is obtained.
Even if data is written to the maximum value data register, if the operation result Z is positive or O, the value of the maximum value data register X is written to the maximum value data register The value of (AY) is written to the maximum value data register In the seventh line, the calculation result Z
Depending on the state of the maximum value data address register V or data address AY (even if written to the maximum value data address register ■), if the operation result Z is positive or 0, the maximum value data address register V
The value of data address AY is again written to the maximum value data address register V, and if it is negative, the value of data address AY is written to the maximum value data address register V.
Maximum value depending on the state of operation result Z when W is specified Data address register ■ or data address AY selection top Even if it is automatically performed by hardware, the data address indicating data register Y (AY) on the 8th line AY
Even if the value of AY is incremented by 1, the value of data address AY is determined in the 9th line. If the value of AY is less than 50, the program branches to the 5th line, and if it exceeds 50, the program ends. The steps from the 5th line to the 9th line are executed 49 times, and the maximum value of the 50 pieces of data is finally set in the maximum value data register X, and the address of the maximum value data is finally set in the maximum value data address register V. In the case of detecting the minimum value, the order of the calculations in the 5th line is reversed and it becomes Y (AY) - What is the judgment of the calculation result Z on the 5th line and the conditional branch processing? Also, in this example program 2, 4
1 Compared with the conventional program 2, the determination of the calculation result Z in the 6th line and the conditional branch processing in the conventional program 2 are different. 2 reduces the number of program steps and enables high-speed processing.
In particular, in actual general-purpose processors, pipeline processing is performed, and it takes time to perform judgments and conditional branch processing based on judgment results.Reducing the steps of judgment and conditional branch processing based on judgment results is an effective way to increase processing speed. According to the present invention, the maximum value or minimum value of two or more types of data and the maximum value or minimum value of two or more types of data can be determined with a simple configuration. The address of value data or the address of minimum value data can be detected at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the maximum value/minimum value detection device of the first invention. FIG. 2 is a block diagram of an embodiment of the maximum value/minimum value detection device of the second invention. ...Data RAM, 102, 1
03... Data bar 7,, 104...
・ALU% 105... Sign flag register,
106... Selected episode 107,108...
...Data register, 209...Address pointer, 210...Address register,
211...Address selection process

Claims (2)

[Claims] (1) means for subtracting or comparing two types of data;
code flag setting means for setting a code flag based on the subtraction result or comparison result by the means; data storage means for storing the two types of data; and simultaneous designation of the two types of data to be stored in the data storage means. and when the two types of data are simultaneously specified by the specifying means, the larger or smaller data of the two types of data is determined depending on the state of the code flag set by the code flag setting means. 1. A maximum value/minimum value detection device, comprising: selection means for selecting one of the two types of data. (2) means for subtracting or comparing two types of data;
code flag setting means for setting a code flag according to the subtraction result or comparison result by the means; data storage means for storing the two types of data; and address storage for storing addresses of the two types of data in the data storage means. and the second data stored in the data storage means.
a designating means for simultaneously designating two types of data, and when the two types of data are simultaneously designated by the designation means, the data of the two types of data is determined by the state of the code flag set by the code flag setting means; data selection means for selecting the larger data or the smaller data of the two types of data; and selecting the address of the larger data or the address of the smaller data of the two types of data depending on the state of the code flag. A maximum value/minimum value detection device comprising: address selection means; and means for storing the address selected by the address selection means in the address storage means.