JPH03218547A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor memory device.

BACKGROUND OF THE INVENTION Microprocessors, which have become increasingly sophisticated and highly integrated in recent years, tend to adopt a virtual memory system and also incorporate an address translation device and some memory, such as cache memory that is accessed using physical addresses. It is in. As an example, to describe the main operations when an address translation device and a cache memory are built in, first a logical address is given to the address translation device, the address translation device outputs the corresponding physical address, and on the other hand, the address translation device outputs the corresponding physical address. The tag memory in memory also outputs the physical address. Two physical addresses output from the address translation device and the cache memory are transferred to a comparator and compared. As described above, in conventional semiconductor memory devices, it is generally necessary to transfer data output from an address translation device and some memories to other identical functional blocks. As the operating frequency of microprocessors increases, it has become increasingly necessary to speed up such processing, and conventionally, processing speeds have been achieved by increasing the speed of each functional block itself, such as the address translation device and memory. The method was used.

Problems to be Solved by the Invention However, in the conventional example described above, the address translation device and other memories are regarded as independent functional blocks, and the actual configuration and arrangement are also separated, and the data output from them is need to be transferred to the same functional block located far away. Therefore, even if the transfer destination functional block is located near either the address translation device that outputs data or the tag memory, the transfer must be performed at least for the distance between the address translation device and the tag memory. First, the transfer time was a factor that hindered speeding up of processing.

In view of the problems of the prior art as described above, the present invention reduces the transfer time by shortening the transfer distance when transferring data output from an address translation device and several memories to other same functional blocks. It is an object of the present invention to provide a semiconductor memory device that is shortened in size.

Means for Solving the Problems In order to achieve the above object, a semiconductor memory device according to the present invention provides a semiconductor memory device in which one entry of an address translation device includes a content addressable memory cell array, a first random access memory cell array, and a second random access memory cell array. a memory cell array; a first decoding means for generating a word signal for the content addressable memory cell array; a control means for generating a word signal for the first random access memory cell array using the word signal for the content addressable memory cell array and a comparison result; a second random access memory cell array generating a word signal for the second random access memory cell array;
decoding means.

The present invention also provides that the second random access memory cell array is a cache tag memory cell array;
At least two random access memory cell arrays of the random access memory cell array group included in the entry are arranged in parallel in a direction perpendicular to the bit line.

The present invention also provides that one entry of the first address translation device is a word of the first associative memory cell array, the first random access memory cell array, the second random access memory cell array, and the first associative memory cell array. a first decoding means that generates a signal;
a first control means for generating a word signal for a random access memory cell array, and one entry of the second address translation device includes a second associative memory cell array, a third random access memory cell array, a fourth random access memory cell array, a second decoding means for generating a word signal of the second content addressable memory cell array, and a third random access memory cell array using the word signal of the second content addressable memory cell array and the comparison result. a second control means for generating a word signal for the second and fourth random access memory cell arrays, and one entry of the first and second address translation devices generates a word signal for the second and fourth random access memory cell arrays. The bit lines are arranged left and right in parallel with the decoding means at the center.

The present invention also provides that one entry of the first address translation device includes a first associative memory cell array, a first random access memory cell array, a second random access memory cell array, and a second random access memory cell array. The first decoding means generates a word signal, and the first control means generates a word signal of the first random access memory array using the word signal of the first content addressable memory cell array and the comparison result, One entry of the second address translation device includes a second associative memory cell array, a third random access memory cell array, a fourth random access memory cell array, and a fourth random access memory cell array.
a second decoding means for generating a word signal for the random access memory cell array; and a second control for generating a word signal for the third random access memory array using the word signal for the second associative memory cell array and the comparison result. one entry of these first and second address translation devices has bit lines parallel to each other around a third decoding means that generates word signals for the first and second content addressable memory cell arrays. They are arranged on the left and right.

The present invention also provides that the second and fourth random access memory cell arrays are cache tag memories, and further that the two random access memory cell arrays included in one entry of each address translation device are arranged in parallel in a direction perpendicular to the bit line. It has an arranged configuration.

Effect The present invention having the above-mentioned configuration has several memories arranged without being separated in the same entry of the address translation device outputting data from adjacent locations, so that the communication between the address translation device and the memory is improved. This has the effect of shortening the data transfer distance between the two, thereby shortening the transfer time. In addition, since associative memory cells are generally larger than random access memory cells, the problem of unnecessary space being created on the random access memory cell array side when arranged in an array can be solved by, for example, the length of the associative memory cells in the bit line direction. In the case of approximately twice the size, there is an effect that unnecessary space can be saved by arranging two random access memory cell arrays in parallel in a direction perpendicular to the bit line.

Example (Example 1) FIG. 1 shows a block configuration of a first embodiment of the present invention.

In FIG. 1, l is an associative memory cell array, 2 and 3 are random access memory cell arrays, 4 and 6 are decoders, 5 is a control means, 7, 9, and 10 are word signals, 8 is a coincidence detection line, 11, 12, 13, 14, 15, and 16 are bit lines, and 17 and 18 are address signals.

Next, the operation of the first embodiment will be explained. First, in a write operation, the decoder 4 uses the address signal 17 to generate the word signal 7 for the content addressable memory cell array 1, the bit line 11 is given a normal inversion signal of the logical address, and the bit line 12 is given the inversion signal of the logical address. A signal is applied, whereby an m-bit logical address is written into the content addressable memory cell array 1. Using the word signal 7, the control means 5 then generates a word signal 9 for the first random access memory cell array 2. That is, in FIG. 7,
First, control signal 22 is set high to turn off P-channel transistor 23, and control signal 24 is set high. Next, when word line 7 is selected, word line 9 is selected via OR circuit 25 and AND circuit 26. A normal inversion signal of the physical address is applied to the bit line 13 , and an inversion signal of the physical address is applied to the bit line 14 , whereby an m-bit physical address is written into the first random access memory cell array 2 . On the other hand, the decoder 6 uses the address signal 18 to generate a word signal 10 for the second random access memory cell array 3 provided in the same entry of the address translation device, and the bit line 15 receives a normal data signal. given, bit line 1
A data inversion signal is applied to 6, whereby m-bit data is written into the second random access memory cell array 3.

Next, in a read operation, a normal inversion signal and an inversion signal of an m-bit logical address are applied to the bit lines 11 and 12 of the associative memory cell array 1 of the address conversion device, respectively, and the associative memory cell array 1 stores the given logical address. The comparison result is output to the match detection line 8. Then, using the coincidence detection line 8, the control stage 5 connects the first random access memory cell array 2.
A word signal 9 is generated. That is, first, control signal 2
4 to low and control compensation code 22 to low, P
The channel transistor 23 is turned on and the match detection line 8 is precharged. Control signal 22 is then set high to turn off P-channel transistor 23 and turn on control signal 24. Thereafter, the comparison result appears on the coincidence detection line 8, is detected by the sense amplifier 27, and the word line 9 is selected via the OR circuit 25 and the AND circuit 26. As a result, the m-bit physical address is transferred from the first random access memory cell array 2 to the bit lines 13, 1.
4 and output. On the other hand, the decoder 6 uses the address signal 18 to generate a word signal 1o for the second random access memory cell array 3 provided in the same entry of the address translation device, thereby causing the second random access memory cell array 3 to m bits of data are read out to bit lines 15 and 16 and output. At this time, since the first random access memory cell array 2 and the second random access memory cell array 3 are arranged in the same entry, data will be output from adjacent locations.

In this way, in the semiconductor memory device of this embodiment, a plurality of random access memory cell arrays 2 and 3 are arranged in the same entry of the address translation device, and the distance between the outputs of data read from them is shortened. , the data transfer distance and transfer time can be shortened.

(Example 2) FIG. 2 shows a block configuration of a second embodiment of the present invention.

Here, the same elements as in the first embodiment shown in FIG. 1 are given the same reference numerals. In FIG. 2, 1 is a virtual memory cell array, 2 is a random access memory cell array,
4, 6 are decoders, 5 is a control means, 7, 9, 10 are word signals, 8 is a coincidence detection line, 11, 12, 13, 14, 1
5, 16 are bit lines, 17, 18 are address signals, 19
2 is a comparator, 20 is a comparison result output, and 21 is a tag memory cell array.

This embodiment differs from the first embodiment in that it has a plurality of entries, which are connected to common bit lines 11 to 16 and address signals 17 and 18, and further includes an m-bit comparator 19. The point is that The configuration of each entry is the same as in the first embodiment, but in this embodiment, the second random access memory cell array 3 disposed in the entry of the address translation device has a tag memory of the cache memory accessed by the physical address. A cell array 21 is used.

Next, the operation of this embodiment will be explained. First, in a write operation, the decoder 4 generates a word signal 7 for the associative memory cell array 1 using address decoding l7, and the bit line 1
1 is given a normal rotation signal of a logical address, and bit line 1
2 is supplied with an inverted signal of a logical address, thereby writing an m-bit logical address into the content addressable memory cell array l. Next, using the word signal 7, the control means 5 generates the word signal 9 for the random access memory cell array 2, the bit line 13 is given a normal inversion signal of the physical address, and the bit line 14 is given an inversion signal of the physical address. is given, thereby writing an m-bit physical address into the random access memory cell array 2. On the other hand, the decoder 6 uses the address signal 18 to generate a word signal 10 for the tag memory cell array 21 provided in the same entry of the address conversion device, and
is given a normal rotation signal of the physical address, and the bit line 16
An inverted signal of the physical address is applied to , whereby an m-bit physical address is written into the tag memory cell array 21 .

Next, in a read operation, a normal inversion signal and an inversion signal of an m-bit logical address are applied to the bit lines 11 and 12 of the associative memory cell array 1 of the address conversion device, respectively, and the associative memory cell array 1 stores the given logical address. The comparison result is output to the match detection line 8. Then, using the coincidence detection line 8, the control means 5 generates a word signal 9 for the random access memory cell array 2, whereby an m-bit physical address is read out from the random access memory cell array 2 onto the bit lines 13, 14 and output. be done. On the other hand, the decoder 6 uses the address signal 18 to generate a word signal 10 for the tag memory cell array 21 provided in the same entry of the address conversion device, whereby the m-bit physical address is transferred from the tag memory cell array 21 to the bit line 15. ,
16 and output. The physical addresses read from the random access memory cell array 2 and the tag memory cell array 21 are respectively input to the comparator 19 , the two physical addresses are compared, and the comparison result is obtained at the output 20 .

As described above, in this embodiment, when data is transferred to the comparator 19, which is the same functional block, since the data is output from a nearby location, the destination functional block is set to the semiconductor memory device of this embodiment. If they are placed close together, the data transfer distance can be extremely shortened, and the transfer time can be shortened.

Although this second embodiment deals with the case where the number of entries in the address translation device and the number of entries in the tag memory cell array 21 arranged in the address translation device are the same, even if the numbers of entries are different between the two, the partial Generally speaking, the configuration of the second embodiment can be applied.

In addition, since associative memory cells are generally larger than random access memory cells, that is, the number of transistors in associative memory cells is greater than the number of transistors in random access memory cells, so when they are arranged in an array, unnecessary Regarding the problem of space, for example, as shown in the above embodiment, if the length of the associative memory cell in the bit line direction is approximately twice the length of the random access memory cell array in the bit line direction, By arranging two random access memory cell arrays in parallel in a direction perpendicular to the bit line, it is possible to eliminate unnecessary space.

For reference, an example circuit diagram of the associative memory cell 1 is shown in FIG.
FIG. 9 shows an example of a circuit diagram of the random access memory cell 2. 8 and 9, 28 is N channel M
The OS transistor 29 is a P-channel MOS transistor. In this way, the content addressable memory cell 1 and the random access memory cell 2 differ in the number of transistors forming each cell.

(Example 3) FIG. 3 shows a block configuration of a third embodiment of the present invention.

Here again, the same elements as in the first embodiment shown in FIG. 1 are given the same reference numerals. In FIG. 3, 1 is an associative memory cell array, 2 and 3 are random access memory cell arrays, 4.6 is a decoder, 5 is a control means, 7, 9.1
0 is a word signal, 8 is a coincidence detection line, 11, 12, 13,
14, 15 and 16 are bit lines, and 17 and 18 are address signals.

This embodiment differs from the first embodiment in that the number of bits of the first random access memory cell array 2 and the number of bits of the second random access memory cell array 3 are different. The number of bits of the first random access memory cell array 2 is m bits, and the number of bits of the second random access memory cell array 3 is k bits, and (1>k).

Next, the operation of this embodiment will be explained. First, in a write operation, the decoder 4 uses the address signal 17 to generate a word signal 7 for the content addressable memory cell array 1, and the bit line 1
1 is given a normal rotation signal of a logical address, and bit line 1
2 is supplied with an inverted signal of the logical address, whereby an m-bit logical address is written into the content addressable memory cell array 1. Next, using the word signal 7, the control means 5 generates a word signal 9 for the first random access memory cell array 2, a normal inversion signal of the physical address is applied to the bit line 13, and a physical address signal is applied to the bit line 14. is applied, thereby writing an m-bit physical address into the first random access memory cell array 2. On the other hand, the decoder 6 uses the address signal 18 to generate a word signal 10 for the second random access memory cell array 3 provided in the same entry of the address translation device, and the bit line 15 receives a normal data signal. A data inversion signal is applied to the bit line 16, thereby writing k bits of data into the second random access memory cell array 3.

Next, in a read operation, a normal signal and an inverted signal of an m-bit logical address are applied to the bit lines 11 and 12 of the associative memory cell array 1 of the address translation device, respectively, and the virtual memory cell array l is connected to the applied logical address. It compares the stored logical address and outputs the comparison result to the match detection line 8. Then, using the coincidence detection line 8, the control means 5 controls the first random access memory cell array 2.
A word signal 9 is generated, whereby an m-bit physical address from the first random access memory cell array 2 is read out to the bit lines 13 and 14 and output. On the other hand, the decoder 6 uses the address signal 18 to generate a word signal 1o for the second random access memory cell array 3 provided in the same entry of the address translation device, thereby causing the second random access memory cell array 3 to K bits of data are read and output onto bit lines 15 and 16. At this time, since the first random access memory cell array 2 and the second random access memory cell array 3 are arranged in the same entry,
Data will be output from a nearby location.

In this way, in the semiconductor memory device of this embodiment, a plurality of random access memory cell arrays 2 and 3 are arranged in the same entry of the address translation device, and the distance between the outputs of data read from them is shortened. Therefore, the data transfer distance and transfer time can be shortened.

Note that the relationship between the number of bits m of the first random access memory cell array 2 and the number of bits k of the second random access memory cell array 3 was m>k in this embodiment, but
m<k may also be satisfied. Therefore, a general memory other than a cache tag memory can also be used for the second random access memory cell array 3. Further, when m=k, the result is the same as in the first embodiment.

(Example 4) FIG. 4 shows a block configuration of a fourth embodiment of the present invention.

Here again, the same elements as in the first embodiment are given the same reference numerals. In FIG. 4, 1 is an associative memory cell array, 2.3a. 3b is a random access memory cell array; 4.6a and 6b are decoders; 5 is a control means; 7.9
．． 10a, IQb are word signals, 8 is a coincidence detection line, 11
, 12.13.14.30.31.32.33 are bit lines, and 17, 18a, 18b are address signals.

This embodiment differs from the first embodiment in that it has a plurality of entries, and these are bit lines 11.12.13.14, 3.
0.31.32.33 and address signal 17.18a
, 18b are connected in common, and the configuration of each entry is the same as in the first embodiment, but in this embodiment, two types of second random access memory cell arrays are arranged in the entry of the address change device. random access memory cell arrays 3a and 3b are used, and 3a and 3b are used.
are arranged alternately for each entry of the address translation device.

Next, the operation of this embodiment will be explained. First, in a write operation, the decoder 4 uses the address signal 17 to generate a word signal 7 for the content addressable memory cell array 1, and the bit line 1
1 is given a normal rotation signal of a logical address, and bit line 1
2 is supplied with an inverted signal of the logical address, whereby an m-bit logical address is written into the content addressable memory cell array 1. Next, using the word signal 7, the control means 5 generates the word signal 9 for the random access memory cell array 2, the bit line 13 is given a normal inversion signal of the physical address, and the bit line 14 is given an inversion signal of the physical address. is given, thereby writing an m-bit physical address into the random access memory cell array 2. On the other hand, the decoder 6a uses the address signal 18a to generate a word signal 10a for the random access memory cell array 3a provided in the same entry of the address conversion device, and the bit line 3o is given a normal rotation signal of data.
A data inversion signal is applied to the bit line 31, thereby writing m bits of data into the random access memory cell array 3a. Further, the decoder 6b uses the address signal l8b to generate a word signal 10b for the random access memory cell array 3b provided in the same entry of the address conversion device, and a normal rotation signal of data is applied to the bit line 32. A data inversion signal is applied to the bit line 33, thereby writing m bits of data into the random access memory cell array 3b.

Next, in a read operation, the normal and inverted signals of the m-bit logical address are applied to the bit lines 11 and 12 of the virtual memory cell array 1 of the address conversion device, and the associative memory cell array l receives the given λ. The logical address is compared with the stored logical address, and the comparison result is sent to the match detection line 8. Using the match detection line 8, the controller 5 then generates a word signal 9 for the random access memory cell array 2, thereby reading the m-bit physical address from the random access memory cell array 2 onto the bit line 13.14. issued and output. On the other hand, decoder 6a
uses the address signal 18a to generate a word signal 10a for the random access memory cell array 3a provided in the same entry of the address conversion device, thereby transferring m-bit data from the random access memory cell array 3a to the bit lines 30, 31. is read out and output. Further, the decoder 6b uses the address signal l8b to generate a word signal 10b of the random access memory cell array 3b provided in the same entry of the address translation device.
As a result, m-bit data is read out from the random access memory cell array 3b to the bit lines 32 and 33 and output.

In this way, in this embodiment, a plurality of random access memory cell arrays are arranged within the same entry, and data is output from nearby locations, so it is possible to make the data transfer distance extremely short. Transfer time can be shortened. In particular, in this embodiment, two types of second random access memory cell arrays 3a and 3b are arranged alternately for each entry of the address translation device, and for example, one second random access memory cell array is used as a cache tag memory. , it is also possible to use the other second random access memory cell array as a cache data memory.

(Example 5) FIG. 5 shows a block configuration of a fifth embodiment of the present invention.

In this embodiment as well, the same elements as in the first embodiment are given the same reference numerals. In FIG. 5, ■ is an associative memory cell array, 2.3 is a random access memory cell array, 4.6 is a decoder, and 5 is a control means. ．． 9.1
0 is word line, 8 is match detection line, 11, 12.13, 1
4.15, 16, 34, 35.36.37.38.39
is a bit line, and 17.18 is an address signal.

Next, the operation of this embodiment will be explained. First, in a write operation, the decoder 4-1.4-2 uses the address signal 17-1.17-2 to write the addressable memory cell array 1-1.1.
-2 word signal 7-1.7-2 is generated and bit line 1
A normal inversion signal of the logical address is applied to bit lines 12 and 35, and an inversion signal of the logical address is applied to the bit lines 12 and 35, whereby the m-bit logical address is transferred to the content addressable memory cell array 1-1. A logical address is written to the content addressable memory cell array 1-2. Word signal 7-1
．． 7-2, the control means 5-1.5-2 generates word signals 9-1.9-2 for the random access memory cell array 2-1.2-2, and the bit lines 13.36 A normal rotation signal of the physical address is given, and the bit line 14.37
An inverted signal of the physical address is applied to the memory cell array 2, whereby an m-bit physical address is written to the random access memory cell array 2-1, and an n-bit physical address is written to the random access memory cell array 2-2.

On the other hand, the decoder 6 uses the address signal 18 to generate the word signal 1 of the random access memory cell arrays 3-1 and 3-2 provided in the same end area of the address translation device.
0-1.10-2, a normal data signal is given to the bit line 15.38, and an inverted data signal is given to the bit line 16.39, whereby m bits of data are randomly generated. In the access memory cell array 3-1, n
Bit data is randomly accessed in memory cell array 3
-2 is written.

Next, in a read operation, a normal signal and an inverted signal of an m-bit logical address are applied to the bit lines 11 and 12 of the associative memory cell array 1-1, respectively, and the bit lines 34 and 35 of the associative memory cell array 1-2 are respectively applied. Given a normal signal and an inverted signal of an n-bit logical address, the associative memory cell array 1-1.1-2 compares the given logical address with the stored logical address and detects a match based on the comparison result. Output to lines 8-1 and 8-2.

Control means 51.5- using coincidence detection line 8-1.8-2
2 is a random access memory cell array 2-1.2-
2 word signals 9-1.9-2 are generated, thereby reading the m-bit physical address from the random access memory cell array 2-1 onto the bit line 13.14, and the n-bit physical address from the random access memory cell array 2-2 is read out to the bit line 13.14. The physical address of the bit is read and output on bit lines 36,37.

On the other hand, the decoder 6 uses the address signal 18 to generate a word signal 10 of the random access memory cell array 3-1.3=2 provided in the same entry of the address translation device.
-1.10-2, thereby reading m bits of data from the random access memory cell array 3-1 to the bit lines 15, l6, and reading n bits of data from the random access memory cell array 3-2 to the bit lines. 38
．． 39 and output. At this time, random access memory cell arrays 2-1 and 3-1, 2-2 and 3-
2 are placed in the same entry, data will be output from nearby locations.

In this way, in the semiconductor memory device of this embodiment, a plurality of random access memory cell arrays are arranged within the same entry of the address conversion device, and the distance between the outputs of data read from them is shortened, so that the data transfer distance and transfer time are reduced. can be shortened. Another advantage is that it is possible to use a generally used random access memory in which a decoder is located in the center and memory cell arrays are arranged on both sides of the decoder.

Note that the operation timings of the first address translation device and the second address translation device may be the same or different. Furthermore, the number of bits of address and data is m>n. m=n. man
Any one is fine.

(Implementation fXA16) FIG. 6 shows a block configuration of a sixth embodiment of the present invention.

Elements similar to those in the fifth embodiment are given the same reference numerals. In FIG. 6, 1 is an associative memory cell array; 2 is a content addressable memory cell array;
．． 3 is a random access memory cell array, 4 and 6 are decoders, and 5 is a control means. ．． 9.10 is a word line, 8 is a coincidence detection line, 11.12, 13.14.15.16, 3
4.35, 36, 37, 38.39 are bit lines, 17,
18 is an address signal.

Next, the operation of this embodiment will be explained. First, in a write operation, the decoder 4 uses the address signal 17 to write the word signal 7-1.7 of the content addressable memory cell array 1-1.1-2.
-2 is generated, a normal inversion signal of the logical address is given to the bit line 11.34, and an inverted signal of the logical address is given to the bit line 12.35. 1-1, an n-bit logical address is written into the content addressable memory cell array 1-2. Using the word signal 7-1.7-2, the control means 5-1.5-2 generates a word signal 9-1.9-2 for the random access memory cell array 2-1.2-2;
A normal inversion signal of the physical address is applied to the bit line 13.36, and an inversion signal of the physical address is applied to the bit line 14.37, whereby an m-bit physical address is applied to the random access memory cell array 2-1. The n-bit physical address is random access memory cell array 2-
Written to 2.

On the other hand, the decoder 6-1.6-2 receives the address signal 18-1.
．． Random access memory cell array 3 provided within the same entry of the address translation device using 18-2
-1.3-2 word signal 10-1.10-2 is generated, a normal data signal is given to bit line 15.38, and an inverted data signal is given to bit line l6, 39. , thereby writing m-bit data to random access memory cell array 3-1 and writing n-bit data to random access memory cell array 3-2.

Next, in a read operation, a normal signal and an inverted signal of an m-bit logical address are applied to bit lines 11 and 12 of the content addressable memory cell array 1-1, respectively, and bit lines 34 and 35 of the content addressable memory cell array 1-2 are provided with a normal signal and an inversion signal of the m-bit logical address, respectively. Given a normal signal and an inverted signal of an n-bit logical address, the associative memory cell array 1-1.1-2 compares the given logical address with the stored logical address and detects a match based on the comparison result. Output to lines 8-1 and 8-2.

Seito Sendan 5-1.6 using match detection line 8-1.8-2
-2 is random access memory cell array 2-1.2
-2 word signal 9-1.9-2 is generated, whereby the m-bit physical address is read out from the random access memory cell array 2-1 onto the bit line 13.14;
An n-bit physical address is read out from the random access memory cell array 2-2 to the bit lines 36 and 37 and output.

On the other hand, decoders 6-1, 6-2 receive address signals 1g-1.
Random access memory cell array 3- provided within the same entry of the address translation device using 18-2.
1.3-2 word signal 10-1.10-2 is generated,
As a result, random access memory cell array 3-1
m bits of data from the random access memory cell array 3-2 are read out to the bit lines 38, 39, and n bits of data are read out from the random access memory cell array 3-2 to the bit lines 38, 39. At this time, random access memory cell array 2
Since -1 and 3-1 and 2-2 and 3-2 are placed in the same entry, data will be output from nearby locations.

In this way, in the semiconductor memory device of this embodiment, a plurality of random access memory cell arrays are arranged within the same entry of the address conversion device, and the distance between the outputs of data read from them is shortened, so that the data transfer distance and transfer time are reduced. can be shortened. Another advantage is that it is possible to use an associative memory, which is generally used and has a decoder in the center and memory cell arrays are arranged on both sides of the decoder.

Note that the operation timings of the first address translation device and the second address translation device may be the same or different. Furthermore, the number of bits of address and data is m>n. m=n, m<n
Any one is fine.

Effects of the Invention As is clear from the above description, the present invention has a configuration that includes several memories in the same entry of an address translation device, and these are arranged without being separated, so that they can be accessed from close locations. Since the data is output, the data transfer distance between the address translation device and the memory is shortened, which has the effect of shortening the transfer time. Furthermore, unnecessary space created on the random access memory cell array side when associative memory cells and random access memory cells are arranged in an array is also avoided by arranging at least two random access memory cell arrays in parallel in a direction perpendicular to the bit line. This can be eliminated by increasing the integration density. As described above, according to the present invention, high speed and high integration can be realized, and the practical effects are great.

The present invention also has two address conversion devices arranged on the left and right sides of the decoder, and in this case, the decoder is located in the center and memory cell arrays are arranged on both sides of the decoder, which is commonly used. This has the advantage of using an associative memory in which there is a decoder in the center and associative memory cell arrays arranged on both sides of the decoder. The two left and right address translation devices can be operated independently, and in that case, the operation timings of the two address translation devices can be made to differ. Furthermore, the number of bits of address and data is m
> n s m = n N m < n and can be applied to any case, and the practical effect is great.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a schematic block diagram of a semiconductor memory device according to a second embodiment of the present invention, and FIG. 3 is a schematic block diagram of a semiconductor memory device according to a second embodiment of the present invention. FIG. 4 is a schematic block diagram of a semiconductor memory device according to a fourth embodiment of the present invention, and FIG. 5 is a schematic block diagram of a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 6 is a schematic block diagram of a semiconductor memory device according to a sixth embodiment of the present invention, FIG. 7 is a circuit diagram of a control means in an embodiment of the present invention, and FIG. The figure is a circuit diagram of an associative memory cell according to an embodiment of the present invention, and FIG. 9 is a circuit diagram of a random access memory cell according to an embodiment of the present invention. 1... Content addressable memory cell array, 2.3.3a. 3b・
...Random access memory cell array, 4,6. 6
a, 5b...decoder, 5...control means, 7,9.
10.10a. 10b... Word signal, 8... Coincidence detection line, 11, 12.13.14.15.16, 30,
31.32.33.34.35.36.37.38.3
9...Bit line, 17.18.18a, 18b...
Address signal, 19... Comparator, 20... Comparison result output, 21... Tag memory cell array, 22.24.
...Control signal, 23...P channel MOS transistor, 25...OR circuit, 26...AND circuit, 2
7...Sense amplifier, 28...N channel MOS transistor, 29...P channel MOS transistor.

Claims (9)

[Claims] (1) One entry of the address translation device is at least
an associative memory cell array that stores and compares m-bit logical addresses; a first random access memory cell array that stores m-bit physical addresses; and a second random access memory cell array that stores m-bit physical addresses.
a random access memory array, a first decoding means for generating a word signal for the content addressable memory cell array, and a word signal for the first random access memory cell array using the word signal for the content addressable memory cell array and a comparison result. and second decoding means for generating a word signal for the second random access memory cell array. (2) The semiconductor memory device according to claim (1), having a plurality of entries. (3) The semiconductor memory device according to claim (1) or (2), wherein the second random access memory cell array is a cache tag memory. (4) According to any one of claims (1) to (3), wherein at least two random access memory cell arrays out of the random access memory cell array group included in one entry are arranged in parallel in a direction perpendicular to the bit line. semiconductor storage device. (5) One entry of the first address translation device includes a first associative memory cell array that stores and compares m-bit logical addresses, a first random access memory cell array that stores m-bit physical addresses, and m bit second
a random access memory cell array, a first decoding means for generating a word signal of the first associative memory cell array, and a first decoding means for generating a word signal of the first associative memory cell array and a comparison result of the first random access memory cell array. a second content addressable memory cell array in which one entry of the second address conversion device stores and compares an n-bit logical address; and a second content addressable memory cell array that stores and compares an n-bit logical address; a fourth random access memory cell array of n bits, a second decoding means for generating a word signal for the second content addressable memory cell array, and the second content addressable memory. a second control means for generating a word signal for the third random access memory cell array using a word signal of the cell array and a comparison result, one entry of the first and second address translation devices is a second control means for generating a word signal of the third random access memory cell array using a word signal of the cell array and a comparison result; Bit lines are arranged left and right in parallel with the decoding means at the center, and word signals for the second and fourth random access memory cell arrays are generated by the third decoding means. Device. (6) One entry of the first address translation device includes a first associative memory cell array that stores and compares m-bit logical addresses, a first random access memory cell array that stores m-bit physical addresses, and m bit second
a random access memory cell array, a first decoding means for generating a word signal for the second random access memory cell array, and a first control means, wherein one entry of the second address translation device has n bits. a second associative memory cell array for storing and comparing logical addresses of , a third random access memory cell array for storing n-bit physical addresses, a fourth random access memory cell array for n-bits, and the fourth random access memory cell array for storing and comparing logical addresses of . A second decoding means for generating a word signal for an access memory cell array, and a second control means, wherein one entry of the first and second address translation devices has a bit line centered around the third decoding means. Word signals for the first and second associative memory cell arrays are generated by the third decoding means, and the first control means generates word signals for the first and second content addressable memory cell arrays. The signal and the comparison result are used to generate a word signal for the first random access memory array, and the second control means uses the word signal and the comparison result for the second content addressable memory cell array to generate a word signal for the third random access memory array. A semiconductor memory device that generates a word signal for an access memory array. (7) Claim (5) or (6) having multiple entries
). (8) The second and fourth random access memory cell arrays are cache tag memories.
7) The semiconductor memory device according to any one of 7). (9) The first and second random access memory cell arrays are arranged in parallel in a direction perpendicular to the bit line, and the third and fourth random access memory cell arrays are arranged in parallel in a direction perpendicular to the bit line. (5)
) to (8).