JPH0321858U - - Google Patents

Info

Publication number
JPH0321858U
JPH0321858U JP8193189U JP8193189U JPH0321858U JP H0321858 U JPH0321858 U JP H0321858U JP 8193189 U JP8193189 U JP 8193189U JP 8193189 U JP8193189 U JP 8193189U JP H0321858 U JPH0321858 U JP H0321858U
Authority
JP
Japan
Prior art keywords
region
well region
conductivity type
guard ring
anode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8193189U
Other languages
Japanese (ja)
Other versions
JP2509485Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989081931U priority Critical patent/JP2509485Y2/en
Publication of JPH0321858U publication Critical patent/JPH0321858U/ja
Application granted granted Critical
Publication of JP2509485Y2 publication Critical patent/JP2509485Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図と第２図は夫々本考案を説明する為の断
面図と平面図、第３図と第４図は夫々従来例を説
明する為の断面図と平面図である。 1 and 2 are a sectional view and a plan view, respectively, for explaining the present invention, and FIGS. 3 and 4 are a sectional view and a plan view, respectively, for explaining a conventional example.

Claims (1)

【実用新案登録請求の範囲】 (1) 一導電型半導体基板の表面に形成した逆導
電型のウエル領域と、 該ウエル領域の表面に前記ウエル領域とのＰＮ
接合で保護ダイオードを構成するように形成した
一導電型のアノード（又はカソード）領域と、 該アノード（又はカソード領域）の表面にオー
ミツク接触し入力接続パツドと接続されるアノー
ド（又はカソード）電極と、 前記ウエル領域の表面に前記アノード（又はカ
ソード）領域を取り囲むように形成し且つ固定電
位が印加される逆導電型のガードリング領域と、 前記保護ダイオードと隣接し、外部接続パツド
と接続されるＩＧ−ＦＥＴのドレイン（又はソー
ス）を構成する逆導電型のドレイン（又はソース
）領域とを具備する半導体集積回路において、 少なくとも前記保護ダイオードと前記ＩＧ−Ｆ
ＥＴとが隣接する部分において、前記ウエル領域
を前記ガードリング領域よりも拡張し、前記基板
と前記ガードリング領域との間に、前記ウエル領
域の抵抗分が介在するようにしたことを特徴とす
る半導体集積回路。 (2) 前記ウエル領域は前記ガードリング領域の
全周において拡大されていることを特徴とする請
求項第１項に記載の半導体集積回路。[Claims for Utility Model Registration] (1) A well region of an opposite conductivity type formed on the surface of a semiconductor substrate of one conductivity type, and a PN between the well region and the well region on the surface of the well region.
an anode (or cathode) region of one conductivity type formed so as to constitute a protection diode by junction; an anode (or cathode) electrode in ohmic contact with the surface of the anode (or cathode region) and connected to an input connection pad; , a guard ring region of opposite conductivity type formed on the surface of the well region so as to surround the anode (or cathode) region and to which a fixed potential is applied; a guard ring region adjacent to the protection diode and connected to an external connection pad; A semiconductor integrated circuit comprising a drain (or source) region of an opposite conductivity type constituting a drain (or source) of an IG-FET, at least the protection diode and the IG-FET.
In a portion adjacent to the ET, the well region is expanded beyond the guard ring region, so that a resistance of the well region is interposed between the substrate and the guard ring region. Semiconductor integrated circuit. (2) The semiconductor integrated circuit according to claim 1, wherein the well region is expanded all around the guard ring region.
JP1989081931U 1989-07-11 1989-07-11 Semiconductor integrated circuit Expired - Lifetime JP2509485Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989081931U JP2509485Y2 (en) 1989-07-11 1989-07-11 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989081931U JP2509485Y2 (en) 1989-07-11 1989-07-11 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH0321858U true JPH0321858U (en) 1991-03-05
JP2509485Y2 JP2509485Y2 (en) 1996-09-04

Family

ID=31628300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989081931U Expired - Lifetime JP2509485Y2 (en) 1989-07-11 1989-07-11 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2509485Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57147278A (en) * 1981-03-05 1982-09-11 Fujitsu Ltd Protecting device for mis integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57147278A (en) * 1981-03-05 1982-09-11 Fujitsu Ltd Protecting device for mis integrated circuit

Also Published As

Publication number Publication date
JP2509485Y2 (en) 1996-09-04

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term