JPH03218661A - Field effect transistor device - Google Patents

Abstract

PURPOSE:To protect a transistor device against latch-up by a method wherein a region whose conductivity is smaller than those of a source and a drain region is provided just under the source and the drain region, and the the part of the region concerned adjacent to the source region and the drain region is surrounded with an insulating layer or a semi-insulating layer. CONSTITUTION:A p<->-type region 22 of small conductivity and an insulating layer or a semi-insulating layer 24 are provided just under a source region 14 and a drain region 13 of a first MOS transistor (p-ch MOSFET), and a n<->- type region 23 small in conductivity and an insulating layer or a semi-insulating layer 24 are provided just under a source region 18 and a drain region 17 of a second MOS transistor (n-ch MOSFET) which constitutes a complementary transistor with the first MOS transistor. By this setup, a latch-up phenomenon can be moderated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary insulated gate field effect semiconductor device,
Especially regarding source and drain structures.

[Conventional technology]

Generally, a CMOS (complementary metal oxide) semiconductor device has a cross-sectional structure shown in FIG. This figure shows an n-well type CMOS structure, in which an n-well 15 is formed on a P-type substrate 1l, and on top of this an n+ diffusion layer 16 for contacting DD, a p'' source region 14, and a p+ drain. A region l3 is provided, and a gate electrode 1 is provided on the p+ type source region 14 and the p+ type drain region 13 via an insulating film.
9 is provided to constitute a p-ch MOsFET. Further, on the P type substrate 1l, a p+ diffusion layer 12, an n'' type source region 18 and an n
A + type drain region 17 is provided, and an n + type source region 1
8 and n+ drain region 17, a gate electrode 20 is provided via an insulating film to constitute an N-ch MOsFET. Note that a field oxide film 21 is provided between these p-ch MOsFET and N-ch MOSFET.

In the above CMOS configuration, as shown by the dotted line in FIG. 3, a parasitic vertical (particle) pmp transistor T
r. and a lateral npn transistor Tr2 are formed to form a pnpn structure, and when surge current, external noise, heavy particle irradiation, etc. occur, a current is generated in the semiconductor, causing a latch-up phenomenon, and in some cases, It is known that excessive current flows and damages circuits and elements, and conventional measures have been taken to prevent this latch-up phenomenon and to eliminate parasitic transistors.

FIG. 4 is a transmission circuit diagram of the conventional parasitic transistor circuit shown in FIG. 3. From this diagram, the following three points can be raised in order to prevent the latch-up phenomenon.

b) Reduce the resistance values of resistors Rw and Rs+ to make it difficult to turn on transistors Tr, Tr2. (Example) Even if the transistors Trl and Tr2 are turned on, the resistance value of the resistor RSIRw+ is increased to limit the current flowing through them. c) Transistor Tr It Tr
2. Reduce the current amplification factor (hpg) of 2 itself.

[Problem to be solved by the invention]

However, in order to prevent the latch-up phenomenon, it is necessary to add extra component elements, which increases layout dimensions and reduces circuit density.Although some methods use SOI technology to eliminate parasitic transistors, yield This method has the problems of limited throughput and high cost.

An object of the present invention is to provide a complementary insulated gate field effect semiconductor device that can alleviate the wrap-up phenomenon with a simple configuration.

[Differences between the invention and the prior art]

In contrast to the above-described conventional complementary insulated gate field effect semiconductor device, the present invention provides a source/drain structure with a region of the same conductivity type and low conductivity immediately below the source/drain structure. The difference is that the adjacent portion is surrounded by an insulating material or a semi-insulating material.

[Means to solve the problem]

The complementary insulated gate field effect semiconductor device of the present invention comprises a first
a first MIS having a second conductivity type source region and a second conductivity type drain region selectively formed in the first conductivity type well of a second conductivity type semiconductor substrate in which a conductivity type well is formed; A complementary insulated gate field semiconductor comprising a transistor and a second MIS transistor having a first conductivity type source region and a first conductivity type drain region selectively formed on the second conductivity type semiconductor substrate. In the device, the source region 2 of the first M/S transistor is provided directly under the train region with the same conductivity type as the source region and the drain region but with a lower conductivity, and a portion adjacent to the source region and the drain region. is surrounded by an insulating material or a semi-insulating material, and immediately below the source and drain regions of the second MIS transistor, a region having the same conductivity type as the source region and the drain region and a smaller conductivity is provided. The portions adjacent to the source region and drain region are surrounded by an insulating material or a semi-insulating material.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(A) and 1(B) are drawings showing a first embodiment of the present invention. In this embodiment, a P-type substrate 11 (
The p+ type source region l4 selectively formed in the n well 15 at an impurity concentration of ~1515cm-3)
and p” type drain region 13 (both with impurity concentration ~
In the figure, the same numbers as in FIG. 3 indicate the same components. In this embodiment, a p-type region 22 with a small conductivity (1 to 10 Ωcm) is provided directly under the source region l4 and drain region 13 of the first MOS transistor (p-ch MOSFET), and an insulating layer or semi-insulating layer (1000 Ωcm) is provided.
cm or more) 24, and a second MOS transistor (p-ch MOsFET) complementary to the first MOS transistor (p-ch MOsFET) is provided.
Immediately below the source region 18 and drain region 17 of the S transistor (n-ch MOsFET), an n-type region 23 with low conductivity and an insulating layer or semi-insulating layer 24 are provided.

The p-type region 22 is heated to a higher energy level (200
keV~400keV) and low dose (1011~10
It can be formed by ion implantation of 12CIIIl-2). Note that this ion implantation generally uses boron, but oxygen or nitrogen may also be used. Insulating or semi-insulating layer 24
is oxygen or nitrogen ion implantation (200 to 400k e
V, 18cm-2). This depth is only slightly larger than the p+ type source region 14 and the p+ type drain region 13, and is about 1 μm. Similarly, the n-type region 23 can be formed by ion implantation at a higher energy (200 to 400 keV) and a lower dose (101' to 10I2 cm-2) when forming the n+ type region l8 and the n+ type region l7. For this ion implantation, arsenic, phosphorus, etc. are used.

FIG. 5 is a transmission circuit of the parasitic transistor circuit according to the present invention. p-type region 22 and insulating layer or semi-insulating layer 2
4 is the addition of resistor R1 in Fig. 5,
Similarly, a resistance R2 is added to the n-type region 23 and the insulating layer or semi-insulating layer 24. Here, the insulating layer or semi-insulating layer 24 has p that cannot be reduced by the n-type region 23 alone.
This is necessary to lower the resistance of the side surfaces of the + type source region and the p + type drain region 13. As a result, the effect of limiting the current in (1) and the reduction in emitter injection efficiency as explained in the conventional technology, and the effect of reducing the transistor T r in (3)
The effect of substantially reducing hFE can be obtained by setting the bias of l+T r 2 to a reverse bias.

Therefore, the latch-up phenomenon can be prevented or alleviated.

FIGS. 2(A) and 2(B) are drawings showing a second embodiment of the present invention. In contrast to the method for forming the insulating layer or semi-insulating layer 24 in the first embodiment, which relied on ion implantation, in this practical example, a trench groove was formed and a thermal oxide film 26 was attached.
It is formed by creating a groove using the C VD Si 0 2 film 25. At this time, the depth of the trench groove is 1μ
There is no problem with trench groove formation because it is only about m.
In the previous Example 1, since high-energy oxygen ion implantation was used, there was a risk that leakage current would occur due to the defects induced therein, but in this example, no defects would occur. Excellent in this respect.

Further, in Example 1 and Example 2, an n-well system was used, but the same applies to a p-well system.

〔Effect of the invention〕

As explained above, the present invention provides a structure in which a region having a lower conductivity is provided directly below the source train region of a MOSFET, and the portions adjacent to the source region and drain region are surrounded by an insulating layer or a semi-insulating layer. This has the effect of providing a complementary insulated gate field effect semiconductor device that can prevent or alleviate latch-up phenomena without significantly reducing circuit density or yield.

Furthermore, the diffusion capacitance at the bottom and side surfaces of the source and drain regions can be reduced, which has the effect of increasing the operating speed of the transistor.

4

[Brief explanation of drawings]

Figure 1 (A), (B) and Figure 2 (A), (B)
are drawings showing the first and second embodiments of the present invention, respectively, FIG. 3 is a sectional view showing a conventional example of a complementary insulated gate field effect semiconductor device, and FIG. 4 is a latch-up diagram of the conventional example of FIG. FIG. 5 is an equivalent circuit diagram for explaining the latch-up phenomenon prevention measures of the present invention. 11...P type substrate, 12...p+ diffusion layer, 13...p+ type drain region, 14...
...p+ type source region, l5...n well,
16...n+ diffusion layer, 17...n+ type drain region, 18...n+ type source region, 1
9.20...Gate electrode, 21...Field oxide film, 22...P-type region, 23.
... n-type region, 24 ... insulating layer or semi-insulating layer, 25 ... CV D Si0 2 film, 26 ... thermal oxidation film.

Claims (1)

[Claims] A first conductive type semiconductor substrate having a second conductive type source region and a second conductive type drain region selectively formed in the first conductive type well of the second conductive type semiconductor substrate in which the first conductive type well is formed. and a second MIS transistor having a first conductivity type source region and a first conductivity type drain region selectively formed on the second conductivity type semiconductor substrate. In the electric field semiconductor device, a region of the same conductivity type and a conductivity lower than that of the source region and the drain region is provided directly below the source region and the drain region of the first MIS transistor, and the region has the same conductivity type as the source region and the drain region. The adjacent part is surrounded by an insulating material or a semi-insulating material, and the second part is surrounded by an insulating material or a semi-insulating material.
A region of the same conductivity type and a conductivity lower than that of the source and drain regions of the MIS transistor is provided, and a portion adjacent to the source region and the drain region is surrounded by an insulating material or a semi-insulating material. field effect semiconductor device.