JPH03218663A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To shorten a semiconductor in a manufacturing process by a method wherein a multilayered film is patterned under a first etching condition, and irregularities are provided to the side face of the multilayered film under a second etching condition. CONSTITUTION:Silicon oxide multilayered films 7-9 different from each other in type and concentration of impurity are formed, and when the cross sections of the multilayered films 7-9 are exposed and etched, as an etching rate varies corresponding to impurity concentration, the silicon oxide film which contains impurity is quickly etched as compared with one which contains no impurity, in result large irregularities are formed on the cross section of the multilayered films 7-9. When a polysilicon 10 is deposited thereon, as the polysilicon 10 is very excellent in step coverage, it is deposited well even in the irregularities formed on the cross section of the multilayered silicon oxide films 7-9. The polysilicon 10 serving as a storage node is patterned, and then the multilayered films 7-9 of silicon oxide are selectively removed through a wet etching method, whereby a storage node 11 large in area can be formed. By this setup, a semiconductor device of this design can be shortened in a manufacturing process.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a dynamic random access memory (DRAM).

Conventional technology As LSr becomes more and more highly integrated, DRAM is also being devised in various ways to increase the degree of integration.Among these is the so-called stacked memory cell, in which the capacitance portion for charge storage is stacked on a silicon substrate. Although stack cells are considered to be promising due to their ease of manufacturing and high resistance to soft errors, various structures and manufacturing methods have been proposed, including a box structure (Sjnoue, A.
Nitayama, K. Hieda and F.
'A New Stacked
Capacitor Cell with Thin
Box Structured Storage
node, 'Ext. Abs. 21th SSDM
, p. 141 (1989)) East Fin Structure (T
, Ema, S. Kawanago, T. Nishi
i, S, Yoshida, H, Nishibe,
T. Yabu, Y. Kodama, T, Nakano
andM. Taguchi ;”3-DIMENS
IONAL SRACKED CAPACITORCE
LL FOR 16M AND 64M DRAMS,
"IEDM Tech. Dig..p, 592 (
1988)). The manufacturing method of these structures will be explained with reference to process cross-sectional views shown in FIGS. 10 and 11. First, a word line 2, which is a gate of a switching transistor, is formed in a box structure as shown in FIG. 10(a), and an interlayer insulating film 3, a SizNa film 4, and a first SiO2 film 30 are deposited. Thereafter, as shown in FIG. 10(b), a contact hole 18 is formed and I-th polysilicon 6 is deposited.

Next cq lΩ As shown in diagram (c), the second SiO2
film 31, second polysilicon lO, third SiOa film 3
2, the second SiO2 film 31, the second polysilicon lO
, the third SiO2 film 32 is etched.

Thereafter, as shown in FIG. 10(d), a third polysilicon 33 is deposited and the first and third polysilicon are etched by etch-back to form a side wall with the third polysilicon 33.

Next, as shown in Figure 10(e), the remaining second SI
A portion of the O2 film 31 and the second polysilicon lO are etched away by a photolithography process and a dry etching process.

Thereafter, as shown in FIG. 10(f), the first, second, and third Si02 films 14, 31, and 32 are removed by etching to form the storage node 11. Then Figure 1O (g
), a capacitor insulating film l2 and a cell plate l3 are formed.

Next, the fin structure will be explained based on Fig. 11.
As shown in Figure (a), a word line 2, which is also the gate of a switching transistor, is formed on a silicon substrate 1, and an active region Ln1 is formed to form a transistor. A SiN film 15 is deposited thereon as shown in FIG. 11(b). Furthermore, a first SiO2 film 60, a first polysilicon film 62, and a second SiO2 film 61 are deposited thereon. After that, the contact hole 18 is opened as shown in FIG. 11(c).
Open. Furthermore, a second polysilicon film 63 is deposited over it as shown in FIG. 11(d). Thereafter, a resist pattern is formed.Using this resist pattern as a mask, first the second polysilicon film 61 is etched, and then the second SiOa film 6l is etched as shown in FIG. 11(e).
Remove by etching. Thereafter, the first polysilicon film 62 and the first 8102 film 60 are etched in the same manner.
A storage node 11 is formed as shown in FIG. 11(f). After that, a capacitive insulating film l is placed on the surface of the storage node.
After forming a cell plate 13 via this capacitive insulating film 12, a bit line 14 is formed as shown in FIG. This manufacturing method uses polysilicon and S
Although it is possible to increase the storage capacity by increasing the number of laminated layers 102, the number of steps also increases at the same time.

Problems to be Solved by the Invention The problems to be solved by the present invention are as shown in the prior art. In order to obtain a large storage capacity, it is necessary to increase the surface area of the storage node. This means that the number will be very large. For example, in the first conventional technique mentioned above, although it is only concerned with storage node processing, it also extends to the photolithography process (2 steps), the film deposition process (7 steps), and the etching process (7 steps).
S% Ready-to-plate Photolithography process ζ & 2 views of the first patterning of a multilayer film of SiO2 and polysilicon, and the second patterning for hole-drilling Film deposition? 'LSiO
2. Si3N as a wet etching stopper
4 deposits 1st Si02 deposit 1st polysilicon deposit
2nd (7) SiO2 deposition 2nd polysilicon deposition 3rd SiO2 deposition SiOa etching,
Etching must be performed in three steps: second polysilicon etching and second 8102 etching (°C
Furthermore, etching for forming the third polysilicon sidewall - third S during the second hole drilling of the multilayer film
iO2 etching and second polysilicon etching,
Finally, wet etching was performed seven times to remove SiO2. If a multilayer film of Si02 and polysilicon is used in this manner, it is impossible to etch Si02 and polysilicon at the same time, and the number of etching steps increases significantly. In addition, in the process shown in FIG. 3(e), as miniaturization progresses in the second multilayer film hole-drilling process, a process margin cannot be secured due to misalignment in the photolithography process.

In view of the above problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a storage node with a large surface area in a self-aligned manner while suppressing an increase in the number of steps.

Means for Solving the Problems The Present Invention ζ To solve the above problems, the etching rate difference for the first etching condition is smaller than the etching rate difference for the second etching condition (＼ 2
a step of forming a multilayer film consisting of more than one type of layer; a step of performing a first etching for patterning the multilayer film under the first etching condition; and a step of performing a first etching for patterning the multilayer film under the second etching condition. A method of manufacturing a semiconductor device includes: performing a second etching process to form irregularities on a side surface of a multilayer film.

Further, a step of forming a switching transistor on a semiconductor substrate, a step of forming an interlayer insulating film covering the switching transistor on the semiconductor substrate, and a step of forming a multilayer film including two or more types of insulating layers on the interlayer insulating film. and a step of etching a predetermined portion of the multilayer film and the interlayer insulating film by performing a first etching process to form a contact hole in the multilayer film and the interlayer insulating film that reaches the active region of the switching transistor. and a step of etching the side surfaces of the multilayer film and the interlayer insulating film to form irregularities on the side surfaces by performing second etching, and a step of forming a conductive film covering the side surfaces of the multilayer film. A method for manufacturing a semiconductor device, comprising: removing the multilayer film by performing a third etching.

Sarah l-. a step of forming a switching transistor on a semiconductor substrate; a step of forming an interlayer insulating film on the semiconductor substrate to cover the switching transistor; and a step of forming a contact hole in the interlayer insulating film reaching an active region of the switching transistor. and a multilayer film comprising a silicon layer, a portion of which is in contact with the active region of the switching transistor through the contact hole, the multilayer film having an impurity concentration difference at least from an adjacent silicon layer. a step of forming a film on the interlayer insulating film; a step of patterning the multilayer film by performing a first etching; and a step of etching a side surface of the multilayer film by performing a second etching. a step of forming irregularities on the side surface, a step of performing heat treatment to diffuse the impurity, a step of forming a dielectric film covering the multilayer film, and a step of depositing a silicon film on the dielectric film. The present invention utilizes the difference in etching rate of films having different impurity concentrations. In particular, if a multilayer film of silicon oxide films with different impurities and impurity concentrations is formed and a cross section of this multilayer film is exposed and etched, the etching rate will vary depending on the impurity concentration. In comparison, a silicon oxide film containing impurities is etched much faster, and large irregularities are formed in the cross section of the multilayer film. When polysilicon is deposited there, because the step force coverage of polysilicon is extremely good, it can be deposited neatly even in the irregularities of the cross section of the multilayer silicon oxide film.And after patterning the polysilicon that will become the storage node, Multilayer silicon oxide films can be easily and selectively removed by wet etching.
A storage node with a large surface area is formed.

In addition, the process of depositing the multilayer film of silicon oxide film can be reduced to a single deposition sequence in which continuous deposition is performed by controlling the flow rate and pressure of the impurity gas. It is possible to eliminate the increase.

In addition, the etching rate varies depending on the impurity concentration in polysilicon. After forming a multilayer film of polysilicon films with different impurity concentrations, patterning is performed to expose the cross section, and etching the cross section. Since many high layers are etched, unevenness is formed in the cross section, and a storage node having a large surface area is formed.Embodiment A first embodiment of the present invention will be explained based on the cross-sectional process diagram of FIG. 1.

As shown in FIG. 1(a), after forming the switching transistor 50 which also serves as the word line 2, the interlayer insulating film 3 is
The thickness of the 3N4 film 4 is 20 nm, and the thickness of the first NSG 5 is 100 nm.
Deposit m. Next, a contact hole 18 is formed by a photolithography process and an etching process as shown in FIG. PSG (P205 is 8.5 mol
%) 8. After depositing 200 nm of the third NSG9 to form a 600 nm multilayer film, heat treatment is performed at 900 degrees for 30 minutes. Thereafter, the multilayer film of NSC and PSG is patterned by a photolithography process and an etching process as shown in FIG. 1(C). Etching of this multilayer film can be easily performed by reactive ion etching using fluorocarbon-based gas, but the cross section of this patterned multilayer film is wet etched for 2 minutes with a 20:1 solution of NH4F and HF. Then, since the etching rate of PSG containing impurities is sufficiently higher than that of NSC containing almost no impurities, PSG recedes as shown in Figure 1(d), and large irregularities are formed on the cross section of the multilayer film. .

Here, a report on investigating the difference in the etching rate of a silicon oxide film due to the difference in impurity concentration in the silicon oxide film by changing the etching conditions (J.M. Eldridge and P.
Balk, Trans, Metallurg. S
oc. AITM, 242:539, 1968) No. 9
As shown in the figure. Moreover, the experimental results of the present inventor are shown in FIG.

PSG, BPSG, NSG deposited by CVD equipment,
as-depo and at 900°20 in N2
The etch rate is shown when a silicon oxide film (S i 02) is etched with a solution of NH, F and HF in a ratio of 20 to 1 after heat treatment (annealed) for minutes and by thermal oxidation.

From Figure 8, in as-depo PSG and BPSG, P
The etch rate of SG is about 6a. The etch rate of annealed PSG is about 4 times that of annealed NsG. As shown in FIG. 1(e), a second n+ polysilicon film 10 of 150 nm is deposited over the entire surface.

At this time, the wafer is inserted into the low-pressure CVD apparatus, which is a deposition apparatus, so that the first n+ polysilicon and the second n-10 polysilicon are electrically connected. to prevent the formation of an oxide film. Next, the entire polysilicon is etched by anisotropic etching until the first NSC film 5 is exposed.
As shown in FIG. 1(f), the second n+ polysilicon is N
It remains as a sidewall only on the sidewall of the multilayer film of SC and PSG, and is connected to the lth n+ polysilicon 6 at the bottom of the sidewall. After that, when NSG and PSG are removed by wet etching with a hydrofluoric acid solution (NHaF:HF=20:l), only polysilicon remains on the upper side of the Si3N4 film 4, as shown in Figure 1(g). A storage node 11 with a large surface area is formed. Thereafter, as shown in FIG. 1(h), a capacitor insulating film 12 and a cell plate 13 are formed to constitute a memory cell.

Furthermore, bit lines 14 are then formed to form memory cells, but in this embodiment, the etching of the cross section of the silicon oxide film also etches the NSC, so the pattern recedes and the dimensions become smaller. The finished dimensions of the storage node can be set arbitrarily depending on the film thickness of the polysilicon 10. In other words, even if the pattern size becomes smaller, the finished size of the storage node can be increased by increasing the thickness of the second polysilicon 10.

Therefore, it is also possible to finish the interval between storage nodes to be less than the resolution limit of photolithography.

In addition, although PSG and NSC that were heat-treated were used in this example, if they were used without heat treatment, fine irregularities would be formed after wet etching of the PSG cross section due to variations in the P concentration of PSG, which would further reduce the surface area of the storage node. It is possible to increase it.

In this embodiment, the bit line was formed after forming the storage node, but conversely, the storage node can be formed according to this embodiment after forming the bit line.

A cross-sectional view of the memory cell in this case is shown in FIG.

Furthermore, in this example, N is required for forming storage nodes.
Strength NS using two types of multilayer oxide films: SC and PSG
If two or more types of multilayer oxide films such as G, PSG, BPSG, etc. are used, the unevenness of the cross section of the multilayer film can be increased by wet etching due to the difference in the concentration of each oxide film, and the surface area of the storage node can be increased.

The second embodiment of the present invention will be explained based on the process cross-sectional diagram in FIG. 3, but in the first embodiment, NSG, PSG. Strengthening by forming unevenness on the cross section of the three-layer multilayer film of NSG and utilizing this In the present invention, no matter how many multilayer films are stacked, the film deposition process increases, and the other processes do not change at all. It can be implemented. For example, NSG, PSG, NSG, PSG
When a seven-layer multilayer film of SNSG, PSG, and NSC is deposited, a structure as shown in FIG. 3 can be formed using exactly the same steps as in the first embodiment. In this case, the unevenness of the multilayer film will further increase, and the number of protrusions inside the storage node will be three.Although the area occupied on the plane is the same as in the first embodiment, the surface area of the storage node will be significantly increased. 3(a) shows a cross-sectional view of a memory cell in which a bit line is formed after forming a storage node, and FIG. 3(b) shows a cross-sectional view of a memory cell in which a storage node is formed after forming a bit line.

FIG. 5 shows a comparison of the number of steps required to increase the number of protrusions in a storage node between the conventional technique and the present invention. Note that from the number of steps here and the opening of the C-friend storage node contact, this is the number of steps until the formation of the storage node is completed. What is the present invention 1? When the multilayer film deposition process of the inner silicon oxide film of the present invention is performed separately for each layer, the present invention 2 and the above multilayer film deposition process can be performed by simply adjusting the flow rate and pressure of the impurity gas. This was done in one controlled deposition process.While the conventional method increases the number of processes as the number of protrusions in the storage node increases, it can be seen that in the present invention, the number of processes hardly increases. .

A third embodiment of the present invention will be described with reference to FIG. 4, which is a cross-sectional view of the process.

In the first embodiment, the film thickness of the second polysilicon 10 was increased to 100 nm. By making the film thickness of the second polysilicon 10 less than one-half of the PSG film thickness 8, As shown in FIG. 4(a), folds of polysilicon are further formed in the concave portion of PSG8. If the process proceeds in accordance with the first embodiment, a storage node l1 with an even larger surface area may be formed as shown in FIG. 4(b). , NSG is used as a silicon oxide film containing almost no impurities, and PSG is used as a silicon oxide film containing impurities.
Oa, HTO, etc. are used as a silicon oxide film containing impurities.
A fourth embodiment of the present invention will be described with reference to FIG. 6, which is a cross-sectional view of the process.

As shown in FIG. 6(a), a word line 2 which also serves as the gate of a switching transistor is formed on a p-type silicon substrate 1, and n0 active regions 19 are formed to form a switching transistor 50. As shown in FIG. 6(b), an interlayer insulating film 3 is deposited, and a first PSG 20 is formed on it as a silicon oxide film having a different etching rate.
, first NSG21, second PSG22, second N
Deposit SC sequentially. The deposition conditions at this time are first S
iHa: 40sccm, 02: 500sccmS
PHs: 5 sec, PSG is deposited at a temperature of 400° C. The resistor PHs is stopped, NSC is deposited, PHs is flowed again, PSG is deposited, and PHs is stopped and NSC is deposited in a series of continuous steps. A resist pattern 16 is formed by a photolithography process on the multilayer film of silicon oxide film deposited by the above process.
form. As shown in FIG. 6(c), the multilayer film is anisotropically etched using the resist pattern 16 as a mask to open a contact 18 reaching the n+ active region 19 of the switching transistor 50. Next, the cross section of the multilayer film of silicon oxide film exposed in the above process is
When etching is carried out for 60 seconds with a mixed solution of 50% and 50%, large irregularities are formed in the cross section of the multilayer silicon oxide film, as shown in FIG. 6(d). Thereafter, n+ polysilicon is deposited so as to be in contact with the active region l9 of the switching transistor 50.
As shown in FIG. 6(e), the storage node 11 is patterned using the resist pattern 17 as a mask.

Thereafter, as shown in FIG. 6(f), the first PSG 20, the first NSC 21, and the second PS
G22, after removing the second NSG 23, the resist pattern 17 is removed, a capacitive insulating film l2 is formed on the surface of the storage node 11, a cell layer hl3 is formed via the capacitive insulating film 12, and then a bit line is formed. It is.

A fourth embodiment of the present invention will be described with reference to FIG. 6, which is a cross-sectional view of the process.

As shown in FIG. 5(a), a word line 2, which also serves as the gate of a switching transistor, is formed on a p-type silicon substrate 1. A switching transistor 50 is formed by forming n0 active regions 19.

Next, as shown in FIG. 6(b), the switching transistor 5
A contact hole 18 reaching the n0 active region 19 is opened. As shown in FIG. 6(c), two layers of polysilicon 25 containing P as an impurity and two layers of polysilicon 26 containing no impurity are successively deposited thereon. The deposition conditions at this time were: SiH4: 500scc
rrh PH3: 1.2SCCrrL Pressure 1
Polysilicon 25 containing P is deposited at 20 Pa and a temperature of 625 degrees. PHs is stopped, the pressure is set to 50 Pa, and polysilicon 26 containing no impurities is continuously deposited. Furthermore, after flowing PH3 again to return the pressure to 120 Pa and depositing polysilicon 25 containing P, continue to stop PHs and set the pressure to 50 Pa to deposit polysilicon 26 containing no impurities.
Deposit.

A resist pattern 3l is formed by a photolithography process on the polysilicon multilayer film deposited as described above.

When the polysilicon multilayer film is anisotropically etched using the resist pattern 3l as a mask, a shape as shown in FIG. 6(d) is obtained.

The cross section of the polysilicon multilayer film exposed by this process is
When etched for 30 seconds with a 1:400 mixture of F and HNO3, as shown in Figure 6(e), polysilicon 25 containing P has a higher etching rate than polysilicon 26 that does not contain impurities, so unevenness is formed on the cross section. be done. Thereafter, P is diffused over the entire surface of the polysilicon by heat treatment to form a storage node 11. Furthermore, a capacitor insulating film 12 is formed on the surface of the storage node as shown in FIG. After forming plate 13, bit lines are formed to complete the memory cell.

Etching of the exposed cross-section of the polysilicon multilayer film was performed by wet etching in this embodiment.It is also possible to perform isotropic dry etching using fluorine-based gas plasma.

Effects of the Invention From the above explanation, it is clear that according to the present invention, the process for forming storage nodes can be significantly shortened compared to the conventional technology. If it is done in one process, increasing the number of layers in the multilayer silicon oxide film will only lengthen the deposition process, and it is possible to increase the unevenness without increasing the photolithography process and etching process.Increase in the number of processes. Being able to prevent this means that the generation of dust can be suppressed, and it is possible to increase the yield of semiconductor devices.

The present invention has extremely high industrial value in that it can significantly shorten the process and obtain a high yield compared to the conventional technology.

[Brief explanation of drawings]

FIGS. 1 and 2 are process cross-sectional plates showing a first embodiment of the present invention. FIG. 3 is a process cross-sectional plate showing a second embodiment of the present invention. FIG. 4 is a process cross-sectional plate showing a third embodiment of the present invention. The process cross section shown is 5th
Figure 6 shows the process cross section of the fourth embodiment of the present invention. Figure 7 shows the process cross section of the fifth embodiment of the present invention. Figure 8 shows the process cross section of the fifth embodiment of the present invention. Figure 9 shows the etching rate of an oxide film containing a predetermined impurity.
Changes in etching rate of G film FIGS. 10 and 11 are process cross-sectional views showing a conventional method. l...p-type silicon substrate, 2...word line 3.
... Interlayer insulation A 4... Si3N4, 5... First NSC, 6... First n+ polysilicon [7... Second N S G, 8 - P S G, 9... ...Third N
SC, 10... second n+ polysilicon llljll
-...Storage Node Mi l2...Capacitive insulation 111
L13...Cell plate, l4...Bit line 1
6.17-...Resist pattern, 18...Contact hole I9...n10 diffusion layer 20...First PS
G, 21...1st NSG, 22...2nd PSG
123... Second NSG, 25... Polysilicon containing p, 26... Polysilicon not containing impurities, 3l... Resist pattern, 50... Switching transistor.

Claims (14)

[Claims] (1) forming a multilayer film consisting of two or more types of layers in which the difference in etching rate under the first etching condition is smaller than the difference in etching rate under the second etching condition, and under the first etching condition, A step of performing a first etching to pattern the multilayer film; and a step of performing a second etching to form unevenness on the side surface of the multilayer film under the second etching condition. A method for manufacturing a semiconductor device. (2) forming a multilayer film consisting of two or more types of layers in which the difference in etching rate under the first etching condition is smaller than the difference in etching rate under the second etching condition, and under the first etching condition, a step of performing a first etching to pattern the multilayer film; a step of performing a second etching to form unevenness on the side surface of the multilayer film under the second etching condition; forming a conductive film having an etching rate lower than the etching rate of any layer constituting the multilayer film under etching conditions so as to cover the multilayer film; exposing a portion of the multilayer film by forming an opening that reaches the film; performing a third etching under the third etching conditions;
A method for manufacturing a semiconductor device, comprising: removing the multilayer film while leaving the conductive film. (3) The method for manufacturing a semiconductor device according to claim 2, wherein the conductive film is a polycrystalline silicon film. (4) forming a switching transistor on a semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate to cover the switching transistor; and forming a contact hole reaching an active region of the switching transistor in the interlayer insulating film. forming a first conductive film on the interlayer oxide film, a part of which contacts the active region of the switching transistor through the contact hole; ,2
a step of forming a multilayer film consisting of more than one type of insulating layer; a step of performing a first etching on a predetermined portion of the multilayer film until a surface of the first conductive film is exposed; (4) forming a second conductive film covering the side surface of the multilayer film; and third etching. and removing the multilayer film. (5) The method for manufacturing a semiconductor device according to claim 4, wherein the conductive film is a polycrystalline silicon film. (6) The method of manufacturing a semiconductor device according to claim 4, wherein the interlayer insulating film has a laminated structure having an etching stop layer as an intermediate layer, which has a property that it is difficult to be etched by the third etching. (7) The step of forming a multilayer film consisting of two or more types of insulating layers on the first conductive film is a step of successively depositing two or more insulating layers with different impurity concentrations using a CVD method. The method for manufacturing a semiconductor device according to claim 4. (8) Claim 7, wherein the first etching is anisotropic dry etching, and the second etching is isotropic etching.
A method of manufacturing the semiconductor device described above. (9) a step of forming a switching transistor on a semiconductor substrate; a step of forming an interlayer insulating film on the semiconductor substrate to cover the switching transistor; and a multilayer consisting of two or more types of insulating layers on the interlayer insulating film. A step of forming a film and a first etching are performed to etch a predetermined portion of the multilayer film and the interlayer insulating film, and to form a contact hole reaching the active region of the switching transistor in the multilayer film and the interlayer insulating film. a step of etching side surfaces of the multilayer film and the interlayer insulating film by performing a second etching to form unevenness on the side surfaces; and a step of forming a conductive layer covering the side surfaces of the multilayer film. A method for manufacturing a semiconductor device, comprising: forming a film; and removing the multilayer film by performing third etching. (10) The step of forming the multilayer film made of two or more types of the insulating layers on the first conductive film uses a CVD method,
10. The method of manufacturing a semiconductor device according to claim 9, which is a step of successively depositing two or more insulating layers having different impurity concentrations. (11) The step of forming a multilayer film consisting of two or more types of insulating layers on the first silicon film is a step of successively depositing two or more insulating layers with different impurity types using the CVD method. The method for manufacturing a semiconductor device according to claim 9. (12) Claim 1, wherein the first etching is anisotropic dry etching, and the second etching is isotropic etching.
12. The method for manufacturing a semiconductor device according to 0 or 11. (13) forming a switching transistor on a semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate to cover the switching transistor; and forming a contact hole reaching an active region of the switching transistor in the interlayer insulating film. forming a multilayer film of silicon layers, a part of which is in contact with the active region of the switching transistor through the contact hole, the silicon layer having an impurity concentration different from that of at least an adjacent silicon layer; A multilayer film with
a step of forming the multilayer film on the interlayer insulating film; a step of patterning the multilayer film by performing a first etching; a step of etching the side surface of the multilayer film by performing a second etching; a step of forming irregularities in the portion, a step of performing heat treatment to diffuse the impurity, a step of forming a dielectric film covering the multilayer film, a step of depositing a silicon film on the dielectric film, A method for manufacturing a semiconductor device containing. (14) The method of manufacturing a semiconductor device according to claim 13, wherein the step of forming the multilayer film on the interlayer insulating film is a step of successively depositing each layer of the silicon layer using a CVD method.