JPH0321924B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention provides a sequential execution programmable
This is a controller (hereinafter referred to as a PC) that has achieved particularly high processing speed.

As is well known, there are two known input control methods for PCs: the I/O refresh method and the sequential execution method.

In the I/O refresh method, data is periodically transferred repeatedly from input to memory and from memory to output, and all program execution is performed based on data on memory. For this reason, unused input/output and memory are also refreshed, which results in wasted time and
If there is a system in which input/output and memory processing are completed when a program is executed sequentially, the time for this refresh itself becomes a complete waste of time.

For these reasons, the sequential execution method can theoretically achieve faster processing speed than the refresh method.

However, in the case of the conventional sequential execution method, the bus line is separate for the input/output device and the memory, or even if the bus line is the same, the address assignments are different. It is necessary to write data and then transfer the data to the output device, or to scan the input card in advance and then selectively import data from either input or output, which slows down the process. This was one factor.

As a result, the current situation is that the refresh method, which has almost no difference in processing speed from the refresh method and has a simpler program structure, is currently being adopted.

This invention was made to solve the above problem, and its purpose is to control the input/output device (input/output rack) and internal memory in the same way (read/input/write/output). Focusing on this, connect both to the same bus line, make the internal memory have the same address as the address assigned for the input or output card in each rack, and make sure that the input card is an input card. each rack is provided with an identification code indicating an input card according to the identification code, and in response to an addressing operation, provides a signal to the internal memory to deactivate the internal memory; detects a read signal of the input card and sends data from the addressed input card onto the bus line, while detecting an output card or no card according to the identification code responds to the addressing operation and sends data from the addressed input card onto the bus line. A signal to enable the memory is provided to the internal memory, a write signal on the bus line is detected and data is written to the output card, and the internal memory receives the write signal when activated by the rack. The device is configured to detect and read the data, and also to detect a read signal on the bus line and send the data onto the bus line.

Therefore, according to the present invention, when outputting data, data can be written to the internal memory and the output card at the same time, and when inputting data, data is automatically written to the bus from the card or from the internal memory depending on the addressed card. Since it is sent out on the line, it is possible to speed up the processing speed, and it is also possible to easily control reading data from the input card or internal memory, or controlling data writing to the internal memory and output card. However, there are two different
This provides the advantage that different types of data never exist.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Figure 1 is a block diagram showing the overall electrical configuration of the PC according to this embodiment, Figure 2 is a memory map showing the internal memory configuration, and Figure 3 is an identification card provided on each input card and output card. FIG. 4 is a diagram showing the configuration of the pattern, FIG. 4 is a diagram showing an example of a ladder diagram used in this PC, and FIG. 5 is a flowchart showing the configuration of the system program.

As shown in FIG. 1, the PC of this embodiment includes a CPU 1 consisting of a microprocessor, a system program memory 2 consisting of a ROM,
User program memory 3 consisting of RAM
and an operation unit 4 consisting of a keyboard etc.
It is composed of an internal memory 5 composed of RAM and a plurality of input/output racks 6-1 and 6-2 (two in the illustrated example). The internal memory 5 and input/output racks 6-1 and 6-2 are each connected to a CPU.
1 to a common bus line 7.

Each of the input/output racks 6-1 and 6-2 is configured so that a total of eight input or output cards can be connected thereto, and address data corresponding to any card in the rack is stored on the bus line 7. an address selection circuit 8-1 for detecting whether the
8-2 is provided.

When any address data is sent onto the bus line 7, the corresponding address selection circuit 8-1 or 8-2 operates, and the input or output card designated by this operates on the bus line 7.
It will be connected to the data bus that makes up the

The input card 9 and the output card 10 each contain eight input circuits or eight output circuits. The input card is composed of, for example, an I/V conversion circuit that converts a current signal supplied to an input terminal into a voltage signal, and a gate circuit that puts the output voltage of this I/V conversion circuit on a data bus. The opening/closing of this input gate circuit is controlled by a read signal sent from the CPU 1 onto the bus line 7. The output circuit includes, for example, a latch circuit that latches output data sent out on the data bus in response to a write signal sent out from the CPU 1 onto the bus line 7, and a driver circuit that is driven by the output of this latch circuit. These input or output circuits are activated for each card by the action of the address selection circuits 8-1 and 8-2.

Addresses 000 to 177 are assigned to the rack connectors to which each output card or input card is connected, as shown in FIG.

Furthermore, each input/output rack 6-1, 6-2 has 8
Book card identification lines L0 to L7 and one ground line LE are provided, and these lines are configured to be connectable to card identification patterns provided on each card.

As shown in FIG. 3A and B, each identification pattern is
Earth pattern 11 leading to earth line LE,
The ground pattern 11 provided on the input card 9 and the card pattern 12 are electrically connected to each other, while the ground pattern 11 provided on the input card 9 and the card pattern 12 are electrically connected to each other. The provided ground pattern 11 and card pattern 12 are in a non-conducting state.

Therefore, when the input card 9 is easily connected, there is continuity between the corresponding card identification lines L0 to L7 and the ground pattern LE, whereas when the output card is connected, these lines are non-conductive. .

And each of these card identification lines L0 to L7
The output signals of address selection circuits 8-1, 8-2
The signal is taken out via multiplexers 13-1 and 13-2, which are respectively switched and controlled by , and supplied to a chip select terminal CS of the internal memory 5, which will be described later.

In the internal memory 5, the same addresses as the addresses 000 to 177 assigned to the racks 6-1 and 6-2 are assigned as shown in FIG. In the supplied state, when predetermined address data is sent onto the data bus constituting the bus line 7, the contents of the address in the internal memory 5 become readable or writable.

Next, the operation of the PC with the above configuration will be explained in the fifth section.
This will be explained according to the flowchart shown in the figure.

As shown in FIG. 4, if input 040 is turned on, external output 000 is turned on, and then input 0 is turned on.
Assume that a ladder diagram in which the internal output 140 is to be turned on is constructed based on an AND condition between the internal output 140 and the external output 000.

When the program shown in FIG. 5 is executed while this user program is stored in the user program memory 3, initial processing (1) is executed, and the internal memory 5 and output card 1 are
0, a predetermined reset operation is performed and its contents are cleared.

Next, when step (2) is executed, one of the user instructions is read from the user program memory 3.

Now, if the command in the first column of the ladder diagram in Figure 4 is read out, this is to read input data 040 and judge its contents, so the execution result of step (3) will be NO. At the same time, the execution result of step (8) also becomes NO.
After the corresponding command word is determined in the same manner,
The LORD instruction is executed and address data 040 is sent onto the bus line 7.

Here, as shown in FIG. 1, an input card is actually connected to the connection point corresponding to address 040 of rack 6-1. Therefore, when the corresponding input card is addressed in accordance with the address data 040 sent out on the bus line 7, the multiplexer 13-1 outputs a card identification signal "H" to identify this card. The internal memory 5 is disabled by the signal "H". As a result, the CPU 1 receives data from the input card 9, but no data from the internal memory 5. This captured data is then stored in a power flow register (not shown).

Next, return to step (2) and write the next command word.
OUT 000 is read. As a result, step (3) NO becomes step (8) YES, and steps (9), (10), and (11) are sequentially executed.

Here, as shown in FIG. 1, an output card is actually connected to the connection point corresponding to address 000 of rack 6-1.

Therefore, when the corresponding output card is addressed in response to the address data 000 sent out on the bus line 7, the multiplexer 13-
1 outputs a card identification signal "L", and the internal memory 5 is enabled by this card identification signal "L". As a result, the output data sent onto the bus line 7 is simultaneously written to both the area corresponding to address 000 of the internal memory 5 and the address corresponding to address 000 of the output card 10. .

Next, the process returns to step (2) again, and when the next instruction word is read, this is an instruction that should refer to input 041, so steps (3) and (8) are executed in the same manner as above.
The execution result is NO, followed by LORD 041
is executed, the state of input 041 is fetched from the corresponding input card, and this state is stored in a power flow register (not shown).

Then, the process returns to step (2) again, and when the next instruction is read, this instruction is AND 000,
This is an instruction that should refer to output data, so
The execution result of step (3) is YES, and then steps (4), (5), (6), and (7) are executed in sequence.

First, when step (4) is executed, the address 000 is placed on the address bus constituting the bus line 7.
is sent. Here, as mentioned above, easy 6-
The output card 10 is actually connected to the connection point corresponding to address 000 of No. 1. Therefore, when step (4) is executed and address 000 is sent onto the address bus, the multiplexer 13
The output of -1 becomes "L", and the internal memory 5 is enabled by this "L" output.

In this state, when step (5) is executed and a read signal is sent onto the bus line 7, the output cards 10 do not respond to the read signal, so no data is captured by the output cards. On the other hand, the contents stored at address 000 are read from internal memory 5 and sent onto bus line 7.

When step (6) is executed in this state,
The contents of address 000 of the internal memory 5 sent onto the bus line 7 are taken in by the CPU 1, and then an AND operation is executed along with the execution of step (7).

Next, the process returns to step (2), and when the next instruction word is read, this instruction outputs the contents of the power flow register up to that point to the internal output 140, so step (3) NO → Step (8) YES, and then steps (9), (10), and (11) are executed in sequence.

First, when step (9) is executed, the calculation results of the power flow register up to that point are transferred to the bus line 7.
is sent out on the data bus that constitutes the Then,
When step (10) is executed, address data corresponding to address 140 is sent onto the address bus.

Here, as shown in FIG. 1, neither the input nor the output card is connected to the connection point corresponding to address 140 of the rack 6-2, and it is in an empty state.

Therefore, when the address 140 is sent onto the address bus, the output of the multiplexer 13-2 becomes "L", and the internal memory 5 is enabled by this "L" signal.

As a result, when a write signal is sent onto the bus line 7 in subsequent step (11), the calculation data sent onto the bus line 7 is automatically stored in the storage area corresponding to address 140 in the internal memory 5. It will be remembered.

Thus, according to the PC related to this example,
Each rack 6-1, 6-2 and internal memory 5 are connected to a common bus line 7, and the same common address is assigned to both, and each rack has identification lines L0 to L7 dedicated to each card. In addition to providing a ground line LE, each input or output card 9, 10 is provided with a card-specific identification pattern 12.
and the ground pattern 11 are formed to be conductive or non-conductive, and the outputs of these identification lines L0 to L7 are taken out via multiplexers 13-1 to 13-2 in conjunction with the corresponding addressing operation,
Since this is supplied to the chip select terminal CS of the internal memory 5, the CPU 1 sends address data, output data,
By simply outputting read signals and write signals as usual, data is automatically read from the input card or internal memory 5, or data is simultaneously written to the internal memory 5 and output card. Compared to methods such as identifying the type of each card on the side, the time required for data transfer processing is significantly shortened, and this type of
This contributes to speeding up PCs.

As is clear from the above description of the embodiments, the PC according to the present invention significantly increases the processing speed of a PC that adopts this type of sequential execution method, especially when the user program has a large capacity. It has a remarkable effect on

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the overall electrical configuration of the PC according to this embodiment, Figure 2 is a memory map showing the internal memory configuration, and Figure 3 is an identification card provided on each input card and output card. FIG. 4 is a diagram showing the configuration of the pattern, FIG. 4 is a diagram showing an example of a ladder diagram used in this PC, and FIG. 5 is a flowchart showing the configuration of the system program. 1...CPU, 2...System program memory,
3...User program memory, 4...Operation unit, 5...
Internal memory, 6-1, 6-2...I/O rack, 7
...Bus line, 8-1, 8-2...Address selection circuit, 9...Input card, 10...Output card, 11...
Earth pattern, 12...Card pattern.

Claims (1)

[Scope of Claims] 1. It has one or more input/output racks, and each rack is configured to be connectable with one or more input or output cards, and input/output data can be transmitted in units of input or output cards. In the programmable controller that performs the transfer; each rack and internal memory are connected to the same bus line, the internal memory has the same address as the address allocated for the input or output card in each rack, and the input An identification code is attached to the card to indicate that it is an input card, and each rack, upon detecting the input card by the identification code, sends a signal to the internal memory in response to an addressing operation to deactivate the internal memory. and detecting a read signal on the bus line to send data from the addressed input card onto the bus line, while detecting an output card or no card according to the identification code addressing operation. in response to providing a signal to the internal memory to enable the internal memory, detecting a write signal on the bus line and writing data to the output card, the internal memory being activated by the rack; 1. A programmable controller characterized in that the programmable controller is configured to detect the write signal and read the data, and to detect the read signal on the bus line and send the data onto the bus line.