JPH0426312B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data buffer circuit for a printing device, etc., and more specifically, to a printer for printing character information by specifying a character pattern using a character code. A data buffer circuit that has the functions of both a buffer circuit and a printer buffer circuit for printing a pattern as raster data representing dots;
That is, it relates to a printer/printer buffer circuit.

[Prior art]

In conventional printing devices, there is a printer buffer for printing character information by specifying a character pattern using a character code, and a printer buffer for printing image information using raster data representing the pattern in the form of a dot pattern. By providing both printer buffers separately, or by switching one buffer through the I/O port, either one of the two functions was used.

[Problem that the invention seeks to solve]

However, in the former case, two separate memories are required, which increases the number of parts, increases the size of the device, and increases costs. When carrying out this process, it is inevitable that the configuration becomes complicated in terms of both hardware and software, resulting in an increase in cost and a decrease in reliability when commercializing the product.

[Means for solving problems]

The present invention has been made in view of the above circumstances, and involves assigning addresses to each of raster data and character code data that can distinguish whether the data is character code data, and storing the data in a buffer memory. During reading, when the address of the data to be read is given, the address signal is discriminated by an address decoder, and the function as a printer buffer or plotter buffer is automatically switched and performed based on this. It is an object of the present invention to provide a printer/plotter buffer circuit which solves the above-mentioned difficulties.

The printer/plot buffer circuit according to the present invention includes a first memory storing raster data representing a pattern as dots and character code data;
between a second memory that receives data output from the first memory and outputs character pattern data corresponding to the character code data, and a data bus that transfers read data to the first memory; an interposed first gate circuit, a second gate circuit interposed between the second memory and a data bus for transferring read data, and an address assigned to the first memory; an address decoder that discriminates between two types of chip select signals and generates first and second chip select signals; a circuit that reads out raster data stored in the memory of the computer and outputs it to the data bus; The present invention is characterized by comprising a circuit that reads character code data stored in a memory, supplies this to a second memory, and outputs character pattern data corresponding to this data to the data bus.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of a printer/plotter buffer circuit according to the present invention.

In the figure, 1 is a buffer memory which is a first memory, and uses RAM (random access memory). This buffer memory 1 has an address bus AB connected to its address input terminal ADDRESS.
The address is from the chip select signal input terminal.
Chip select signal is applied to CS, and memory write signal is applied to memory write signal input terminal WR.
MWR is given for each.

The input of data to this buffer memory 1 and the output of stored data are data input/output terminals.
Done via DATA. This data input/output terminal DATA is connected via a bus to tri-state buffers 3 and 4 that function as gate circuits and to an address input terminal ADDRESS of a ROM2 that is a second memory.

FIG. 2 is a memory map of the entire device in which the circuit of the present invention is incorporated. As shown in Figure 2, the entire memory area is divided into multiple areas, each with chip select signals CS1, CS2...CSa...CSb.
...Allocated to memory, etc. that is specified and accessed by CSn. Of these memory areas, the area accessed by the chip select signal CSa and the area accessed by the chip select signal CSb are both allocated to the storage area of the buffer memory 1, as described later. Specifically, the address signal consists of a part corresponding to the chip select signal, for example its upper bit, and a part indicating the storage area, for example its lower bit. The address signal and the address signal of the area accessed by the chip select signal CSb designate the address of the same storage area of the buffer memory 1. Therefore, two types of addresses are assigned to apparently the same buffer memory 1, in which the lower bits representing the storage location are the same and only the upper bits corresponding to the chip select signal are different. In other words, data stored at the same address in the buffer memory 1 has two different address signals with different upper bits.
Specifically, the chip select signal is determined by the upper bit.
Access is possible using both address signals: an address signal distinguished from CSa and an address signal distinguished from chip select signal CSb. In the circuit of the present invention, raster data representing a pattern in the form of dots is attached with an address signal having upper bits from which the chip select signal CSa is discriminated, and character code data is attached with an address signal having upper bits from which the chip select signal CSb is discriminated. An address signal having a value is attached to each address signal.

Tri-state buffers 3 and 4 are each configured to pass a signal in one direction only when an enable signal is applied, and
Each is connected to a data bus DB. Specifically, when the tri-state buffer 3 is given an enable signal, the buffer memory 1
The tri-state buffer 4 outputs the data output from the data bus DB to the data bus DB.
The signals from the buffer memory 1 are passed in the input direction to the buffer memory 1.

The data bus DB is connected to a printing head, etc., and data outputted from the buffer memory 1 is transferred to the printing head, etc. via this data bus DB, thereby performing data printing, etc.

ROM (read-only memory) is the second memory
2 is used as a character generator. That is, various character patterns are stored in the ROM 2, and data output from the buffer memory 1 is given as an address signal. The ROM 2 then outputs the character pattern data stored at the address corresponding to the applied address signal to the tri-state buffer 5 from the data output terminal DATA.

The tri-state buffer 5 has the same function as the tri-state buffers 3 and 4 described above, and when an enable signal is applied,
Data output from ROM2 (character pattern)
Outputs the signal to the data bus DB.

Address decoder 6 decodes the address given from address bus AB according to its value and outputs a corresponding chip selector signal. Among these chip select signals, the chip select signal corresponding to the address attached to raster data
CSa is connected to one input terminal of each of OR gate 7 and AND gate 9, and chip select signal CSb corresponding to the address attached to the character code data is
The other input terminal of OR gate 7 and AND gate 1
0 to one of the input terminals.

The output of OR gate 7 is connected to the chip select signal input terminal CS of buffer memory 1 and AND gate 8.
is applied to one input terminal of . This AND
A memory write signal MWR is applied to the other input terminal of the gate 8, and its output is applied to the write signal input terminal WR of the buffer memory 1 as a write signal and to the tri-state buffer 4 as an enable signal. ing.

A memory read signal MRD is applied to the other input terminal of the AND gate 9, and its output is applied to the tri-state buffer 3 as an enable signal.

The above-mentioned memory read signal MRD is applied to the other input terminal of the AND gate 10, and its output is applied to the tri-state buffer 5 as an enable signal.

The operation of the printer/printer buffer circuit of the present invention configured as described above will be explained below.

First, data is written to the buffer memory 1 as follows. In this case, the memory write signal MWR is set to "1", and depending on whether the data to be stored is raster data or character code data, the upper bit is set to the chip select signal.
An address signal corresponding to CSa or CSb is first applied to buffer memory 1 and address decoder 6 from address bus AB. At this time, the address decoder 6 decodes the applied address signal, which discriminates the applied address signal and outputs either the chip select signal CSa or CSb as "1", and at the same time outputs the OR gate 7. is also set to “1”.

When the output of the OR gate 7 becomes "1", this is applied to the chip select signal input terminal CS of the buffer memory 1, and the buffer memory 1 is enabled, and since the memory write signal MWR is also "1", the memory of the buffer memory 1 is Buffer memory 1 is given to the write signal input terminal WR.
is in a state where data can be written. Furthermore,
The output of AND gate 8 also becomes "1", which serves as an enable signal for tri-state buffer 4.
is given to the data bus DB.
Data is input to buffer memory 1 via state buffer 4 . In this case, for the buffer memory 1, only the lower bit representing the storage position of the data in the applied address signal is valid, and the data is stored at the address of the buffer memory 1 corresponding to this.

As described above, data is stored at the address of the buffer memory 1 designated by the address signal.

Data is output from the buffer memory 1 as follows.

First, when outputting the raster data stored in the buffer memory 1, a corresponding address signal is given, and this address signal is not only given to the address input terminal ADDRESS of the buffer memory 1, but also given to the address decoder 6 for discrimination. and the chip select signal CSa is set to “1”.
The memory read signal MRD is also set to "1".
As a result, the input to the chip select signal input terminal CS of the buffer memory 1 becomes "1", so that the data ( In this case, raster data) is output from the data input/output terminal DATA.
At the same time, both inputs of the AND gate 9 become "1" and its output becomes "1", so an enable signal is given to the tri-state buffer 3 and it is opened. Therefore, buffer memory 1
The raster data outputted from the input/output terminal DATA is outputted to the data bus DB through the tri-state buffer 3, and applied to a printing head etc. to print a pattern.

On the other hand, when reading character code data, if a corresponding address signal is given, this address signal is sent to the address input terminal of buffer memory 1.
In addition to being given to ADDRESS, it is also given to address decoder 6 and is discriminated as a chip select signal.
CSb is set to “1” and memory read signal
MRD is also set to "1". As a result, the input to the chip select signal input terminal CS of buffer memory 1 becomes "1", so the data (character code data in this case) corresponding to the lower bit representing the storage location in the given address becomes the data input. Output from output terminal DATA. This character code data is then given to the ROM2 as its address signal, and the ROM2 outputs the character pattern data stored at the address corresponding to this address signal. At the same time, both inputs of the AND gate 10 become "1" and its output also becomes "1", so an enable signal is given to the tri-state buffer 5 and it is opened. Therefore,
The character pattern data outputted from the ROM 2 is outputted to the data bus DB through the tri-state buffer 5, and is applied to a printing head or the like to print the character pattern.

Note that when reading raster data, the read raster data is given to ROM2, but
Since the tri-state buffer 5 is closed, character pattern data is not output to the data bus DB.

〔effect〕

As explained above, according to the present invention, the same storage area of one buffer memory can be used as a printer buffer for printing character information by specifying a character pattern using a character code, and also as a printer buffer for printing character information in the form of a dot pattern. It is possible to easily switch to use as a plotter buffer for printing a pattern using the expressed raster data by simply changing the data readout address. Therefore, it is possible to adopt a simpler configuration in terms of both hardware and software than in the past.

[Brief explanation of drawings]

The drawings show embodiments of the present invention.
The figure is a block diagram showing the configuration of the printer/protester buffer circuit of the present invention, and FIG. 2 is a schematic diagram of the memory map. AB...address bus, DB...data bus,
1... Buffer memory, 2... ROM (character generator), 3, 4, 5... Tri-state buffer, 6... Address decoder, 7...
...OR gate, 8, 9, 10...AND gate.

Claims (1)

[Claims] 1. A first memory that stores raster data representing a pattern as dots and character code data; and a character pattern corresponding to the character code data into which data output from the first memory is input. a second memory that outputs data; a first gate circuit interposed between the first memory and a data bus that transfers read data; and a first gate circuit that transfers read data to and from the second memory. a second gate circuit interposed between a data bus and an address decoder that discriminates between two types of addresses allocated to the first memory and generates first and second chip select signals; When the first chip select signal and the read signal are applied, the first gate circuit opens and the first chip select signal and the read signal are applied.
a circuit for reading out raster data stored in the memory of the device and outputting it to the data bus;
A printer/plotter buffer comprising: a circuit for reading out character code data stored in a second memory, applying it to a second memory, and outputting character pattern data corresponding to this data to the data bus. circuit.