JPH03219329A - Microaddress control system - Google Patents

Abstract

PURPOSE:To make hardware compact and to speed up a reference clock by providing a fixed area specified by a branching microinstruction on a microprogram storing memory, and at the time of executing the microinstruction, directly specifying an address in the fixed area with previously determined fixed address information and instruction code information. CONSTITUTION:The fixed area 8A specified by the branching microinstruction is provided on the microprogram storing memory 8, and at the time of executing the branching microinstruction, an address in the fixed area 8A is directly specified based upon the previously determined fixed address information and the instruction code information to be executed. Thereby, branching microinstruction (mu-OPJ) processing can be executed without waiting an address RAM (ROM) storing jump addresses and without applying a jump address by the microprogram. Consequently, the gate array formation of a microprogram control mechanism around a microsequency can easily be attained and the hardware can be made compact.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a microaddress control system applied to a microprocessor that handles branch microinstructions without an address field.

(Prior Art) Conventionally, in a microprocessor that handles a branch microinstruction (μm0PJ) that does not have an address field,
The micro sequencer that controls the microaddress is equipped with a jump address generation memory that generates the jump address for the branch microinstruction (μm0PJ), and when a certain branch microinstruction (μm0PJ) is issued, a certain process is executed at that step. At the same time, the microprogram was jumping. Having this kind of functionality allows you to create flexible programs.

An example of a conventional hardware configuration in this case is shown in FIG. In FIG. 3, Ol is an OP code jump counter (ROPC) that counts up (+1) when a microinstruction (μm0PJ) is issued. 02 is an instruction register (ROP) that stores software instruction codes. The output of the counter O1 and the output of the instruction register 02 are combined and the read address of the address RAMO4 (A RA
D11. -1). 04 is a branch microinstruction (
This is an address RAM (ARAM) that stores the jump address when μ-〇PJ) is issued. O5 is an address generated (output) from the address RAMO4, and is input to the microsequencer 06. O6 is a microsequencer (MSEQ) that controls the address of the microprogram. O7 is micro sequencer 0
Micro address output from 6 (M A D 15
−0) and microprogram (firmware)
microprogram RAM (MRAM) that stores
) addressing O8. Micro program RA
The microprogram address output from M0B is once natched to register (RD R63-0) 09,
It is used to control various hardware inside the CPU through the bus OLD. Some of them are micro decoders (MD E
C) Input to OIL and used to control the next microprogram address. That is, micro decoder 011
The output becomes the input of the microsequencer 06.

From this micro decoder 011 to micro sequencer 0
To simplify the explanation, three microinstructions (μmEND, u-
Only OPJ, tl-NORM) 012 to 014 were described. Among these microinstructions, O12 is a microinstruction indicating the end of the instruction that is output at the last firmware step when the firmware processes a certain software instruction, and is referred to as a μmEND instruction here.

013 is a branch microinstruction that is output when the firmware wants to jump to the contents of address RAMO4, and is referred to here as the μm0PJ instruction.

014 is a normal microinstruction that is output when the microinstruction is not a microbranch instruction, that is, when the microinstruction to be executed next is at the microaddress currently being executed +1, and is referred to as a μmNORM instruction here. Furthermore, μ
- When the END command 012 is output, the counter (ROPC
3-0)-01 is cleared (set to 0").

Now, suppose that an instruction code -15H is given and the firmware processes this instruction in n microsteps. It is assumed that the μm0PJ instruction 013 is output twice. The structure of the microprogram RAMO8 at this time is shown in FIG. 4(a), the structure of the address RAMO4 is shown in FIG. 4(b), and the flowchart of the firmware is shown in FIG.

Here, the operation of the conventional example will be explained with reference to the above-mentioned FIGS. 3 to 5.

Instruction code 15H is set in instruction register (ROP 7-0) 02, and this instruction code (-15
Since the counter (ROPC3-0) 1 is "0" in the μ-END instruction 012 before H) is executed, the instruction code (ROP) stored in the instruction register 02 is sent from the microsequencer 06. Selected, [MA D 1
5-0-15 H], and the microprogram RAM
O8 is accessed. Therefore, the first step of the microinstruction is processed by 151 (151) of the microprogram RAMO8.Here, as shown in the flowchart of FIG. The micro address is [M
A D 15-0- D A R A M 15-01
becomes. Now, [ROPC3-0-0, [RO
Since it is P7-O-15H, the address RAM
4 is the output of address RAM4 when address -15H is accessed (D A RAM 15-0) 05
is the address ADRI. Therefore [M A D
15-0- D A R A M 15-O-ADR1
1, and the second step is to write the microprogram RAM0.
ADRl of & is processed (see FIG. 4). Further, the counter 01 is incremented by 1 and becomes [ROPC8-0-1].

In the second step, process 2 is executed, but since branch processing is not performed, μmNORM instruction 014 is output and [
MAD15-0-DMAD+5-0, and the third step is A of microprogram RAMO8.
DR1+1 is processed. Similarly, the address of the microprogram RAMO8 is incremented by 1 up to the m-th step.

Next, since μm0PJ instruction 013 is issued at the beginning of m step, the next microaddress is [MAD15-0-
It becomes DA RAM 15-01. Now [ROP
C3-0-1. Since the ROP is 7-0-11, address RAMO4 is accessed at address -115H and the output of address RAM04 (D A RAM
15-0) becomes ADH2. Therefore [M A D
15-0-DARAM15-0-DARA, and the m+1st step is the AD of microprogram RAM08.
H2 will be processed.

Thereafter, since there is no branch processing from steps m+1 to n, the μmNORM instruction 014 is output, and the address of the microprogram RAM08 is incremented by 1.

Since the μmEND instruction 12 is issued in the last n steps, the first microaddress of the next firmware instruction is output from the microsequencer 06 as microaddress (MAD 15-0) 07, and the instruction register (ROP 3-0) is outputted from the microsequencer 06. 0) Content power of 02 (cleared. In this way, software instructions are executed sequentially.

(Problems to be Solved by the Invention) Conventionally, when implementing a microprogram control mechanism centered on a microsequencer as described above using a gate array hardware configuration, there have been the following problems. In other words, in order to make the hardware more compact (one board) and improve performance, we would like to convert the address RAM section into a gate (GA), but it is difficult to convert it into a gate array due to restrictions on the number of gates and the number of bins. .

Also, if the address RAM section is deleted, jump processing will be required, which will increase the number of steps and reduce processing speed (especially when the number of microprogram steps per software instruction is small, this will be affected). There was a problem with this.

The present invention has been made in view of the above-mentioned circumstances, and includes an address RAM (or ROM) that stores address information for the branch micro-instruction in a data processing device that handles branch micro-instructions that do not have an address field. The processing performance of the above branch microinstructions can be achieved without unnecessary jump instructions and without increasing the number of jump instructions.This makes it easy to create a gate array for microprogram control mechanisms centered on microsequencers and to make the hardware more compact. The purpose is to provide a microaddress control method that enables this.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a data processing device that handles branch microinstructions that do not have an address field. A fixed area is provided, and when the branch microinstruction is executed, an address within the fixed area is directly specified using predetermined fixed address information and instruction code information to be executed. There is no need to have an address RAM (ROM) that stores the destination address, and there is no need to give the destination address using a microprogram.
The above branch microinstruction (μ-〇PJ) processing becomes possible. With the above configuration, it is possible to easily implement a gate array of a microprogram control mechanism centered on a microsequencer, and the hardware can be made more compact. Furthermore, the speed of the basic clock can be improved due to the compactness, and the processing speed can be improved accordingly. Furthermore, by simplifying the hardware by eliminating the address RAM, it is possible to reduce costs and improve quality by reducing the number of parts, and it can also greatly contribute to the reduction of CPU chips into one chip.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration according to an embodiment of the present invention.

In FIG. 1, 2 is an instruction register (ROP7-0) that stores software instruction codes, and the instruction code (ROP7-0) stored in register 2 is input to the microsequencer 6 through the bus. . Reference numeral 6 denotes a micro sequencer (MSEQ), which controls the micro address (1-) to execute arbitrary micro program processing. 8 is a micro program RAM (MRAM) that stores a micro program (firmware), and the micro address (
Addressed by MAD15-0)7. Here, a fixed area 8A designated by a branch microinstruction (μm0PJ instruction with instruction code 15H) is provided in the specific address area, as shown in FIG. 9 is micro program RAMP! This is a register that carries out the microprogram code from the bus (RD
R13-0) Various information inside the CPU through 10/1-
used for software control. 11 is a micro decoder, which is used for address control in the micro sequencer 6 according to a micro instruction, and is a micro decoder as described above.
D.

Micro instructions 12 to 1 such as μm0PJ and μmNORM
Outputs 4. Here, 12 is the μ-END instruction,
Output at the final microstep in a software instruction. 13 is a μm0PJ instruction, which is output according to the designation of the microprogram.

14 is a μmNORM instruction, which is output in a microprogram other than a branch instruction.

FIG. 2 shows a microprogram R according to an embodiment of the present invention.
It is a memory map diagram showing the structure of AM8, and here,
The above branch microinstruction (μm0PJ of instruction code 15H)
A fixed area 8A designated by a command) is provided.

The operation of an embodiment of the present invention will now be described with reference to FIGS. 1 and 2.

In FIG. 1, the operation of each part except for the microsequencer B can be easily understood from the operation of FIG. 3 described above, so the explanation thereof will be omitted here.

Micro sequencer 6 is μm from micro decoder 11
When the 0PJ instruction 13 is output, a micro address (MAD15-0) 7A as shown in the figure is output in accordance with the instruction code (ROP 7-0) stored in the instruction register 2. In addition, in this microaddress structure, 0
PJADR5-0 can be arbitrarily determined by the designer,
Its value is determined by the fixed area 8A allocated to the microprogram RAM 8.

An example of the configuration of the microprogram RAM 8 in this case is shown in FIG. Here 0PJADR5-0-“000100
In addition, since the lower two bits of the micro address 7^ are set to "0", an area of 4 steps is secured according to the instruction code. The designer can freely set the bit width, but if it is set too large, the area secured in the microprogram RAM 8 according to the instruction code becomes large, and there is no flexibility in program creation.Actually, about 2 bits is appropriate. This seems to be the case, because by securing 2 bits, even if the address RAM is deleted, the first entry + 4 steps -
Processing up to m5 steps can be performed with the same number of steps as before. If it is 5 bits or more, you must jump once, but the impact is 1.
It will be less than double.

In this way, as shown in FIG. 2, a fixed area specified by a branch microinstruction (μm0PJ instruction with instruction code 15H) is stored in a specific address area of the microprogram RAM (MRAM) 8 that stores the microprogram (firmware). 8A is provided, and the branch microinstruction (μ
When executing the m0PJ instruction), the address within the fixed area 8^ is directly specified using predetermined fixed address information and instruction code information to be executed, so that the above-mentioned conventional technique is not possible. Without having address RAM (ROM) storing the destination address,
Furthermore, the branch microinstruction (μm0PJ) processing described above can be performed without giving a destination address using a microprogram. As a result, the gate array (G
A) can be easily realized, the hardware can be made more compact, the basic clock can be made faster, and the processing speed of the entire system can be improved accordingly. Furthermore, by simplifying the hardware by eliminating the address RAM, costs can be reduced, and quality can be improved by reducing the number of parts.

[Effects of the Invention] As detailed above, according to the microaddress control method of the present invention, in a data processing device that handles branch microinstructions without an address field, the microprogram storage memory can be A configuration comprising means for providing a specified fixed area and directly specifying an address within the fixed area using predetermined fixed address information and instruction code information to be executed when executing the branch microinstruction. By doing this, it is possible to process the branch microinstruction mentioned above without having an address RAM (ROM) to store the destination address L/S, and without having to give the destination address by the microprogram. Gate array (GA) is a microprogram control mechanism centered on a sequencer.
This makes it possible to easily realize interconnection of node hardware and to increase the speed of the basic clock as a result.

Furthermore, the processing speed of the entire system can be improved accordingly. Furthermore, by simplifying the nodeware by eliminating the address RAM, it is possible to reduce costs and improve quality by reducing the number of parts, which can greatly contribute to increasing the number of CPUs to 1,000 CPUs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a microprogram control mechanism according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the fixed area allocation of the microprogram RAM in the above embodiment, and FIG. 3 is a diagram showing a conventional example. Figure 4 shows the configuration of the microprogram control mechanism centered on the microsequencer of
5 and 5 are for explaining the operation of the conventional microprogram control mechanism shown in FIG. 3, respectively. FIG. 4 shows the structure of the microprogram RAM and address RAM, and FIG. 5 shows the structure of the firmware. FIG. 3 is a diagram showing a processing flow. 2...Instruction register (ROP), 8...Micro sequencer (MSEQ), 7.7^...Micro address (MAD 15-0), 8...Micro program RAM, 8A... Fixed area, 9... Register (RD R63-0) 10... Bus, 11...
・Micro decoder (MDEC), 12, 13 14・
・Micro instructions (12・μm END instruction, 13・μm
0PJ instruction, 14...μ-NORM instruction). Figure 2 Figure 1

Claims (1)

[Claims] In a data processing device that handles branch microinstructions that do not have an address field, a fixed area designated by the branch microinstruction is provided in the microprogram storage memory, and when the branch microinstruction is executed, a predetermined fixed address is provided. A microaddress control system comprising means for directly specifying an address within the fixed area based on information and instruction code information to be executed.