JPS6158043A - Register address converter circuit - Google Patents

Abstract

PURPOSE:To access an arbitrary subject in a register group by synthesizing other addresses in addition to the address in a register field while the register field in a command language is held. CONSTITUTION:A commoand stored in a command register 11 is decoded by a decoder 12 and outputs a variety of commands. When a read address field Ra is read out, a selection code RS is decoded by a decoder 13a, and a read address RA is written either of 17a and 17b. When a write address field Rb is read out, a selection code WS is decoded by adecoder 13b, and a write address WA is written in either of registers 18a and 18b. An address off-set AO for converting the read address RA and the write address WA is applied to adder circuits 20a and 21a, or 20b and 21b, other address areas in an address space AS can be accessed.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a register address conversion circuit for an information processing device having a group of registers addressed by a register field in an instruction word and accessed by the instruction word. Regarding.

[Prior art and problems]

An information processing device such as a general-purpose electronic calculation stage has one or more general-purpose registers therein for /A calculation, special notes, etc. On the other hand, with the increasing performance and functionality of information processing devices, microprogram control systems have come to be widely adopted, starting from the conventional hard-wired 1. In this microprogram-based information processing device, in addition to normal general-purpose registers, registers and flip-flops for interfaces with external devices and controlled circuits are commonly treated as general-purpose registers by the microprogram. It is being said. Also, LSI
Advances in technology have made it possible to have many registers in these information processing devices, and in applications that require particularly high-speed access, registers are sometimes used as local memory.

Various methods have been proposed as access methods for such register groups consisting of registers and memories, depending on the application, but all of these methods include register fields, register fields, etc. in the instruction word, as shown in Figure 4. This is a system in which a f-field is provided.

In the instruction register 11 shown in FIG.
de is an instruction code field that stores an instruction code, R
A and Rb are register fields each storing one address, and one or more register fields are provided. By addressing with these register fields Ra and Rb, an object to be manipulated by an instruction in a register group such as a memory or a register (not shown) is accessed.

In this way, access to a conventional register group was usually specified by a register field in an instruction word, so as long as the contents of this register field or field are not changed, the target in the register group to be accessed can be arbitrarily selected. could not. This is inconvenient, as it becomes a major constraint on program creation when the configurations and uses of register groups are diversified, as described above.

(Objective of the Invention) The object of the present invention is to solve the drawbacks of the conventional register group addressing method, and to synthesize other addresses in addition to the register field address while preserving the register field in the instruction word. An object of the present invention is to provide a register address conversion circuit that can access any target in a register group.

[Structure of the invention]

In order to achieve the above object, the present invention provides a register address conversion circuit for an information processing device having a register group that is addressed to a register field in an instruction word and accessed by the instruction word. at least one address offset register set by the command word; and a register field provided corresponding to the whole or a part of the register group and designated by the contents of the address offset register and the command word. at least 1111i+ address synthesis means for synthesizing an address from the addresses of
The present invention is characterized in that the entire or part of the register group can be addressed by the output of the address synthesis means without changing the contents of the register field.

[Embodiments of the invention]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is an explanatory diagram of the address space of the address register, and FIG. 3 is an explanatory diagram of address changes within the register cent according to the embodiment of FIG.

In FIG. 1, 11 is the same instruction register as in FIG.
OP code is an instruction code field, and Ra and Rb are register fields. In the embodiment, Ra is for a read address and Rb is for a write address. 12 is an instruction decoder for decoding instruction codes; 13a and 13b are register cent selection decoders for decoding register set selection codes RS and WS in register fields Ra and Rb; 14 is an internal bus; 15a and 15b are two registers. register set with areas 16a and 1
6b is controlled by the output of register set selection decoder 13a and selects register set tSa and 15b and internal bus 1.
Output enable circuit 17a for selectively controlling connection with 4
and 17b are read address registers that specifically specify the read address RΔ read from the register field Ra; 18a and 18b are write address registers that temporarily store the write address WA read from the register field Rb; and 19 is an address. Address offset registers 20a and 20b that store offset amounts
21a and 21b are adder circuits that add the read address and address offset I of the register field Ra, 21a and 21b are adder circuits that add the write address and address offset of the register field Rh, and 22 is an address offset register enable No. 18 (AOR- A selection circuit RΔ which selects the connection between the address offset I read out from the address offset register 19 by ENB) and the adder circuits 20a, 20b and the adder circuits 21a, 21b;
a and RAI) are write addresses for register safes I-15a and 15b, WEa and WEb are write enable signals for register safes h15a and 15b, and a and W8 are register safes I-15a and 1 for W.
Rie I address for 5b, RW a and RWb
For example, it is a register write signal for register sets i5a and 15b. Note that the illustrated register set shows a part of the register group, and each adder circuit is provided corresponding to the whole or part of the register group.

Next, the operation shown in FIG. 1 will be explained. The instruction register 11 constitutes a main storage device (not shown) together with other instruction registers,
Reading is performed sequentially as the program progresses. Instruction code OP codelJ<When read, it is decoded by the instruction decoder 12 and outputs various instructions necessary for the desired operation. When the read address register field Ra is read, the selection code R3 is decoded by the register set selection decoder 13a, and depending on its contents, enables one of the output enable circuits 16a and 16b. Read address RA is written to read address registers 17a and 17b.

When the register field Rb for the write address is read, the selection code WS is decoded by the register set selection decoder 13b, and depending on its contents, a write enable signal WEa for the register set 15a or a write enable signal WEb for the register set 15a is output. Write address WA is written to write address registers 18a and 18b. This fruit Jf! u
In lj, output enable circuit 1 is selected by selection code R3.
6a is enabled, the register set 15a is connected to the internal bus 14, and reading and writing are performed on the register set I-15a.

Therefore, write enable signal WEa is applied to register set 15a.

The address offset register 19 contains an address offset Δ0 for converting the read address RA and write address W from the outside or from the instruction code OP cod.
Stored by e. Address offset register enable added to selection circuit 22 (No. i AOR-
The address offset (AO) read from the address offset I register 19 by ENB is added to the adder circuit 20.
a,, 21a or the adder circuits 201) and 21b. In the embodiment, it is assumed that address offset AO is added to adder circuits 20a and 21a.

The adder circuit 20a adds the read address RA of the read address register 17a and the address offset I-AO of the address offset register 19 to synthesize a new read address RΔa, which is used as a read address for the register set 15a.

Further, the adder circuit 21a and the write address register 18
The write address WA of a and the address offset AO are added to synthesize a new write address WΔa, which is used as the write address for the register set 15a.

Read address RA of register fields Ra and Rb
When the write address WA is n bits, the address space AS has two address areas as shown in FIG.・It occupies a part of S.

By adding the read address RA, write address WA, and address offset 1-AO using adder circuits 20a and 21a, other address areas within the address space AS can be accessed, and other address areas within the same address center can be accessed. Other address areas can be accessed.

FIG. 3 shows an example of accessing another address area within the same address set. (A
) shows the physical address of the register cell l-153 when the AOR-ENB signal is off, that is, the address off cell l-AO is not applied to the adder circuits 2Qa and 21a, and the adder circuit 20a on the left side. , 21a are shown as logical addresses which are composite addresses.

In this case, the physical address and logical address naturally match.

(B) of the figure shows the physical address of the register set 15a when the Δ0R-2NB signal is turned on and the simplest "1" is added as the address offset AO, and the adder circuit 20a on the left side. A logical address that is a composite address output from (or 21a) is shown.

In this way, in addition to the original read address RA and write address W, a logical address modified by an address offset of 80 can be synthesized.

Furthermore, by rewriting the contents of the address offset register 19 by an instruction, that is, by a Q P code, addresses of different registers can be used in the same instruction.

In the above-mentioned embodiment, the address offset cell 1-ΔO is common to each address register 20a, 20b, 21a, 21b, etc., but by increasing the number of bits of the Δ0R-EN B signal, each address register 20a, 2
0b, 21a, 21b, etc., or may be added only to a specific group of address registers.

Furthermore, by providing a plurality of address offset registers 19, different address offsets can be added to each address register to synthesize different logical addresses. Note that the register set is not limited to the illustrated Hllil, and the illustrated register set shows a part of the register group, and each adder circuit may be provided corresponding to the whole or part of the register group. What is being said is
As already mentioned.

〔Effect of the invention〕

As explained above, the present invention modifies the address of a register included in an instruction using an address offset register set by the instruction and synthesizes a logical address, thereby addressing different register areas with the same instruction. I can do it. The degree of freedom in addressing can be further increased by rewriting the contents of the address offset register or changing the combination of register addresses that are combined with the address offset. This makes it possible to use advanced programming techniques such as multi-m programming without having to save the contents of register addresses, thereby greatly improving system throughput. Also, address offset 1 to register enable (Δ0R-EN
B) By controlling signals, it is possible to synthesize logical addresses as described in 1j; 1, and to access each register set using the absolute address of the register field while preserving the value of the address offset register during interrupt processing etc. This allows for detailed processing.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of an address space of an at-register, FIG. 3 is an explanatory diagram of an example of an address change in a register according to the present invention, and FIG. 4 is a diagram of a conventional FIG. 2 is an explanatory diagram of an addressing method. 11...Instruction register, 12...Instruction decoder, 1
3a, 13b...Register set selection decoder, 14
...Internal bus, 15a, 15b...Register set, 16a, 16b...Output enable circuit, 17a
,. 17L+...Read address register, 18a, 18
b...Write address register, 19...Address offset register, 20a, 20b, 21a, 21b
... Addition circuit, 22... Selection circuit.

Claims (3)

[Claims] (1) A register address conversion circuit in an information processing device having a register group addressed to a register field in an instruction word and accessed by the instruction word, wherein at least one register address is set by the instruction word.
at least one address offset register that is provided corresponding to the whole or a part of the register group and that synthesizes an address from the contents of the address offset register and the address of the register field specified by the instruction word. 1. A register address conversion circuit comprising address synthesis means, and addressing all or part of the register group by the output of the address synthesis means. (2) The address synthesis means includes an addition circuit that adds the contents of the address offset register and the address of the register field to synthesize an address. Register address conversion circuit. (3) The address synthesis means accesses all or part of the register group by selecting either an address obtained by adding the contents of the address offset register and the address of the register field, or an address of the register field. 2. The register address conversion circuit according to claim 1, further comprising a selection circuit for selecting the register address conversion circuit.