JPH03219489A - Detector for abnormal address position - Google Patents

Abstract

PURPOSE:To surely judge the correctness of a relative address position by detecting a write address and a read address, judging by finding the correctness of relative address position information, and detecting the abnormality of a memory only when the information is correct. CONSTITUTION:A write clock (b) is generated at a write clock generator 1 for a reproducing signal (a) accompanying by time base fluctuation, and the signal (a) is written on the memory 3 via an A/D converter 2. Write data (c) is read from the memory 3 with a read clock (d) from a clock generator 4, and a read data signal (e) is outputted from a D/A converter 5 as a reproducing signal to which time base correction is applied. The clocks (b), (d) are counted with counters 6, 7, and write and read operating position information (g), (h) in the memory 3 are found, and the relative address position is detected at a detecting part 8, and a judging part 9 judges a state where both address information (j), (k) coincide with each other or difference shows zero as an abnormal state, and outputs judging output (t) to a control part 10, and the control part 10 performs initialization on the memory 3.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Field of Industrial Application) This invention determines the pros and cons of relative address position information obtained from write operation positions and read operation positions of memories that operate asynchronously with each other. The present invention relates to an address position abnormality detection device that determines the occurrence of an abnormal state in a memory only when relative address position information is correct.

(Prior Art) A memory used as a time axis correction medium for a time axis correction circuit used in a device such as a VTR, and an ATM (ATM).
synchronus Transfer Mode
) Write and read operations are essentially asynchronous in the receive buffer memory used in the above.

On the other hand, before the appearance of large-capacity FIFO memories that can perform write and read operations at high speed on the same memory, RAMs were used to cope with the asynchronous interface section described above.

Taking the memory used as the time axis correction medium of the time axis correction circuit as an example, the write operation and read operation of the memory used as the time axis correction medium of the time axis correction circuit are asynchronous with each other, and only the write operation is performed. In other words, since the write operation position is constantly changing, it is necessary to constantly monitor whether an abnormal state has occurred between the write operation position and read operation position in the memory. If an abnormal condition occurs that exceeds the time axis correction range due to an overflow such as writing , or an underflow such as re-reading old data before writing new data,
It is necessary to immediately detect this and initialize the entire time base correction circuit system.

Conventionally, when detecting an abnormal state in such a memory, the relative address position is found based on the write address and the read address, and if they match, it is determined that an abnormal state has occurred. I was trying to make the initial settings.

(Problem to be Solved by the Invention) However, in such a conventional address position abnormality detection device, since the write operation and the read operation are asynchronous with each other, errors may occur in reading the relative address position itself. However, due to an error in reading the relative address position, it is detected that the write address and read address overlap, even though they are actually being written to and read from the correct address position. There have been cases in which it has been incorrectly determined that an abnormal state has occurred.

To explain this background in more detail, RAM has been used as many of the time axis correction media, and the time axis with a time axis correction range of ±1 line is In the configuration of the memory 101 for realizing the correction circuit, it is impossible to perform write and read operations simultaneously on the same RAM. Blocks are arranged in a ring-type configuration, and write and read operations are performed independently for each block. Further, since the relative address position is determined in units of one block, the determination of the relative address position is also performed in units of one block.

However, in recent years, large-capacity FIFO memories that can perform write and read operations asynchronously on the same memory have become available, and by using such FIFO memories, compared to using RAM, The number of memories can be reduced and the circuit configuration has become simpler.

In Figure 5(b), using such a FIFO memory, ±
The configuration example of the memory 102 having a time axis correction range of one line is shown, but if a FIFO memory is used, the FIF
Since the write operation position and read operation position in O memory change on a clock basis, unlike when using conventional RAM, where the operation position changes on a block-by-block basis, the relative address position information itself It is necessary to judge whether it is right or wrong.

However, conventionally, in such a large-capacity FIFO memory, the relative address position information between the write operation position and the read operation position is determined, and an abnormal state of the memory is detected only when the relative address position information is correct. No address position abnormality detection device has been proposed.

This invention was made in view of these conventional problems, and uses a simple configuration to reliably determine whether the relative address position is correct or not when the write operation position and read operation position are changing on a clock basis. An object of the present invention is to provide a memory occupancy detection device that can detect memory occupancy.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an address position abnormality detection device for a memory capable of asynchronously performing a write operation and a read operation on the same memory. A write address detection means for detecting a read address in the memory, a read address detection means for detecting a read address in the memory, and a relative address position from the detection results of each of the write address detection means and the read address detection means,
and determining means for determining whether the relative address position information detected by the relative address position detecting means is correct and outputting the occurrence of an abnormal state only when the relative address position information is correct. It is something that

(Function) In the memory occupancy detection device of the present invention, the write address detection means detects a write address that is performing a write operation, the read address detection means detects a read address that is performing a read operation, and the relative Relative address position information between the write address and the read address is detected by the address position detection means.

The determination means then determines whether the relative address position information is correct, and outputs an abnormal state occurrence only when it is determined that the relative address position information is correct.

(Example) Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

FIG. 1 shows a configuration when applied to a time axis correction circuit as an embodiment of the present invention, in which a write clock generator 1 generates a write clock in response to input of a reproduced signal a with time axis fluctuations. , an analog-to-digital converter (A/D converter) 2 that performs analog-to-digital conversion on the input signal a based on the write clock b from the write clock generator 1, and write data C from the A/D converter 2. A large-capacity FIFO memory 3 in which data is written, a read clock generator 4 that generates a read clock d, and digital-to-analog conversion of read data e from the FIFO memory 3 in accordance with the timing of the read clock d from the read clock generator 4. Digital to analog converter (
(D/A converter) 5.

Also, write clock b from write clock generator 1
a write address counter 6 that counts the read clock d from the read clock generator 4, a read address counter 7 that counts the read clock d from the read clock generator 4, write address information g from these write address counters 6, and read address information from the read address counter 7. Relative address position detection unit 8 that performs relative address position detection based on
, a determination unit 9 that determines whether the relative address position information p obtained by the relative address position detection unit 8 is correct or not, and a control unit that performs time axis correction of the FIFO memory 3 in accordance with the determination output t from the determination unit 9. It is equipped with 10.

FIG. 2 shows a determination unit 9 for the relative address position information p.
, which shows a detailed circuit configuration of a D flip-flop 21 that receives the relative address position information p from the relative address position detector 8 as an input, and a second D flip-flop 22 that receives the output q of this flip-flop 21 as an input. , an OR gate 23 whose inputs are the outputs Q+' of both of these flip-flops 21 and 22, and this OR gate 2.
A third D flip-flop 24 receives the output S of 3 as an input.
It is composed of.

Next, the operation of the memory occupancy detection device having the above configuration will be explained.

In FIG. 1, a write clock generator 1 extracts a time axis variation component from a reproduced signal a with time axis variation, and generates a write clock b including the time axis variation component.

Using this write clock b, the reproduced signal a is converted into digital write data C by the A/D converter 2, and based on the write clock b, data is written to the FIFO memory 3 which can perform write and read operations asynchronously. It is said that

This write data C is converted into a read data signal e by being read from the FIFO memory 3 based on a read clock d which is generated by a read clock generator 4 and is not accompanied by time axis fluctuation. This read data e is converted into an analog playback signal f whose time axis fluctuations have been corrected by the D/A converter 5, and is output.

Here, the write address counter 6 and the read address counter 7 count the locks b and d obtained from the write clock generator 1 and the read clock generator 4 as shown in FIG.
The write operation position and read operation position within are determined as 10-bit address information g and h as shown in FIG. 3(a).

The relative address position detecting section 8 detects the relative address position using only the upper 8 bits of the 10-bit address information g and h in the memory, as shown in FIG. 2(b).

Here, the top 8 of the 10-bit address information g and h
By using bits, the address information j+k used for detection is 1/4 (-1/(2"-8)-1/22) of the address information g and h indicating the address in the memory 3.
) becomes the value of the divided integer.

By dividing the frequency into 1/4 in this manner, the timing becomes as shown in FIG. 3(b). Also, FIFO memory 3
Focusing on the fact that the write operation position and read operation position overlap when an abnormal state occurs in The point where the addresses match or the difference between the address information j and becomes zero is detected as an abnormal state.

Next, this abnormal state detection operation will be explained based on the timing chart of FIG.

The timing diagram of the 8-bit write address information j used for detection by the relative address position detection section 8 is shown in FIG.・.

Further, the relative address position information p which is the output of the relative address position detecting section 8 at that time is shown in FIG. 4(c). As shown in FIG. 4(C), since the data is uncertain, the transition time between the write address and the read address is also uncertain, and the relative address position detector 8 contains uncertain address information. become.

The determining section 9 determines whether the relative address position information p of the relative address position detecting section 8 is valid or not, as shown in FIG. 4 (,C). The determination operation of the determination section 9 will be explained based on the detailed circuit block shown in FIG. 2 and the timing shown in FIG. 4.

First, the relative address position information p from the relative address position device detection unit 8 is detected using the D flip-flop 21 as shown in FIG.
The data is latched with the read clock d as shown in d). The output q from this D flip-flop 21 is as shown in FIG. 2(e).

Similarly, when the relative address position information p is latched by the second D flip-flop 22 using the read clock d,
An output r as shown in FIG. 4(f) is obtained.

In these operations, the uncertain address information of the write address information j that is not synchronized with the read clock d is
Flip-flop 21 may latch (
(U portion in FIG. 4(e)). However, as mentioned above, clock b.

Compared to the cycle of address information j, the frequency is divided by 1/4, so the cycle is longer. Therefore, the uncertain address information U is not latched for more than two clocks.

The outputs Q+r of each of the D flip-flops 21 and 22 are input to an OR gate 23, where if the output cycle is 2 clocks or more, that is, if the write address information and the read address information d match consecutively, the output S is applied to the third D free tube 24, which synchronizes with the lead clock d, and outputs a judgment output t as shown in FIG. 4(h) to the control section 10.

The control unit 10 receives the determination signal t output from the determination unit 9.
Based on this, when it indicates a relative address position match, it is determined that an abnormality has occurred since it indicates that a write operation and a read operation are being performed redundantly to the same address position. Then, the FIFO memory 3 is caused to perform initial settings.

In this way, even if the write operation and read operation are asynchronous, the relative address position information can be reliably determined, and if the relative address position information is correct, the occurrence of an abnormal state can be detected from the relative address position information. By initializing the time base correction circuit, the time base correction circuit system is operated stably.

In addition, in the above embodiment, the judgment on whether or not to use relative address position information was made based on the number of points.
This can also be based on write clock b.

Further, the present invention is not limited to the above-mentioned embodiments, and can be applied not only to time axis correction circuits but also to a wide range of systems that operate asynchronously, such as ATMs.
It can also be applied to reception buffer memory, etc.

[Effects of the Invention] As described above, according to the present invention, when a write operation and a read operation are performed asynchronously on the same memory, a write address and a read address are detected and their relative address position information is determined. Since the memory abnormality is detected only when the relative address position information is correct, there is no need to detect abnormal conditions unnecessarily due to misreading of the relative address position as in the past. , it is possible to reliably detect an abnormal state of a memory location.

[Brief explanation of drawings]

5. Figure 1 is a circuit diagram of one embodiment of this invention, and Figure 2 is a circuit diagram of an embodiment of the present invention.
The figure is a detailed circuit block diagram of the determination section of the above embodiment, FIG. 3 is a timing chart showing the operation of the relative address position detection section of the above embodiment, and FIG. 4 is the operation of the judgment section of the above embodiment. The timing chart shown in FIG. 5(a), (
b) is a plan view showing an intra-membrane memory; 1...Write clock generator 2...Analog-digital (A/D) converter 3...
FIFO memory 4...Read clock generator 5...Digital analog (D/A) converter 6...
Write address counter 7... Read address counter 8... Relative address position detection section 9... Judgment section 10... Control section 6

Claims (2)

[Claims] (1) An address position abnormality detection device for a memory capable of asynchronously performing a write operation and a read operation on the same memory, comprising a write address detection means for detecting a write address in the memory, and a read address in the memory. read address detection means for detecting a read address detection means; a relative address position detection means for detecting a relative address position from the respective detection results of the write address detection means and the read address detection means; and a relative address position detected by the relative address position detection means. An address position abnormality detecting device comprising: determining means for determining the validity of information and outputting an occurrence of an abnormal state only when relative address position information is correct. (2) The write address detection means uses information obtained by dividing the write clock for the write operation by a predetermined ratio as write address information, and the read address detection means uses the read clock for the read operation to be the same as the write clock. The determination means is configured to synchronize with the write clock or the read clock and to use the information divided by the ratio of the relative address position information from the relative address position detection means as the write address information. The relative address position between the write address and the read address is determined only when the determination result is the same in a row by making the determination at a cycle shorter than the read clock and making multiple determinations during one cycle of the write address or read address. 2. The address position abnormality detection apparatus according to claim 1, wherein the address position abnormality detection apparatus determines that the information is correct and only then determines whether an abnormal state of the memory has occurred.