JPH0321996A - Audio signal data processor - Google Patents

Abstract

PURPOSE:To enable sound field control with sufficient accuracy even when a low-speed element is used by allowing a data memory control means and a delay memory control means to write and read audio signal data in and out of data memories through mutually independent data buses. CONSTITUTION:The inputted audio signal data are written in and read out of the data memories 5 and 6 through a 1st data bus 4 and the audio signal data are read out of the data memory 6 through a 2nd data bus 14 in order and stored in positions of a delay memory 17 which are specified with write addresses. Further, the audio signal data are read out of the positions of the delay memory 17 which are specified with read addresses in order and written in the data memory 6 through the 2nd data bus 14, and the audio signal data which are read out of the delay memory 17 and written in the data memory 6 are multiplied by specific coefficient data. Consequently, the sound field control over a reverberation sound with sufficient accuracy is possible without increasing a digital processing speed.

Description

[Detailed description of the invention] Technical field The present invention relates to an audio signal data processing device.

BACKGROUND ART An audio signal data processing device that can perform sound field control to create reverberation and a sense of presence in an acoustic space such as a concert hall or a theater at home or in a car is known. It is shown in the publication No. Such an audio signal processing device is provided with a DSP (digital signal processor) that performs sound field control by digitally processing an audio signal output from an audio signal source such as a tuner. The DSP is capable of repeatedly performing arithmetic processing such as four arithmetic operations at high speed.

However, if the digital processing speed is to be increased in order to finely control the sound field, it is necessary to use expensive elements, and reducing the cost of the DSP has been a problem.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an audio signal data processing device that can perform sound field control with sufficient accuracy even when using low-speed elements.

The audio signal data processing device of the present invention includes an input means for sequentially supplying audio signal data, a data memory control means for writing and reading the audio signal data into and from the data memory, and a delay memory for sequentially reading the audio signal data from the data memory. a delay memory control means for storing the audio signal data in a position specified by a write address of the delay memory, while sequentially reading audio signal data from a position specified by a read address of the delay memory and writing it into the data memory; and an address specifying the write address and the read address. a calculation means for multiplying the audio signal data read by the delay memory control means and written into the data memory by predetermined coefficient data;
This is an audio signal data processing device comprising output means for outputting audio signal data according to the calculation result of the calculation means, and the data memory control means and the delay memory control means control the data memory via independent data buses. It is characterized by writing and reading audio signal data.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the audio signal data processing device as an embodiment of the present invention shown in FIG.
The signal is supplied to the human output interface 3 in the DSP 2 via the /D converter 1. A first data bus 4 is connected to the input/output interface 3. Two signal data RAMs 5.6 are connected to the first data bus 4 as data memories for storing audio signal data. Further, a buffer memory 7 is connected to the data bus 4, and an output of the buffer memory 7 is connected to one input of a multiplier 8. A buffer memory 9 for holding coefficient data is connected to the other input of the multiplier 8, and a coefficient data RAMIO for storing a plurality of coefficient data is further connected to the buffer memory 9. ALU (computing unit) 1
1 is provided for performing calculations such as accumulation of the calculation output of the multiplier 8, and the calculation output of the multiplier 8 is supplied to one input. The other input is supplied with the output of an accumulator 12 that holds the calculation output of ALU II. Further, the output of the accumulator 12 is connected to the data node 4.

A memory control circuit 31 is connected to the signal data RAM 5. The memory control circuit 31 generates a control signal for controlling writing of data to a designated address of the RAM 5 and reading of data from the designated address. A memory control circuit 32 similar to the memory control circuit 31 is connected to the signal data RAM 6 via a switching circuit 33.

The switching circuit 33 switches according to a control signal from the memory control circuit 31 so that data is written to and read from a designated address in the RAM 6. Further, a memory control circuit 34 similar to the memory control circuit 31 is connected to RAMIO.

The signal data RAM 6 is also connected to a second data bus 14 different from the first data bus 4. Specifically, as shown in FIG. 2, 3-state buffers 739a and 39b are provided between the RAM 6 and the first data bus 4, and
Three-state buffers 740a and 4ob are provided between the RAM 6 and the second data bus 14. buffer 39
a, 39b, 40a, and 40b are individually turned on and off in response to command signals from a sequence controller 18, which will be described later.゜That is, the signal data from the first data bus 4 is
The buffer 39a is turned on when writing to the AM6, and the buffer 39b is turned on when reading signal data from the RAM6 to the first data bus 4. Similarly, when writing signal data from the second data bus 14 to the RAM 6, the buffer 40a is turned on, and the signal data from the RAM 6 is written to the RAM 6.
When reading signal data onto the data bus 14, the buffer 40b is turned on. The three-state buffers that are turned on in response to the command signal are 39a, 39b, and 40a.
, 40b.

An interface 16 for data transfer with an external RAMI 5 is connected to the data bus 14 .

The external RAM 15 is a delay memory provided for creating delayed signal data of audio signal data, and the larger the storage capacity, the more signal data with a longer delay time can be created. A memory control circuit 35 is provided to designate write and read addresses of the RAM 15, and a delay time data RAM 17 is connected to the memory control circuit 35. Writing and reading of delay time data in the RAMI 7 is controlled by a memory control circuit 38.

Interfaces 3, 16, multiplier 8, buffer memories 7, 9, ALUII, accumulator 12, memory control circuits 31, 32, 34, 35, 38, and switching circuit 3
3 is controlled by a sequence controller 18. The sequence controller 18 has a program RA.
M19 is connected and operates according to the program written in the program RAM 19. Program R
A program counter 20 is connected to one of A and M, and each time the count value of the program counter 20 is added, the instruction code of the step corresponding to the new count value is read out from the program RAM 19 and sent to the sequence controller 1.
8. Further, a register 21 that holds a plurality of commands from a microcomputer 24, which will be described later, is connected to the sequence controller 18.

Program RAM 19 and register 21 are main bus 2
2, respectively. A microcomputer 24 is connected to the main bus 22 via an interface 23. Also, the main bus 22 has a transfer buffer 26.
．． 27 are connected. The transfer buffer 26 transfers coefficient data supplied from the microcomputer 24 to RAMI.
Temporarily held in order to be stored in O. The transfer buffer 27 temporarily holds delay time data supplied from the microcomputer 24 in order to be stored in the RAM 17.

The microcomputer 24 is a microprocessor, RA
It consists of an MSROM and an interface (both not shown). A keyboard 25 is connected to the microcomputer 24.

The keyboard 25 has a plurality of mode keys for specifying sound field modes such as Hall 1 and Hall 2 with different sound field characteristics, a frequency band setting key for graphic equalizer adjustment, a level adjustment key, and a mute key (both A plurality of keys such as (not shown) are provided. In addition to the DSP control program processed by the microcomputer 24 itself, the ROM of the microcomputer 24 stores a plurality of sequence control programs processed by the sequence controller 18, a plurality of coefficient data groups supplied to RAMIO, and RA-1.
A plurality of delay time data groups for setting read addresses to be supplied to the memory card 17 are written in advance.

A clock generator 28 is provided in the DSP 2, and clock pulses are sent from the clock generator 28 to the sequence controller 18 and the program counter 2o.
supplied to Further, a clock pulse generated from the clock generator 28 is supplied as a timing signal for sampling of the A/D converter 1.

Furthermore, audio signal data output from the interface 3 is supplied to a mute switch circuit 3o. When the mute switch circuit 3o is on, the audio signal data is further supplied to the D/A converter 3f via the digital filter 36.

The on/off state of the mute switch circuit 30 is controlled by a command signal output from the sequence controller 18.

In such a configuration, the above-mentioned 3-state buffer 39
In addition to the on/off command signals for a to 40b and the mu 1 switch circuit 30, the sequence controller 18 sends command signals to transfer the coefficient data group held in the transfer buffer 26 to RAMIO, and address data held in the transfer buffer 727. A command signal to transfer the details to the RAM 17, a command signal to transfer the audio signal data from the interface 3 to the specified address of the signal data RAM 5.6, read the signal data from the specified address of the signal data RAM 5.6, and transfer it to the buffer memory 7. command signal, RAMIO
A command signal to read coefficient data from a designated address and transfer it to the buffer memory 9, an ALU II three-type operation command signal, and a command signal to transfer the signal data held in the accumulator 12 to a designated address in the signal data RAM 5.6 or to the buffer memory 7. Command signal, transfer command signal from the specified address of signal data RAM 6 to write specified address of external RAM 15, transfer command signal from the delay specified address of external RAM 15 to the specified address of signal data RAM 6, initialize RAM 5.6 and external RAM 15 A command signal such as a reset command signal is generated to perform the reset command. These command signals are generated at appropriate timings according to commands from the microcomputer 24 or programs stored in the program RAM 19. Note that since commands from the microcomputer 24 are held in the command register 21, the sequence controller 18 monitors the contents of the command register 21 during operation according to the program and uses an interrupt operation to generate command signals in response to commands from the microcomputer 24. will occur. The command held in the command register 21 is canceled by, for example, the sequence controller 18 when a corresponding command signal is generated.

When any mode key on the keyboard 25 is operated, the microcomputer 24 determines whether or not the mode key is operated to specify a sound field mode different from the current sound field mode, as shown in FIG. 41). If a sound field mode different from the current sound field mode is specified, the sequence controller 18 issues a mute command to immediately turn off the mute switch circuit 30 and enter the mute state.
(step 42), and the sequence control program and coefficient data group α1.corresponding to the operated key are generated.
a2...α. and delay time data nN+, t2
. . . tn is read from the ROM and transferred (steps 43 to 45). The sequence control program is connected to the RA via the interface 23 and the main bus 22.
The data is transferred to M19 and written by a memory write control circuit (not shown). The coefficient data group is transferred to the transfer buffer 2 via the interface 23 and the main bus 22.
Transferred to 6. The delay time data group is transferred to the transfer buffer 27 via the interface 23 and the main bus 22.
will be forwarded to. After transferring the coefficient data and delay time data to the transfer buffers 26 and 27 in this way, the microcomputer 24 issues a data switching command to the sequence controller 18 (step 46), and further issues an initialization command (step 47). ). The sequence controller 18 controls the memory control circuit 34 in response to the data switching command.
, 38 to write the coefficient data group transferred to the transfer buffer 26 into a predetermined area of RAMIO, and write the delay time data group transferred to the transfer buffer 27 into a predetermined area of the RAM 17. Let it be written. Further, the sequence controller 18 sends the above-mentioned reset command signal to the memory control circuits 31, 32, . . . in response to the initialization command.
35, so the memory control circuit 31,
32. 35, "O" is written in all storage areas of the signal data RAM 5.6 and the external RAM 15.

After executing step 47, a mute release command is issued to the sequence controller 18 to turn on the mute switch circuit 30 and release the mute state (step 48). That is, mute switch circuit 3
0 is turned off only during the period when the RAM 10.17 and the data and programs in it are changed in order to switch the current sound field mode to the pond sound field mode. This is to prevent noise signals caused by changes in data or programs from being output.

Note that the microcomputer 24 does not generate an initialization command, but after the sequence controller 18 generates a command signal for data transfer to RAMIO, 17 in response to a data switching command, it subsequently generates a reset command signal. It's okay.

Next, the signal data processing operation within the DSP 2 will be explained. The audio signal input to the A/D converter 1 is converted into digital audio signal data groups dl, d2...dn at every sampling period synchronized with the clock pulse from the clock generator 28, and the audio signal The data group is supplied to the first data bus 4 via the interface 3. The signal data group supplied to the data bus 4 is supplied to the RAM 5 or 6 and is stored therein.

The signal data written in the RAM 6 is sequentially transferred to an output register (not shown) in the interface 16 by the data bus 14, and is further transferred from the output register to an external R.
It is written to the storage location specified by the write address of AM15. This write address is written to the memory control circuit 35.
The number of addresses corresponding to the number of storage locations in the external RAM 15 is changed in a predetermined order for each transfer signal data. Signal data at a storage location specified by the read address in the external RAM 15 is read out and transferred to an input register (not shown) in the interface 16. Since the delay time data stored in the RAM 17 is read by the memory control circuit 38 and supplied to the memory control circuit 35, the read address is set based on the write address according to the delay time data supplied by the memory control circuit 35. is set to That is, the delay time data provides a delay time between the writing timing of one signal data to the RAM 15 and the reading timing thereof. The signal data transferred and held in the input register within the interface 16 is transferred to the signal data RAM 6 via the data bus 14. This external RAM1
5, delayed audio signal data for sound field control, that is, early reflected sound data is created.

On the other hand, the coefficient data read from RAMIO is supplied to the buffer memory 9 and held there. By properly timing the sequence controller 18, signal data is transferred from the RAM 5.6 or the accumulator 12 to the buffer memory 6, and the multiplier 8 transfers the signal data held in the buffer memory 6 and the signal data held in the buffer memory 9. Multiply the calculated coefficient data. For example, when performing a product-sum operation on the signal data group dl, d2...dn and the coefficient data group α1, α2...α0, first, d1 is held and output to the buffer memory 6. , α1 is held and output to the buffer memory 9, α1 *d1 is calculated in the multiplier 8, and the ALUI is applied to this α1 *d1.
0 is added at I, and the result of the operation is held in the accumulator 12. Next, the buffer memory 6
d2 is held and outputted, α2 is held and outputted to the buffer memory 9, and when α2・d2 is calculated in the multiplier 8, α1・d1 is outputted from the accumulator 12, and α1・d1+α2・d2 is calculated in the ALU 11. Ru. By repeating this, Σαc −dt is calculated. This tαε·dt is output from the interface 3.

As shown in Figure 4, graphic equalizer (G.E.Q) processing for the right channel, sound field control (S.
．． F. The processing is repeated in the order of C') processing, left channel graphic equalizer processing, and right channel sound field control processing. These four processes are processes using the first data bus 4. On the other hand, the process of creating the delayed audio signal data described above is performed in parallel with the graphic equalizer process and the sound field control process.

That is, as shown in FIG. 4, during the graphic equalizer processing of the right channel and the sound field control processing of the left channel, the delayed audio signal for the sound field control processing of the right channel is transferred from the external RAM 15 to the signal data RAM 6 via the second data bus. Data level transfer processing is performed, and during left channel graphic equalizer processing and right channel sound field control processing, external RA is transferred via the second data bus.
Transfer processing of a delayed audio signal data structure for left channel sound field control processing is performed from M15 to signal data RAM 6.

In the case of graphic equalizer processing, the RAM 10 stores coefficient data corresponding to the levels of each frequency band of the left and right channels set in advance by key operations for the graphic equalizer. RA when calculating each frequency band
Coefficient data is sequentially read from MIO and transferred to buffer memory 9. On the other hand, a read address of the RAM 5 is specified by the memory control circuit 31 for each execution step, and signal data is read from the specified address and transferred to the buffer memory 7 via the data bus 4.

For example, the operation of a graphic equalizer for one frequency band will be described as follows. First, in the first step, the signal data dl2 is read from address 12H of the RAM 5, and the read signal data dl2 and the set coefficient data α0 are transferred to the buffer memories 7 and 9, and multiplied by the multiplier 8. let The multiplication result αO”dl
In the third step, which is two steps after the first step, O is added to 2 by the ALUI 1, and the addition result is held in the accumulator 12.

In the second step, the signal data dll is read from address 11H of the RAM 5, and the read signal data dl
The value held in the accumulator 12 (the addition result in the third step) is added to the multiplication result α0・dll by ALUII in the fourth step, and The addition result is held in the accumulator 12. Then,
In the third step, the value held in the accumulator 12 three steps before (the final calculated value for one frequency band) EQn,
+ is transferred to address 101-1 of RAM 5 and buffer memory 7, and multiplied by coefficient data α0 in multiplier 8.

The value held in the accumulator 12 (the addition result in the fourth step) is added to the multiplication result α0·EQn−+ by ALUI 1 in the fifth step, and the addition result is held in the accumulator 12.

In the fourth step, the signal data dl4 is read from address 14 of RAM 5, and the multiplier 8 multiplies the read signal data dI4 and the set coefficient data α0. The value held in the accumulator 12 (the addition result in the fifth step) is added to the multiplication result αO'dl4 by ALUII in the sixth step, and the addition result is held in the accumulator 12. Then, in the fifth step, 131. ．． The signal data d13 is read from address 1, and the multiplier 8 multiplies the read signal data dl3 and the set coefficient data α0. The value held in the accumulator 12 (the addition result in the sixth step) is added to the multiplication result αO'dl3 by ALUII in the seventh step, and the addition result is held in the accumulator 12. In this way, audio signal data for one frequency band of the graphic equalizer is obtained, and the same operation as above is performed for the set frequency band. Although not shown, a shifter is provided at the output stage of the multiplier 8, so that the multiplication result of the multiplier 8 is transferred to the ALU at an appropriate timing.
It is designed to be supplied to l.

Next, the switching operation of the switching circuit 33 will be explained. When the processing operation of the DSP 2 is changed by a key operation, the microcomputer 24 changes the external RAMI as shown in FIG.
5 is used (step 5).
1). For example, when performing the above-mentioned sound field control processing, the external RAM 15 is used, and when only graphic equalizer processing or filter processing is performed, the external RAM 15 is used.
This is a process that does not use AM15. External RAM1
In the case of processing using sequence controller 5, sequence controller 1
A memory independent use command is issued to 8 (step 52).
), in the case of processing that does not use the external RAM 15, a memory sharing command is issued to the sequence controller 18 (step 53). These commands are held in register 21. The sequence controller 18 generates a command signal to switch the switching circuit 33 according to the content of the command regarding the memory held in the command register 21. That is,
In the case of a memory independent use command, a control signal is supplied from the memory control circuit 32 to the RAM 6, and when performing sound field control processing or performing sound field control processing and graphic equalizer processing in parallel as described above, a control signal is supplied from the memory control circuit 32 to the RAM 6. Data RAM6
Writing and reading are controlled by a memory control circuit 32. On the other hand, in the case of a memory sharing command, a control signal is supplied from the memory control circuit 31 to the RAM5.6, and in the case of only graphic equalizer processing or filter processing that does not use external RAM, the signal data RAM5.
, 6 are controlled by the memory control circuit 31. Therefore, the memory control circuit 31
In addition to specifying the write and read addresses of M5, the address of RAM6 is specified.

For example, when writing to RAM 5, if the write address becomes equal to or higher than the upper limit address of RAM 5, the writing proceeds to RAM 6 by specifying the address.

Next, the operation when the mute key of the keyboard 25 is operated will be described. microcomputer 24
When the mute key is operated, it is determined whether or not the mute state is established as shown in FIG. 6 (step 61).
. This is determined from the contents of the mute flag FM. If it is not in the mute state, it is FM-0, so a mute command is generated (step 62), and the mute flag F
The gate is set to 1 (step 63). Since the mute command is held in the command register 21, the sequence controller 18 turns off the mute switch circuit 30. On the other hand, if the mute state is FM-1, a mute release command is generated (step 64), and the mute flag FM is reset to 0 (step 65). Since the mute release command is held in the command register 21 in place of the mute command, the sequence controller 18 turns on the mute switch circuit 30.

Therefore, when the mute key is operated, the mute switch circuit 30 is turned off, and when the mute key is operated again, the mute switch circuit 30 is turned on. While the mute switch circuit 30 is off, the sequence controller 18 continues to generate commands according to the program.

Effects of the Invention As described above, in the audio signal data processing device of the present invention, input audio signal data is written to and read from the data memory via the first data bus, and audio signal data is read from the data memory via the second data bus. The data is sequentially read and stored in the position specified by the write address of the delay memory, and the audio signal data is sequentially read from the position specified by the read address of the delay memory and written to the data memory via the second data bus. , the audio signal data read from the delay memory and written into the data memory is multiplied by predetermined coefficient data. In other words, the transfer processing of early reflection sound data for sound field control via the second data bus can be simultaneously performed in parallel with the data transfer via the first data bus for multiplication, thereby reducing the digital processing speed using expensive elements. It is possible to perform sound field control with sufficient precision without increasing the speed, and to provide functions such as a graphic equalizer.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram specifically showing a part of the device shown in Fig. 1, and Fig. 3 is a block diagram showing an embodiment of the present invention.
5 and 6 are flowcharts showing the operation of the microcomputer in the apparatus of FIG. 1, and FIG. 4 is a diagram showing the order of each processing operation. Explanation of symbols of main parts 2... DSP 4.14... Data bus 5.6... Signal data RAM 7, 9... Buffer memory 8... Multiplier 10... Coefficient data RAM 11 ...ALU 12...Accumulator 17...Delay time data RAM 18...Sequence controller

Claims (1)

[Claims] an input means for sequentially supplying audio signal data; a data memory control means for writing and reading audio signal data into and from a data memory; delay memory control means for sequentially reading audio signal data from a position specified by a read address of the delay memory and writing it into the data memory; addressing means for specifying the write address and the read address; An audio device comprising a calculation means for multiplying the audio signal data read by the memory control means and written in the data memory by predetermined coefficient data, and an output means for outputting the audio signal data according to the calculation result of the calculation means. A signal data processing device,
An audio signal data processing device characterized in that the data memory control means and the delay memory control means write and read audio signal data to and from the data memory via mutually independent data buses.