JPH0324598A - Audio signal data processor - Google Patents

Abstract

PURPOSE:To realize not only sound field control, but also other functions by using two independently writable and readable storage elements as data memories. CONSTITUTION:Two signal data RAMS 5 and 6 are connected as the data memories for storing audio signal data to a 1st data bus 4 connected to an input/output interface 3. A memory control circuit 31 is connected to the signal data RAM 5, a memory control circuit 32 is connected to the signal data RAM 6 for data write and read control through a switching circuit 33, and switching is performed with a control signal from the control circuit 31 so that data are written and read. Consequently, when two different functions, e.g. sound field control and a graphic equalizer function are put in operation at the same time, the storage elements are used independently of each other and not only the sound field control, but also other functions are enabled.

Description

[Detailed description of the invention] Technical field The present invention relates to an audio signal data processing device.

BACKGROUND ART There is an audio signal data processing device that can perform sound field control to create acoustic spaces such as reverberation and presence in concert halls and theaters at home and in cars. Such an audio signal data processing device is
A DSP (digital signal processor) is provided that performs sound field control by digitally processing an audio signal output from an audio signal source such as a tuner. The DSP is equipped with arithmetic means for performing arithmetic processing such as four arithmetic operations, a data memory for storing audio signal data supplied to the arithmetic means, and a data memory for delaying the signal data stored in the data memory. A delay memory can be attached externally. The DSP is configured to transfer signal data between each memory and from the memory to the calculation means according to a predetermined program so that calculation processing of the signal data can be repeatedly performed at high speed. Further, the program is written in a rewritable memory such as a RAM within the DSP, and the program is changed by a microcomputer outside the DSP each time the sound field mode is switched by operation. In other words, by changing the program, you can create any acoustic space.

However, in such an audio signal data processing device, it is desired that the DSP can be used not only to simply control the sound field but also to easily process other functions such as a graphic equalizer.

SUMMARY OF THE INVENTION An object of the present invention is to provide an audio signal data processing device that can easily perform not only sound field control but also other functions.

An audio signal data processing device according to the present invention includes an input means for sequentially supplying audio signal data, a data memory control means for writing and reading audio signal data into and from a data memory, and a delay memory for sequentially reading audio signal data from the data memory. a delay memory control means for storing the audio signal data in a position specified by a write address of the delay memory, while sequentially reading audio signal data from a position specified by a read address of the delay memory and writing it into the data memory; and an address specifying the write address and the read address. a specifying means, a calculation means for multiplying the audio signal data read by the delay memory control means and written in the data memory by predetermined coefficient data, and an output means for outputting the audio signal data according to the calculation result of the calculation means. An audio signal data processing device comprising an audio signal data processing device characterized in that the data memory comprises at least two independently writable and readable storage elements.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the audio signal data processing device as an embodiment of the present invention shown in FIG.
The signal is supplied to the human output interface 3 in the DSP 2 via the /D converter 1. A first data bus 4 is connected to the input/output interface 3. Two signal data RAMs 5.6 are connected to the first data bus 4 as data memories for storing audio signal data. Further, a buffer memory 7 is connected to the data bus 4, and the output of the buffer memory 7 is connected to one input terminal of a multiplier 8. A buffer memory 9 for holding coefficient data is connected to the other side of the multiplier 8, and a coefficient data RAMIO for storing a plurality of coefficient data is further connected to the buffer memory 9. ALU (computing unit) 1
1 is provided for performing calculations such as accumulation of the calculation output of the multiplier 8, and the calculation output of the multiplier 8 is supplied to one input. The other input is supplied with the output of an accumulator 1.2 which holds the calculation output of ALUI 1. Further, the output of the accumulator 12 is connected to the data bus 4.

A memory control circuit 31 is connected to the signal data RAM 5. The memory control circuit 31 generates a control signal for controlling writing of data to a designated address in the RAM 5 and reading of data from the designated address. Signal data RAM
6 includes a memory control circuit 32 similar to the memory control circuit 31;
are connected via a switching circuit 33. Switching circuit 33
is controlled by the RAM 6 by a control signal from the memory control circuit 31.
Switching is performed so that data is written to the designated address and data read from the designated address. Further, a memory control circuit 34 similar to the memory control circuit 31 is connected to RAMIO.

The signal data RAM 6 is also connected to a second data bus 14 different from the first data bus 4. Specifically, as shown in FIG. 2, three state buffers 39a and three state buffers 39b are provided between the RAM 6 and the first data bus 4.
Three-state buffers 40a and 40b are provided between M6 and the second data bus 14. State buffers 39a, 39b, 40a, and 40b are individually turned on in response to command signals from a sequence controller 18, which will be described later. That is, the signal data from the first data bus 4 is
When writing to AM6, the state buffer 39a is turned on, and when reading signal data from the RAM6 to the first data bus 4, the state buffer 39b is turned on. Similarly, the signal data from the second data bus 14 is
When writing to M6, the state buffer 40a is turned on, and when reading signal data from the RAM 6 to the second data bus 14, the state buffer 40b is turned on. In this way, the state buffer that is turned on in response to a command signal is always one of 39a, 39b, 40a, and 40b.

An interface 16 for data transfer with an external RAM 15 is connected to the data bus 14 .

The external RAM 15 is a delay memory provided for creating delayed signal data of audio signal data, and the larger the storage capacity, the more signal data with a longer delay time can be created. A memory control circuit 35 is provided to specify write and read addresses of the RAMI 5, and the memory control circuit 35 includes delay time data RAM 17.
is connected. Writing and reading of delay time data in the RAM 17 is controlled by a memory control circuit 38.

Interfaces 3, 16, multiplier 8, buffer memories 7, 9, ALUII, accumulator 12, memory control circuits 31, 32, 34, 35, 38, and switching circuit 33
The operation of is controlled by a sequence controller 18. The sequence controller 18 has a program RAM.
19 is connected, and operates according to the program written in the program RAM 19. Program RAM
A program counter 20 is connected to 19, and each time the count value of the program counter 20 is added, the instruction code of the step corresponding to the new count value is added to the program RA.
It is read out from M19 and supplied to the sequence controller 18. Further, a register 21 that holds a plurality of commands from a microcomputer 24, which will be described later, is connected to the sequence controller 18.

Program RAM 19 and register 21 are main bus 2
2, respectively. A microcomputer 24 is connected to the main bus 22 via an interface 23. Also, the main bus 22 has a transfer buffer 26.
．． 27 are connected. The transfer buffer 26 transfers coefficient data supplied from the microcomputer 24 to RAMI.
Temporarily held in order to be stored in O. The transfer buffer 27 temporarily holds the delay time data supplied from the microcombi Δ Ito 24 in order to store it in the RAM 17.

The microcomputer 24 is a microprocessor, RA
ROM, and an interface (both not shown). A keyboard 25 is connected to the microcomputer 24.

The keyboard 25 has a plurality of mode keys for specifying sound field modes such as Hall 1 and Hall 2 with different sound field characteristics, a frequency band setting key for graphic equalizer adjustment, a level adjustment key, and a mute key (both A plurality of keys such as (not shown) are provided. The ROM of the microcomputer 24 contains a sequence computer 1 in addition to the DSP control program that the microcomputer 24 itself processes.
- Multiple sequence control programs processed by the roller 18, multiple coefficient data groups supplied to RAMIO, RAM
A plurality of delay time data groups for setting read addresses to be supplied to the memory card 17 are written in advance.

A clock generator 28 is provided in the DSP 2, and clock pulses from the clock generator 28 are sent to the sequence controller 18 and the program counter 20.
supplied to Further, a clock pulse generated from the clock generator 28 is supplied as a sampling timing signal to the A/D converter 1.

Furthermore, audio signal data output from the interface 3 is supplied to a mute switch circuit 30. When the mute switch circuit 30 is on, the audio signal data is further supplied to the D/A converter 37 via the digital filter 36.

The on/off state of the mute switch circuit 30 is controlled by a command signal output from the sequence controller 18.

In such a configuration, the mute switch circuit 3 described above
In addition to the ON/OFF command signal of 0, the sequence controller 18 sends a command signal to transfer the coefficient data group held in the transfer buffer 26 to RAMIO, a command signal to transfer the address data group held in the transfer buffer 27 to the RAM 17, A command signal to transfer the audio signal data from the interface 3 to a designated address in the signal data RAM 5.6, a command signal to read signal data from the designated address in the signal data RAM 5.6 and transfer it to the buffer memory 7, and a command signal to read the signal data from the designated address in the signal data RAM 5.6 and transfer it to the buffer memory 7, from the designated address in RAMIO. ALUII, a command signal for reading coefficient data and transferring it to the buffer memory 9
various arithmetic operation command signals, transfer command signals of the signal data held in the accumulator 12 to the specified address of the signal data RAM 5.6 or the buffer memory 7, transfer from the specified address of the signal data RAM 6 to the write specified address of the external RAM 15 It generates command signals such as a command signal, a transfer command signal from a delay designated address of external RAM 15 to a designated address of signal data RAM 6, and a reset command signal for initializing RAM 56 and external RAM 15. These command signals are generated at appropriate timings according to commands from the microcomputer 24 or programs stored in the program RAM 19. Note that since commands from the microcomputer 24 are held in the command register 21, the sequence controller 18 monitors the contents of the command register 21 during operation according to the program and uses an interrupt operation to generate command signals in response to commands from the microcomputer 24. will occur. Command register 2
A command held at 1 is canceled by, for example, the sequence controller 18 when a corresponding command signal is generated.

When any mode key on the keyboard 25 is operated, the microcomputer 24 determines whether or not the mode key is operated to specify a sound field mode different from the current sound field mode, as shown in FIG. 41). If a sound field mode different from the current sound field mode is specified, the sequence controller 18 issues a mute command to immediately turn off the mute switch circuit 30 and enter the mute state.
(step 42), the sequence control program corresponding to the operated key, coefficient data group α1,
α2...α. and delay time data group tl+t2
. . . tn is read from the ROM and transferred (steps 43 to 45). The sequence control program is sent to R via the interface 23 and the main bus 22.
The data is transferred to AM19 and written by a program memory control circuit (not shown). The coefficient data group is transferred to the transfer buffer 26 via the interface 23 and the main bus 22. The delay time data group is transferred to the transfer buffer 27 via the interface 23 and the main bus 22. After transferring the coefficient data and delay time data to the transfer buffers 26 and 27 in this way, the microcomputer 24 issues a data switching command to the sequence controller 18 (step 46), and further issues an initialization command (step 47). ). The sequence controller 18 generates a predetermined command signal to the memory control circuits 34 and 38 in response to the data switching command, causes the coefficient data group transferred to the transfer buffer 26 to be written in a predetermined area of the RAM 10, and also writes the coefficient data group transferred to the transfer buffer 26 into a predetermined area of the RAM 10. The delay time data group transferred to is written into a predetermined area of the RAM 17.

Further, the sequence controller 18 transmits the above-mentioned reset command signal to the memory control circuit 31.3 in response to the initialization command.
2.35, so the memory control circuit 31,
32.35, "0" is written into all storage areas of the signal data RAM 5.6 and the external RAM 15.

After executing step 47, a menomute release command is issued to the sequence controller 18 to turn on the mute switch circuit 30 and release the mute state (step 48). That is, mute switch circuit 3
0 is turned off only during the period when RAMI 0.17 and the data and programs within it are changed in order to switch the current sound field mode to another sound field mode. This is to prevent noise signals caused by changes in data or programs from being output.

Note that the microcomputer 24 does not generate an initialization command, but after the sequence controller 18 generates a command signal for data transfer to RAMIO, 17 in response to a data switching command, it subsequently generates a reset command signal. It's okay.

Next, the signal data processing operation within the DSP 2 will be explained.The audio signal input to the A/D converter 1 is converted into a digital audio signal data group d l + every sampling period synchronized with the clock pulse from the clock generator 28. d2...dn, and the audio signal data group is supplied to the first data bus 4 via the interface 3. The signal data group supplied to the data bus 4 is supplied to the RAM 5 or 6 and stored therein.

The signal data written in the RAM 6 is sequentially transferred to an output register (not shown) in the interface 16 by the data bus 14, and is further transferred from the output register to an external R.
It is written to the storage location specified by the write address of AM15. This write address is written to the memory control circuit 35.
The number of addresses corresponding to the number of storage locations in the external RAM 15 is changed in a predetermined order for each transfer signal data. Signal data at a storage location specified by the read address in the external RAM 15 is read out and transferred to an input register (not shown) in the interface 16. Since the delay time data stored in the RAM 17 is read by the memory control circuit 38 and supplied to the memory control circuit 35, the read address is set based on the write address according to the delay time data supplied by the memory control circuit 35. is set to That is, the delay time data provides a delay time between the writing timing of one signal data to the RAM 15 and the reading timing thereof. The signal data transferred and held in the input register within the interface 16 is transferred to the signal data RAM 6 via the data bus 14. This external RAM1
5, delayed audio signal data for sound field control is created.

On the other hand, the coefficient data read from RAMIO is supplied to the buffer memory 9 and held there. By properly timing the sequence controller 18, signal data is transferred from the RAM 5.6 or the accumulator 12 to the buffer memory 6, and the multiplier 8 transfers the signal data held in the buffer memory 6 and the signal data held in the buffer memory 9. Multiply the calculated coefficient data. For example, when performing a product-sum operation on the signal data group d,, d2...dn and the coefficient data group α1, α2...αn, first, d1 is held and output in the buffer memory 6. α1 is held and output to the buffer memory 9, α1・dl is calculated in the multiplier 8, and the ALUI is applied to this α1・d1.
1 is added with 0, and the result of the operation is held in the accumulator 12. Next, d2 is held and outputted to the buffer memory 6, α2 is held and outputted to the buffer memory 9, and when α2・d2 is calculated in the multiplier 8, α1・d1 is outputted from the accumulator 12, and αl'dl is outputted in the ALU 11. +α2·d2 is calculated. This Σαε ◆dt is interface 3
is output from.

As shown in Figure 4, graphic equalizer (G.E.Q) processing for the right channel, sound field control (S.
．． The processing is repeated in the following order: F, C) processing, left channel graphic equalizer processing, and right channel sound field control processing. These four processes are processes using the first data bus 4. On the other hand, the process of creating the delayed audio signal data described above is performed in parallel with the graphic equalizer process and the sound field control process.

That is, as shown in FIG. 4, during the graphic equalizer processing of the right channel and the sound field control processing of the left channel, the delayed audio signal for the sound field control processing of the right channel is transferred from the external RAM 15 to the signal data RAM 6 via the second data path. Data transfer processing is performed, and during left channel graphic equalizer processing and right channel sound field control processing, external RAM
5 to the signal data RAM 6, delayed audio signal data for left channel sound field control processing is transferred.

In the case of graphic equalizer processing, the RAM 10 stores coefficient data corresponding to the levels of each frequency band of the left and right channels, which are set in advance for the graphic equalizer by one operation. RA when calculating each frequency band
Coefficient data is read from MIO and stored in buffer memory 9
will be forwarded to.

On the other hand, the memory control circuit 31 specifies a read address of the RAM 5 for each execution step, and signal data is read from the specified address and transferred to the buffer memory 7 via the data bus 4.

For example, the operation of a graphic equalizer for one frequency band will be described as follows. First, in the first step, the signal data dl2 is read from address 12H of the RAM 5, and the read signal data dl2 and the set coefficient data α0 are transferred to the buffer memory 7.9 to be multiplied by the multiplier 8. . The multiplication result αO”dI
In the third step, which is two steps after the first step, O is added to 2 by ALUII, and the addition result is held in the accumulator 12.

11} of RAM5 in the second step. Read signal data dn from address 1, read signal data d
The multiplier 8 multiplies n and the set coefficient data α0. The value held in the accumulator 12 (the addition result in the third step) is added to the multiplication result αO"dl'1 by ALUII in the m4 step, and the addition result is held in the accumulator 12. Next, the third
In step, accumulator 1 3 steps before
The held value EQn-+ of 2 (the final calculated value of 1 frequency band) is transferred to the IOH address of the RAM 5 and the buffer memory 7, and multiplied by the coefficient data α0 in the multiplier 8.

The multiplication result αo-EQl}I is given the value held in the accumulator 12 by ALUII in the fifth step (
(addition result of the fourth step) is added and the addition result is held in the accumulator 12.

In the fourth step, the signal data dH is read from the number 14+ 3111 of the RAM 5, and the multiplier 8 multiplies the read signal data dI4 and the set coefficient data α0. In the sixth step, the value held in the accumulator 12 (the addition result in the fifth step) is added to the multiplication result αO"dl4 by ALUI 1, and the addition result is held in the accumulator 12. Then, T
In step S5, the signal data dI3 is read from address 13}-1 of the RAM 5, and the multiplier 8 multiplies the read signal data dl3 and the set coefficient data α0. The value held in the accumulator 12 (the addition result in the sixth step) is added to the multiplication result αO'd+3 by ALUII in the seventh step, and the addition result is held in the accumulator 12. In this way, audio signal data for one frequency band of the graphic equalizer is obtained, and the same operation as above is performed for the set frequency band. Although not shown, the output stage of the multiplier 8 is provided with a thick, so that the multiplication result of the multiplier 8 is sent to the ALU at an appropriate timing.
It is designed to be supplied to l.

Next, the switching operation of the switching circuit 33 will be explained. When the processing operation of the DSP 2 is changed by a key operation, the microcomputer 24 stores data in the external RAM 1 as shown in FIG.
5 is used (step 5).
1). For example, when performing the above-mentioned sound field control processing, the processing uses the external RAMI5, and when processing only graphic equalizer processing and filter processing, the external RAMI 5 is used.
This is a process that does not use 5. In the case of processing that uses the external RAM 15, a memory independent use command is issued to the sequence controller 18 (step 52), and the external RAM 15 is
In the case of processing that does not use M15, a memory sharing command is issued to the sequence controller 18 (step 53). These commands are held in register 21.

The sequence controller 18 generates a command signal to switch the switching circuit 33 according to the content of the command regarding the memory held in the command register 21. That is, in the case of a memory independent use command, the control signal from the memory control circuit 32 is R.
When performing sound field control processing, or when performing sound field control processing and graphic equalizer processing in parallel as described above, writing and reading of signal data RAM 6 is controlled by memory control circuit 32.

On the other hand, in the case of a memory sharing command, a control signal is supplied from the memory control circuit 31 to the RAM 5.6, and in the case of processing only for graphic equalizer processing or filter processing that does not use external RAM, the signal data is written to the RAM 5. Reading is controlled by memory control circuit 31.

Therefore, the memory control circuit 31 not only specifies the write and read addresses of the RAM 5 but also specifies the address of the RAM 6.

For example, when writing to RAM 5, if the write address becomes equal to or higher than the upper limit address of RAM 5, the writing proceeds to RAM 6 by specifying the address.

Next, the operation when the mute key of the keyboard 25 is operated will be described. microcomputer 24
When the mute key is operated, it is determined whether or not the mute state is established as shown in FIG. 6 (step 61).
. This is determined from the contents of the mute flag FM. If it is not in the mute state, the FM is 10, so a mute command is generated (step 62), and the mute flag F
Set M to 1 (step 63). Since the mute command is held in the command register 21, the sequence controller 18 turns off the mute switch circuit 30. On the other hand, in the mute state, since FM=1, a mute release command is generated (step 64), and the mute flag FM is reset to 0 (step 65). Since the mute release command is held in the command register 21 in place of the mute command, the sequence controller 18 turns on the mute switch circuit 30.

Therefore, when the mute key is operated, the mute switch circuit 30 is turned off, and when the mute key is operated again, the mute switch circuit 30 is turned on. While the mute switch circuit 30 is off, the sequence controller 18 continues to generate commands according to the program.

Effects of the Invention As described above, in the audio signal data processing device according to the present invention, since the data memory is composed of at least two memory elements that can be written and read independently from each other, two memory elements such as a sound field control and a graphic equalizer can be used. When operating two different functions at the same time, each memory element can be used independently of the other, and when only one function is operated, the storage areas of both memory elements can be used as one continuous storage area. . Therefore, DSP
Using this, not only sound field control but also processing of other functions can be easily achieved, and the range of applications of DSP can be expanded.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram specifically showing a part of the device shown in FIG. 1, and FIG.
5 and 6 are flowcharts showing the operation of the microcomputer in the apparatus of FIG. 1, and FIG. 4 is a diagram showing the order of each processing operation. Explanation of symbols of main parts 2... DSP 4.14... Data path 5.6... Signal data RAM 7, 9... Buffer memory 8... Multiplier 10... Coefficient data RAM 11 ...ALU 12...Accumulator 17...Delay time data RAM 18...Sequence controller

Claims (1)

[Claims] input means for sequentially supplying audio signal data; data memory control means for writing and reading audio signal data into and from a data memory; and a position designated by a write address of a delay memory for sequentially reading the audio signal data from the data memory. delay memory control means for sequentially reading audio signal data from a position specified by a read address of said delay memory and writing it into said data memory; and addressing means for specifying said write address and read address; It consists of a calculation means for multiplying the audio signal data read by the delay memory control means and written in the data memory by predetermined coefficient data, and an output means for outputting the audio signal data according to the calculation result of the calculation means. 1. An audio signal data processing device, characterized in that the data memory comprises at least two memory elements that can be written to and read from independently of each other.