JPH03220740A - Structure of semiconductor device - Google Patents
Structure of semiconductor deviceInfo
- Publication number
- JPH03220740A JPH03220740A JP2016860A JP1686090A JPH03220740A JP H03220740 A JPH03220740 A JP H03220740A JP 2016860 A JP2016860 A JP 2016860A JP 1686090 A JP1686090 A JP 1686090A JP H03220740 A JPH03220740 A JP H03220740A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead
- copper foil
- tape
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/701—Tape-automated bond [TAB] connectors
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の構造に関し、特にTABを用いた
半導体装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, and particularly to the structure of a semiconductor device using TAB.
従来、この種の半導体装置の構造は、有機物で出来たベ
ーステープと、接着剤と、銅箔の3層構造からなるTA
Bテープのリード部分に、金・錫・半田等のめっきを施
し、また接続される半導体素子の電極部上に、金・半田
等の突起電極を設け、TABテープのリードと突起電極
を位置合わせし、熱圧着にて接続した構造になっていた
。Conventionally, the structure of this type of semiconductor device is TA, which consists of a three-layer structure consisting of a base tape made of organic material, adhesive, and copper foil.
The lead part of the B tape is plated with gold, tin, solder, etc., and a protruding electrode of gold, solder, etc. is provided on the electrode part of the semiconductor element to be connected, and the lead of the TAB tape and the protruding electrode are aligned. The structure was such that they were connected using thermocompression bonding.
上述した従来の半導体装置の構造は、TABテープのデ
バイス孔中にリードが長く延在していたので、リードの
位置すれ並びに変形が発生し易いちう欠点がある。The structure of the conventional semiconductor device described above has a drawback in that the leads are easily misaligned and deformed because the leads extend long into the device hole of the TAB tape.
また、リードの導体が半導体素子上を絶縁されない状態
で存在するため、リードと半導体素子間で電気的な短絡
が発生し易いという欠点もある。Furthermore, since the conductor of the lead exists on the semiconductor element in an uninsulated state, there is also a drawback that an electrical short circuit is likely to occur between the lead and the semiconductor element.
本発明の目的は、リ−1〜の位置すれ並ひに変形の発生
がなく、かつ、リ−1・と半導体素子間で短絡の発生の
ない半導体装置の構造を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a structure of a semiconductor device in which deformation does not occur in the positions of the wires 1 and 1, and short circuits do not occur between the wires 1 and the semiconductor element.
本発明は、T A B (Tape Automate
d Bonding)を用いた半導体装置の構造におい
て、有機物で出来たベーステープと、接着剤と、銅箔の
3層構造からなるTABテープで、半導体素子を接続さ
せるため前記ベーステープと前記接着剤を貫いて開けら
れたデバイス孔中に延在する、前記半導体素子と接続す
るために設けられた前記銅箔で作られたリードの、前記
半導体素子と接続される側の、前記半導体素子と接続さ
れる前記リード部分を除いて、前記デバイス孔中全面に
、前記半導体素子の接続用電極部上に設けられた導電体
の突起電極の突起厚より薄い有機被膜が形成された前記
TABテープの、前記有機被膜が除去された前記リード
部分と、前記半導体素子とが、前記突起電極を介して接
続されている。The present invention is based on TAB (Tape Automate).
In the structure of a semiconductor device using d bonding, the base tape and the adhesive are used to connect semiconductor elements using a TAB tape consisting of a three-layer structure of a base tape made of an organic substance, an adhesive, and a copper foil. A lead made of copper foil, which extends into a device hole drilled through and is provided for connecting to the semiconductor element, is connected to the semiconductor element on the side to be connected to the semiconductor element. The TAB tape has an organic film thinner than the protrusion thickness of the protrusion electrode of the conductor provided on the connection electrode portion of the semiconductor element, and is formed on the entire surface of the device hole, except for the lead portion. The lead portion from which the organic film has been removed and the semiconductor element are connected via the protruding electrode.
2.1項記載の半導体装置の構造において、前記デバイ
ス孔中の前記有機被膜の除去箇所か、前記半導体素子と
接続される前記リード部分たけてなく、前記半導体装置
を実装する実装基板と接続される前記リード部分も除去
されている。In the structure of the semiconductor device described in Section 2.1, the portion where the organic film is removed in the device hole or the lead portion connected to the semiconductor element is not exposed and is connected to a mounting board on which the semiconductor device is mounted. The lead portion has also been removed.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の第1の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
第1図において、1は75μm厚のポリイミドテープ、
2は接着剤、3は35μmの厚の圧延銅箔で、3層構造
のTABテープを構成している。In Figure 1, 1 is a 75 μm thick polyimide tape;
2 is an adhesive, and 3 is a rolled copper foil with a thickness of 35 μm, constituting a TAB tape with a three-layer structure.
なお、圧延銅箔3て出来ているリード4は、1μm厚の
共晶半田がめっきされている。5は5μm圧のポリイミ
ドで、圧延銅箔3に密着している。6は半導体素子で、
その表面に接続用電極として1μm厚のアルミ電極7が
配置され、また、半導体素子6の保護膜としてアルミ電
極7以外の表面にパッシヘーシコン8か最大2μm厚て
コートされている。更に、アルミ電極7上に高さ15μ
mの金製突起電極9か形成されており、3層構造のTA
Bテープ上の圧延銅箔3と電気的並びに物理的接続が取
られている。Note that the leads 4 made of rolled copper foil 3 are plated with 1 μm thick eutectic solder. 5 is polyimide with a thickness of 5 μm, and is in close contact with the rolled copper foil 3. 6 is a semiconductor element,
An aluminum electrode 7 with a thickness of 1 .mu.m is arranged as a connection electrode on the surface thereof, and a passihesicon 8 is coated with a maximum thickness of 2 .mu.m on the surface other than the aluminum electrode 7 as a protective film for the semiconductor element 6. Furthermore, a height of 15μ is placed on the aluminum electrode 7.
A gold protrusion electrode 9 of m is formed, and the TA has a three-layer structure.
Electrical and physical connections are made with the rolled copper foil 3 on the B tape.
第2図(a)〜(k)は本発明の第1の実施例の製造工
程を説明する工程順に示した断面図である。FIGS. 2(a) to 2(k) are sectional views showing the manufacturing process of the first embodiment of the present invention in order of process.
まず、第2図(a>に示すように、既に20μm厚のエ
ポキシ系接着剤2が塗布された75μm厚のポリイミド
テープ1(商品名ユーピレックス)で35mm幅にスリ
ットされたものを、第2図(b)に示すように、金型を
用いてデバイス5
孔]Oとスプロケット孔(図示せず)を打ち抜いた。な
お、この後の工程は、全てスプロケッ)・孔を用いて搬
送した。First, as shown in FIG. 2 (a), a 75 μm thick polyimide tape 1 (trade name: Upilex), which has already been coated with a 20 μm thick epoxy adhesive 2, is slit to a width of 35 mm. As shown in (b), a device 5 hole]O and a sprocket hole (not shown) were punched out using a mold.The subsequent steps were all carried out using the sprocket hole.
次に、第2図(c)に示すように、片面を化学的に粗化
処理した公称35μm厚の圧延銅箔3(商品名○FC−
ACE箔)を、粗化面を接着剤2の方向に向けて合わせ
、150°C,2,5kg/cm2に調節されたロール
に通し、100℃。Next, as shown in FIG. 2(c), a rolled copper foil 3 (product name ○FC-
ACE foil) with the roughened side facing the adhesive 2, passed through a roll adjusted to 150°C and 2.5 kg/cm2, and heated to 100°C.
4時間乾燥させることによって張り合わせた。It was laminated by drying for 4 hours.
次に、第2図(d)に示すように、デバイス孔10中に
感光性ポリイミド11(商品名パイメル)を、乾燥後1
0μm厚になるよう滴下塗布し、Air雰囲気のクリー
ンオープン中で100°C13秒乾燥させた。Next, as shown in FIG. 2(d), a photosensitive polyimide 11 (trade name: Pimel) is placed in the device hole 10 after drying.
It was applied dropwise to a thickness of 0 μm and dried in a clean open air atmosphere at 100° C. for 13 seconds.
その後、第2図(e)に示すように、200mj/cm
2で感光性ポリイミド11をコンタクト露光し、]O秒
間秒間上た後直ちに15秒間スプレー現像、3秒間オー
バーラツプ、10秒間スプレーリンスした。その後、N
2雰囲気のクリーンオープンで140℃、30分、続い
て250°C11時間乾燥させた。After that, as shown in Fig. 2(e), 200 mj/cm
2, photosensitive polyimide 11 was exposed to contact light for 10 seconds, then immediately spray developed for 15 seconds, overlapped for 3 seconds, and spray rinsed for 10 seconds. After that, N
It was dried at 140° C. for 30 minutes in a clean open atmosphere of 2 atmospheres, and then at 250° C. for 11 hours.
次に、第2図(f)に示すように、感光済みのポリイミ
ド12をCF 4: 02 = 95 : 5のガスを
用い200 m I / s e c 、真空度0.5
T o r r 、出力100Wでドライエツチングし
た。Next, as shown in FIG. 2(f), the exposed polyimide 12 was exposed to a gas of CF 4:02 = 95:5 at a pressure of 200 mI/sec and a degree of vacuum of 0.5.
Dry etching was carried out at an output of 100 W.
感光性ポリイミド12をパターニングした後、第2図(
g)に示すように、TABテープを化学研磨、酸処理、
水洗し、レジスト13を両面塗布し、130℃、5分間
予備硬化させた。After patterning the photosensitive polyimide 12, as shown in FIG.
As shown in g), TAB tape is chemically polished, acid treated,
After washing with water, resist 13 was applied on both sides and precured at 130° C. for 5 minutes.
その後、第2図(h)に示すように、300m j /
c m 2で圧延銅箔3に密着している側のレジスト
13をコンタクト露光した。After that, as shown in Fig. 2 (h), 300 m j /
The resist 13 on the side in close contact with the rolled copper foil 3 was exposed to contact light at cm2.
引続き、第2図(i)に示すように、1%炭酸ソーダ水
溶液で現像し、水洗シャワーした。Subsequently, as shown in FIG. 2(i), the film was developed with a 1% aqueous solution of sodium carbonate and washed with water.
その後、第2図(j)に示すように、30%塩化第2鉄
で不要な圧延銅箔3をエツチング除去し、水洗シャワー
してリード14を形成した。Thereafter, as shown in FIG. 2(j), unnecessary rolled copper foil 3 was removed by etching with 30% ferric chloride, and leads 14 were formed by washing with water and showering.
最後に、第2図(k)に示すように、3%苛性ソーダ水
溶液で両面のレジストを剥離させ、水洗シャワーして所
望のTABテープを作成した。Finally, as shown in FIG. 2(k), the resist on both sides was removed with a 3% caustic soda aqueous solution, and the desired TAB tape was prepared by washing with water and showering.
一方、第1図に示すように、予めパッシベーション8が
表面にかかった半導体素子6のアルミ電極7上に、電解
めっき法で高さ15μmの金製突起電極9を形成した。On the other hand, as shown in FIG. 1, a protruding gold electrode 9 of 15 μm in height was formed by electrolytic plating on the aluminum electrode 7 of the semiconductor element 6 whose surface had been previously subjected to passivation 8 .
そこで、この金製突起電極つと、圧延銅箔3で出来たリ
ード4表面に、Sn : Pb=60 : 40の半田
を1μm付けたTABテープの接続位置とを粗位置合わ
せして、金製突起電極9をリード4のポリイミド5が除
去されている穴にはめ゛込み、250℃、2kg/cm
2.1秒の条件で熱圧着することにより、第1図に示す
ような半導体装置の構造を作った。Therefore, the gold protrusion electrode was roughly aligned with the connection position of the TAB tape with 1 μm of Sn:Pb=60:40 solder applied to the surface of the lead 4 made of the rolled copper foil 3, and the gold protrusion Insert the electrode 9 into the hole where the polyimide 5 of the lead 4 has been removed, and heat at 250°C and 2kg/cm.
A semiconductor device structure as shown in FIG. 1 was made by thermocompression bonding for 2.1 seconds.
なおこの時、加圧力を極端にあげても、ポリイミド4と
パッシベーション8で圧延銅箔3と半導体素子5の最小
間隔が規定され、かつ、応力も緩和されるため、金製突
起電極
うことはなく、またアルミ電極7下にクラックが発生す
ることもなかった。At this time, even if the pressing force is extremely increased, the minimum distance between the rolled copper foil 3 and the semiconductor element 5 is defined by the polyimide 4 and the passivation 8, and the stress is also alleviated, so it is not possible to use a protruding gold electrode. There was no occurrence of cracks under the aluminum electrode 7.
第3図は本発明の第2の実施例の断面図、第4図は第2
の実施例の実装基板への実装例の断面図である。FIG. 3 is a sectional view of the second embodiment of the present invention, and FIG. 4 is a sectional view of the second embodiment of the present invention.
FIG. 3 is a cross-sectional view of an example of mounting the embodiment on a mounting board.
第3図において、1は75μm厚のポリイドテープ、2
は接着剤、3は35μm厚の圧延銅箔で、3層構造のT
ABテープを形作っている。なお、圧延銅箔3で出来て
いるリード4は、1μm厚の共晶半田めっきが施されて
いる。5は5μm厚のポリイミドで、圧延銅箔3に密着
している。In Figure 3, 1 is a 75 μm thick polyide tape, 2
3 is an adhesive, 3 is a rolled copper foil with a thickness of 35 μm, and a 3-layer T
Forming AB tape. Note that the leads 4 made of rolled copper foil 3 are plated with 1 μm thick eutectic solder. 5 is polyimide with a thickness of 5 μm, and is in close contact with the rolled copper foil 3.
6は半導体素子で、その表面に接続用電極として1μm
厚のアルミ電極7が配置され、また、半導体素子6の保
護膜としてアルミ電[7以外の表面にパッシベーション
8が最大2μm厚でコートされている。更に、アルミ電
極7上に高さ15μmの半田製突起電極1つが形成され
ており、3層構造のTABテープ上の圧延銅箔3と電気
的並びに物理的に接続が取られている。6 is a semiconductor element with a 1 μm connection electrode on its surface.
A thick aluminum electrode 7 is arranged, and a passivation 8 is coated with a maximum thickness of 2 μm on the surface other than the aluminum electrode 7 as a protective film for the semiconductor element 6. Furthermore, one protruding solder electrode with a height of 15 μm is formed on the aluminum electrode 7, and is electrically and physically connected to the rolled copper foil 3 on the three-layer TAB tape.
なお、本実施例のポリイミド5は、半田製突起電極19
がはまり込むところ以外に、半導体素子6を実装基板1
5に実装するさい接続するリードの部分(以後OLB部
分と記す)17も除去されている。そこで第4図のよう
に、3層構造のTABの部分はまったく含まない、OL
B部分17の外周部で半導体装置を切り離し、OLB部
分17を使用して、半導体素子6を実装する実装基板1
5の導体パターン16に本実施例の半導体素子6を熱圧
着して、電気的並びに物理的に接続することが出来る。Note that the polyimide 5 of this example has solder protruding electrodes 19.
Place the semiconductor element 6 on the mounting board 1 other than where it fits.
The lead portion (hereinafter referred to as OLB portion) 17 that is connected to the OLB portion when mounted on the OLB portion 5 is also removed. Therefore, as shown in Figure 4, the OL
A mounting board 1 on which the semiconductor device is separated at the outer periphery of the B portion 17 and the semiconductor element 6 is mounted using the OLB portion 17.
The semiconductor element 6 of this embodiment can be thermocompression-bonded to the conductor pattern 16 of No. 5 for electrical and physical connection.
本実施例では、半導体素子6とTABテープの熱圧着の
際、温度を上げたり、時間を延ばしたりしても、アルミ
電極7の半田突起電極19がり−ド4上を流れ出したり
することがながったので、ポリイミド5が半田の流動防
止になるという利点がある。In this embodiment, even if the temperature is increased or the time is increased during thermocompression bonding of the semiconductor element 6 and the TAB tape, the solder protrusion electrodes 19 of the aluminum electrodes 7 will not flow out onto the solder wires 4. Therefore, polyimide 5 has the advantage of preventing solder from flowing.
また第4図のように、3層構造のTABを除いた状態で
半導体装置を実装基板15に実装すると、リード間の電
流リークの原因となる接着剤がなくなるため、TABを
用いた半導体装置の品質が向上するという利点もある。Furthermore, as shown in FIG. 4, if a semiconductor device is mounted on the mounting board 15 without the three-layer TAB, there will be no adhesive, which causes current leakage between the leads. There is also the advantage of improved quality.
以上説明したように本発明は、TABテープの0
デバイス孔中のリードが大部分有機被膜でサポートし、
かつ有機被膜の厚さは、半導体素子の電極上の突起電極
より薄くすることにより、リードの位置ずれ並びに変形
の発生を防き、かつ、リートと半導体素子間で短絡の発
生をも防ぎ、また、リードと半導体素子か適正な間隔を
保てるという効果もある。As explained above, in the present invention, most of the leads in the zero device holes of the TAB tape are supported by an organic film,
In addition, by making the thickness of the organic film thinner than the protruding electrodes on the electrodes of the semiconductor element, it is possible to prevent misalignment and deformation of the lead, and also to prevent short circuits between the lead and the semiconductor element. This also has the effect of maintaining an appropriate distance between the leads and the semiconductor element.
その上、半導体素子と接続されるリード部分近傍では接
続部分のみ有機被膜が除去されているため、半導体素子
の突起電極をはめ込むだけて位置合わせが済むという効
果もある。Furthermore, since the organic film is removed only at the connecting portion near the lead portion connected to the semiconductor element, there is an effect that alignment can be completed by simply fitting the protruding electrode of the semiconductor element.
また、半導体素子上も有機被膜が存在することにより、
半導体素子へのタメーシ防御の役割も果たすという効果
がある。In addition, due to the presence of an organic film on the semiconductor element,
It also has the effect of serving as a protection against damage to semiconductor devices.
そのほか、半導体素子の突起電極か半田の際は、有機被
膜か壁となることにより、半田のり−1〜側への流出を
防ぐという効果もある。In addition, when soldering a protruding electrode of a semiconductor element, the organic film acts as a wall and has the effect of preventing the solder paste from flowing to the -1~ side.
また、有機被膜の除去箇所が、半導体装置を実装する基
板と接続されるリード部分も除去した際は、半導体装置
を実装基板実装後にはTABテープの接着剤を含む箇所
が残らず、電流リークの問題がなくなるという効果もあ
る。In addition, if the organic film is also removed from the lead part that is connected to the board on which the semiconductor device is mounted, no part containing the adhesive of the TAB tape will remain after the semiconductor device is mounted on the board, which will prevent current leakage. It also has the effect of eliminating problems.
第1図は本発明の第1の実施例の断面図、第2図(a)
〜(1()は本発明の第1の実施例の製造方法を説明す
る工程順に示した断面図、第3図は本発明の第2の実施
例の断面図、第4図は第2の実施例の実装基板への実施
例の断面図である。
1・・・ポリイミドテープ、2・・・接着剤、3・・・
圧延銅箔、4.14・ リード、5・・・ポリイミド、
6・・・半導体素子、7・・・アルミ電極、8・・パッ
シベーション、9・・・金製突起電極、10・・・デバ
イス孔、11・感光性ポリイミド、12・・・感光済み
のポリイミド、13・・・レジスト、15・・・実装基
板、16・導体パターン、17・OL 8部分、]9・
・半田製突起電極。Fig. 1 is a sectional view of the first embodiment of the present invention, Fig. 2(a)
~(1() is a cross-sectional view showing the manufacturing method of the first embodiment of the present invention in the order of steps, FIG. 3 is a cross-sectional view of the second embodiment of the present invention, and FIG. 4 is a cross-sectional view of the second embodiment of the present invention. It is a sectional view of an example mounted on a board. 1... Polyimide tape, 2... Adhesive, 3...
Rolled copper foil, 4.14. Lead, 5... polyimide,
6... Semiconductor element, 7... Aluminum electrode, 8... Passivation, 9... Gold protruding electrode, 10... Device hole, 11... Photosensitive polyimide, 12... Photosensitive polyimide, 13...Resist, 15... Mounting board, 16. Conductor pattern, 17. OL 8 part, ]9.
・Solder protruding electrode.
Claims (1)
g)を用いた半導体装置の構造において、有機物で出来
たベーステープと、接着剤と、銅箔の3層構造からなる
TABテープで、半導体素子を接続させるため前記ベー
ステープと前記接着剤を貫いて開けられたデバイス孔中
に延在する、前記半導体素子と接続するために設けられ
た前記銅箔で作られたリードの、前記半導体素子と接続
される側の、前記半導体素子と接続される前記リード部
分を除いて、前記デバイス孔中全面に、前記半導体素子
の接続用電極部上に設けられた導電体の突起電極の突起
厚より薄い有機被膜が形成された前記TABテープの、
前記有機被膜が除去された前記リード部分と、前記半導
体素子とを、前記突起電極を介して接続したことを特徴
とする半導体装置の構造。 2、請求項1記載の半導体装置の構造において、前記デ
バイス孔中の前記有機被膜の除去箇所が、前記半導体素
子と接続される前記リード部分だけでなく、前記半導体
装置を実装する実装基板と接続される前記リード部分も
除去されたことを特徴とする半導体装置の構造。[Claims] 1. TAB (Tape Automated Bondin)
In the structure of a semiconductor device using g), a TAB tape consisting of a three-layer structure of a base tape made of an organic substance, an adhesive, and a copper foil is used to penetrate the base tape and the adhesive in order to connect semiconductor elements. A lead made of copper foil, which is provided to connect to the semiconductor element and extends into a device hole opened by the semiconductor element, is connected to the semiconductor element on the side to be connected to the semiconductor element. The TAB tape has an organic film thinner than a protrusion thickness of a protrusion electrode of a conductor provided on a connection electrode portion of the semiconductor element, which is formed on the entire surface of the device hole except for the lead portion;
A structure of a semiconductor device, characterized in that the lead portion from which the organic film has been removed and the semiconductor element are connected via the protruding electrode. 2. In the structure of the semiconductor device according to claim 1, the removed portion of the organic film in the device hole is connected not only to the lead portion connected to the semiconductor element but also to a mounting board on which the semiconductor device is mounted. A structure of a semiconductor device, characterized in that the lead portions that are connected are also removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016860A JPH03220740A (en) | 1990-01-25 | 1990-01-25 | Structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016860A JPH03220740A (en) | 1990-01-25 | 1990-01-25 | Structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03220740A true JPH03220740A (en) | 1991-09-27 |
Family
ID=11927973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016860A Pending JPH03220740A (en) | 1990-01-25 | 1990-01-25 | Structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03220740A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS647528A (en) * | 1987-06-30 | 1989-01-11 | Toshiba Corp | Manufacture of semiconductor device |
| JPH02215145A (en) * | 1989-02-16 | 1990-08-28 | Furukawa Electric Co Ltd:The | Manufacture of tape carrier |
| JPH0393247A (en) * | 1989-09-05 | 1991-04-18 | Nitto Denko Corp | Film carrier with bumps |
-
1990
- 1990-01-25 JP JP2016860A patent/JPH03220740A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS647528A (en) * | 1987-06-30 | 1989-01-11 | Toshiba Corp | Manufacture of semiconductor device |
| JPH02215145A (en) * | 1989-02-16 | 1990-08-28 | Furukawa Electric Co Ltd:The | Manufacture of tape carrier |
| JPH0393247A (en) * | 1989-09-05 | 1991-04-18 | Nitto Denko Corp | Film carrier with bumps |
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