JPS647528A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS647528A
JPS647528A JP62161049A JP16104987A JPS647528A JP S647528 A JPS647528 A JP S647528A JP 62161049 A JP62161049 A JP 62161049A JP 16104987 A JP16104987 A JP 16104987A JP S647528 A JPS647528 A JP S647528A
Authority
JP
Japan
Prior art keywords
patterns
lead
conductive layers
insulator
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62161049A
Other languages
Japanese (ja)
Inventor
Koji Yamakawa
Kaoru Koiwa
Nobuo Iwase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62161049A priority Critical patent/JPS647528A/en
Publication of JPS647528A publication Critical patent/JPS647528A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To facilitate the manufacture by a method wherein insulator patterns are formed on conductive layers on a substrate; multiple lead patterns are formed on the conductive layers exposed from the insulator patterns, and the insulator patterns and the lead patterns are peeled off from the conductive layers to form a lead carrier. CONSTITUTION:Insulator patterns 14 with lead pattern type openings are formed on conductive layers 12, 13 on a substrate 11 while lead patterns 15 are formed on the conductive layers 12, 13 exposed from the insulator patterns 14 by electroplating process using the conductive layers 12, 13 as common electrodes. Later, these insulator patterns 14 and the lead patterns 15 are peeled off from the conductive layers 12, 13 of the substrate 11. Thus, a lead carrier with the lead patterns 15 in narrow width and pitch can be easily manufactured. Furthermore, the manufactured lead carrier 16 is integrated comprising the insulator patterns 14 and the lead patterns 15 located on the same plane so that the lead patterns 15 may be prevented from bending and breaking due to deadweight or handling.
JP62161049A 1987-06-30 1987-06-30 Manufacture of semiconductor device Pending JPS647528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62161049A JPS647528A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62161049A JPS647528A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS647528A true JPS647528A (en) 1989-01-11

Family

ID=15727633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62161049A Pending JPS647528A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS647528A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03220740A (en) * 1990-01-25 1991-09-27 Nec Corp Structure of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03220740A (en) * 1990-01-25 1991-09-27 Nec Corp Structure of semiconductor device

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