JPH03220748A - Method of isolation of elements in semiconductor device - Google Patents
Method of isolation of elements in semiconductor deviceInfo
- Publication number
- JPH03220748A JPH03220748A JP1749790A JP1749790A JPH03220748A JP H03220748 A JPH03220748 A JP H03220748A JP 1749790 A JP1749790 A JP 1749790A JP 1749790 A JP1749790 A JP 1749790A JP H03220748 A JPH03220748 A JP H03220748A
- Authority
- JP
- Japan
- Prior art keywords
- region
- isolation
- element isolation
- semiconductor device
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造方法に関し、特にその素子
分離に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to element isolation thereof.
第2図(a)および第2図(b)は、従来の半導体装置
における素子分離方法を説明するための半導体装置の断
面図であり、1はシリコン基板、2はシリコン酸化膜、
3はポリシリコン膜、4はシリコン窒化膜、5は素子領
域部分、6はフォトレジスト、7は素子分離領域部分、
8は素子間寄生チャンネル防止用のイオン、9は素子分
離用のシリコン酸化膜、10はイオン拡散領域である。FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor device for explaining an element isolation method in a conventional semiconductor device, in which 1 is a silicon substrate, 2 is a silicon oxide film,
3 is a polysilicon film, 4 is a silicon nitride film, 5 is an element region portion, 6 is a photoresist, 7 is an element isolation region portion,
8 is an ion for preventing parasitic channels between elements, 9 is a silicon oxide film for element isolation, and 10 is an ion diffusion region.
まず、シリコン基板1上に下地の酸化薄膜であるシリコ
ン酸化膜2を形成し、その上にポリシリコン膜3及びシ
リコン窒化膜4を形成する。次いで素子領域部分5をフ
ォトレジスト6でマスクし、素子分離領域部分7のシリ
コン窒化膜4をエツチング除去する。次いで、シリコン
窒化膜4が除去された素子分離領域部分7に素子間寄生
チャネル防止用のイオン8を注入する。素子間寄生チャ
ネル防止用のイオン8には、たとえばボロンを用いる。First, a silicon oxide film 2 as a base oxide thin film is formed on a silicon substrate 1, and a polysilicon film 3 and a silicon nitride film 4 are formed thereon. Next, the element region portion 5 is masked with a photoresist 6, and the silicon nitride film 4 in the element isolation region portion 7 is removed by etching. Next, ions 8 for preventing inter-element parasitic channels are implanted into the element isolation region portion 7 from which the silicon nitride film 4 has been removed. For example, boron is used as the ions 8 for preventing parasitic channels between elements.
これは、半導体素子同士が電気的につながるのを防止す
るためのものである。This is to prevent the semiconductor elements from being electrically connected to each other.
その後、フォトレジスト6を除去し、素子領域部分5に
残っているシリコン窒化膜4をマスクとし、素子分離領
域部分7の下地ポリシリコン膜3を酸化して素子分離用
のシリコン酸化膜9を形戒する。Thereafter, the photoresist 6 is removed, and using the silicon nitride film 4 remaining in the element region portion 5 as a mask, the underlying polysilicon film 3 of the element isolation region portion 7 is oxidized to form a silicon oxide film 9 for element isolation. admonish.
次いで、シリコン窒化膜4を熱燐酸等でウェット処理し
除去した後、素子領域部分5のポリシリコン膜3をたと
えばフレオンガスのドライエツチングを用いて除去し、
さらに下地酸化薄膜2をたとえば10%0%フッ素水溶
液を用いてエツチング除去する。すると、素子領域部分
5のシリコン基板1が露出する。こうして素子分離が達
成される。Next, after removing the silicon nitride film 4 by wet processing with hot phosphoric acid or the like, the polysilicon film 3 in the element region 5 is removed using, for example, dry etching using Freon gas.
Furthermore, the base oxide thin film 2 is removed by etching using, for example, a 10% 0% fluorine aqueous solution. Then, the silicon substrate 1 in the element region portion 5 is exposed. In this way, element isolation is achieved.
しかしながら、従来の素子分離方法においては、素子分
離領域部分7でのシリコン酸化膜9の形成時に、イオン
8が拡散し、イオン拡散領域10が形成される。このよ
うな状態で、たとえばトランジスタを形威した場合、ト
ランジスタの幅がこのイオン拡散領域10により制限さ
れてしまうという問題がある。However, in the conventional device isolation method, when forming the silicon oxide film 9 in the device isolation region portion 7, the ions 8 are diffused and the ion diffusion region 10 is formed. If, for example, a transistor is formed in such a state, there is a problem in that the width of the transistor is limited by the ion diffusion region 10.
この発明は上記のような問題点を解決するためになされ
たもので、イオン拡散領域の拡がりを抑えることができ
る半導体装置における素子分離方法を提供することを目
的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a device isolation method in a semiconductor device that can suppress the spread of an ion diffusion region.
本発明に係る半導体装置における素子分離方法は、イオ
ン拡散領域をフォトマスクを用いて、その寸法をあらか
しめ縮小しておき、イオン注入後に素子分離領域部分を
拡大するようにしたものである。In the element isolation method in a semiconductor device according to the present invention, the dimensions of the ion diffusion region are preliminarily reduced using a photomask, and the element isolation region portion is expanded after ion implantation.
この発明においては、イオン拡散領域をフォトマスクを
用い、その寸法をあらかじめ縮小しておき、イオン注入
後に素子分離領域部分を拡大するようにしたので、イオ
ン拡散領域の幅が縮小される効果がある。In this invention, the dimensions of the ion diffusion region are reduced in advance using a photomask, and the element isolation region is expanded after ion implantation, which has the effect of reducing the width of the ion diffusion region. .
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図(a)ないしくC)はこの発明の一実施例による
半導体装置における素子分離方法を示す断面図であり、
図において、第2図と同一符号は同一または相当部分を
示し、11はフォトマスク、12は素子分離幅拡大領域
である。FIGS. 1(a) to 1C) are cross-sectional views showing an element isolation method in a semiconductor device according to an embodiment of the present invention,
In the figure, the same reference numerals as in FIG. 2 indicate the same or corresponding parts, 11 is a photomask, and 12 is an element isolation width enlarged region.
まず、シリコン基板1上に下地の酸化薄膜であるシリコ
ン酸化薄膜2を形威し、その上にポリシリコン膜3、シ
リコン窒化膜4を形成する(各工程は図示せず)。First, a silicon oxide thin film 2, which is a base oxide thin film, is formed on a silicon substrate 1, and a polysilicon film 3 and a silicon nitride film 4 are formed thereon (each step is not shown).
次いで、素子領域部分5をフォトレジスト6でマスクし
、素子分離領域部分7の窒化膜4をエツチング除去する
。この際、イオン拡散領域10の拡がりを考慮し、フォ
トマスク11を用い素子分離領域部分7の寸法を縮小す
る(第1図(a))。Next, the element region portion 5 is masked with a photoresist 6, and the nitride film 4 in the element isolation region portion 7 is removed by etching. At this time, taking into consideration the expansion of the ion diffusion region 10, the dimensions of the element isolation region portion 7 are reduced using a photomask 11 (FIG. 1(a)).
次いで、シリコン窒化膜4が除去された素子分離領域部
分7に素子間寄生チャネル防止用のイオン8を注入する
。Next, ions 8 for preventing inter-element parasitic channels are implanted into the element isolation region portion 7 from which the silicon nitride film 4 has been removed.
そして、この後、フォトレジスト6をマスクとし、フレ
オンガス等による等方性エツチングにより、シリコン窒
化膜4をエツチングし、素子分離幅拡大領域12を形成
する(第1図(b))。Then, using the photoresist 6 as a mask, the silicon nitride film 4 is etched by isotropic etching using Freon gas or the like to form an element isolation width enlarged region 12 (FIG. 1(b)).
その後、フォトレジスト6を除去しく工程図示せず)、
素子領域部分5に残っているシリコン窒化膜6をマスク
とし、素子分離領域部分7の下地ポリシリコン3を酸化
して素子分離用のシリコン酸化膜9を形成する(第1図
(C))。After that, the photoresist 6 is removed (process diagram not shown),
Using the silicon nitride film 6 remaining in the element region portion 5 as a mask, the underlying polysilicon 3 in the element isolation region portion 7 is oxidized to form a silicon oxide film 9 for element isolation (FIG. 1(C)).
このように本実施例による、半導体装置における素子分
離方法によれば、イオン拡散領域10をフォトマスク1
1を用い、その寸法をあらかじめ縮小しておき、イオン
8を注入した後に素子分離領域部分7を拡大するように
したので、イオン拡散領域10の幅を縮小できる。As described above, according to the element isolation method in a semiconductor device according to this embodiment, the ion diffusion region 10 is connected to the photomask 1.
1, its dimensions are reduced in advance, and the element isolation region portion 7 is expanded after the ions 8 are implanted, so that the width of the ion diffusion region 10 can be reduced.
以上のように、この発明に係る半導体装置における素子
分離方法によれば、イオン注入前に、フォトマスクを用
いて素子分離領域部分を制限し、その後、素子分離領域
部分をエツチングし、拡大するようにしたので、素子分
離用のシリコン酸化膜は従来と同一寸法であっても、イ
オン拡散領域が縮小された半導体装置を得ることができ
るという効果がある。As described above, according to the device isolation method in a semiconductor device according to the present invention, before ion implantation, the device isolation region is limited using a photomask, and then the device isolation region is etched and expanded. Therefore, even if the silicon oxide film for element isolation has the same dimensions as the conventional one, it is possible to obtain a semiconductor device in which the ion diffusion region is reduced.
第1図(a)ないしくC)はこの発明の一実施例を説明
するための半導体装置の断面図、第2図(a)及び(b
)は従来の半導体装置における素子分離方法を説明する
ための断面図である。
図において、1はシリコン基板、2はシリコン酸化膜、
3はポリシリコン膜、4はシリコン窒化膜、5は素子領
域部分、6はフォトレジスト、7は素子分離領域部分、
8は素子間寄生チャネル防止用イオン、9は素子分離用
シリコン酸化膜、10はイオン拡散領域、11はフォト
マスク、12は素子分離巾拡大領域である。
なお図中同一符号は同−又は相当部分を示す。1(a) to 1C) are cross-sectional views of a semiconductor device for explaining one embodiment of the present invention, and FIGS. 2(a) to 2(b)
) is a cross-sectional view for explaining an element isolation method in a conventional semiconductor device. In the figure, 1 is a silicon substrate, 2 is a silicon oxide film,
3 is a polysilicon film, 4 is a silicon nitride film, 5 is an element region portion, 6 is a photoresist, 7 is an element isolation region portion,
Reference numeral 8 designates ions for preventing parasitic channels between elements, 9 a silicon oxide film for element isolation, 10 an ion diffusion region, 11 a photomask, and 12 an element isolation width expansion region. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
フォトマスクにより縮小されたエッチング領域にアイソ
レーション注入し、 その後、窒化膜の開口部が設計寸法になるまで等方性エ
ッチングを行うことにより、 フィールド酸化膜の分離巾とアイソレーションの分離巾
とを一致させるようにしたことを特徴とする半導体装置
における素子分離方法。(1) In an element isolation method for semiconductor devices, field oxidation is achieved by injecting isolation into an etched region that has been reduced in advance using a photomask, and then performing isotropic etching until the opening in the nitride film reaches the designed dimensions. A method for isolating elements in a semiconductor device, characterized in that a separation width of a membrane and an isolation width are made to match.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1749790A JPH03220748A (en) | 1990-01-25 | 1990-01-25 | Method of isolation of elements in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1749790A JPH03220748A (en) | 1990-01-25 | 1990-01-25 | Method of isolation of elements in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03220748A true JPH03220748A (en) | 1991-09-27 |
Family
ID=11945634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1749790A Pending JPH03220748A (en) | 1990-01-25 | 1990-01-25 | Method of isolation of elements in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03220748A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7687367B2 (en) | 2005-02-04 | 2010-03-30 | Yamaha Corporation | Manufacture method for semiconductor device having field oxide film |
-
1990
- 1990-01-25 JP JP1749790A patent/JPH03220748A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7687367B2 (en) | 2005-02-04 | 2010-03-30 | Yamaha Corporation | Manufacture method for semiconductor device having field oxide film |
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