JPH03220914A - Delay circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit constitution and to attain the setting of a long delay period by acquiring an output signal whose fall is retarded with respect to an input signal given to the gates of respective MOSFETs of 1st and 2nd complementary circuits from a series connection point of the 2nd complementary circuit. CONSTITUTION:An output signal whose fall is retarded with respect to an input signal given to the gates of respective MOSFETs of the 1st and 2nd complementary circuits 11, 12 is obtained from a series connection point of the 2nd complementary circuit 12. That is, since the drain potential of an N- channel MOSFET 12N of the complementary circuit 12 is slowly lowered after the N-channel MOSFET 11N of the 1st complementary circuit 11 is turned on, the turning-on of the N-channel MOSFET 12N of the 2nd complementary circuit 12 is delayed and the fall of an output signal with respect to an input signal is delayed. Thus, the circuit constitution of the delay circuit is reduced and a further longer delay period can be set.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a delay circuit that delays one or both of the rise and fall of a signal.

(Example) Conventional technology Delay circuits with complementary MOS inverter configurations are widely used to delay various signals in semiconductor integrated circuits such as one-chip microcomputers and memories.Delay circuits with inverter configurations It is formed by connecting multiple stages of inverters each having a delay period as necessary, and the delay period of the entire delay circuit is variably set depending on the number of inverters connected in series.In addition, the inverter and other circuits, For example, N.

By combining with an R circuit or the like, it is also possible to construct a structure in which only one of the rising and falling edges of a signal is delayed.

FIG. 5 is a diagram showing an example of a delay circuit that delays the fall of a signal, and FIG. 6 is a waveform diagram of its input signal and output signal.

The input signal A is input directly to one input of the NOR gate (1), and is also input to the other input of the NOR gate (1) via an even number of stages (two stages in the figure) of inverters (2a) (2b). Then, the output of the NOR gate (1) is output as the output signal B via the inverter (3). ``LJ is inverted to low level, and conversely, from the falling edge of input signal A, inverter (2a)
After a delay of 1° according to (2b), r L is reversed to 'HJ. That is, when the input signal A falls, even if one of the inputs of the NOR gate (1) becomes r L , the other input is delayed by the delay period 2. Take remains at "rH", and the NOR gate (1>
Since Bit is not inverted immediately but is inverted after a delay period e from the timing of the fall of the input signal A, only the timing of the fall of the output signal Bit is delayed with respect to the output signal A. However, regarding the timing of the rise of output signal B, the NOR gate (1) and inverter (
3), but it is ignored here.

FIG. 7 is a diagram showing an example of a delay circuit that delays the rising timing of a signal, and FIG. 8 is a waveform diagram of its input signal and output signal.

One P-channel type MOS FET (4P) and three N-channel type MOS FET (4N+ >
<4Nt><4N1> are connected in series between the power source and ground to form a first inverting circuit (4), and input signal A is commonly applied to each gate. In addition, three P-channel type M
O3F E T (5P+) (5P*) (5Fg) and 1
Two N-channel type MOSFETs (5N) are connected in series between the power supply and ground to form a second inverting circuit (5), and each gate is connected in common to a P-channel type MOSFET (4N).
P) and N-channel type MOS FET (4N+
) is connected to the connection point. Then, an output signal B is output from the connection point between the P channel type MOS FET (5Ps) and the Nf channel type MOS FET (5N).
is obtained. In such a delay circuit, when the input signal A rises, the P-channel type MOS FET
The connection point between (4F) and N-channel MOSFET (4N, ), that is, MOS FET (SP+) (5Pffi
) (5PJ ) and (5'N On the other hand, when the input signal A falls, the potential V quickly rises and the second inverting circuit
5> is inverted, there is a slight delay in the fall of the output signal B with respect to the fall of the input signal A. That is, the N-channel type MOSFET of the first inverting circuit <4)
(4N,) (4N, ) (4NA) and the second inverting circuit (
5> P channel type MOSFET (5P, ) (5
Pl ) (5Ps ) are connected in series, and when turning on from an off state, the whole will not turn on unless all MOSFETs are turned on, whereas when turning off from an on state, any one of the MOSFETs will turn on. If you turn it off, the whole thing is off. Therefore, N-channel type MO8FET (4Nl) (4Nm >
(4Nj) are turned on in sequence, and P-channel type M
OS FET (5P+) (5P*) (5Ps)
At the rising edge of input signal A, which turns on sequentially, the first
The inverting operations of the second inverting circuits (4) and (5) are delayed, and the rise of the output signal B is delayed by a period of time (, 1, 2,
)(4N, ) are turned off in turn, and the P-channel type MOS FET (SP, )(5Pt) (5P-
) turns off in turn at the falling edge of the input signal A, the delay in the inverting operation of the first and second inverting circuits (4) and (5) is slight, and the falling edge of the output signal B with respect to the input signal A is delayed. There are almost no delays.

<C> Problems to be solved by the invention However, the above-mentioned delay circuits all have a large number of MOSFETs making up the circuit, and therefore occupy a large area when integrated on a semiconductor chip, making it difficult to achieve high integration. It has problems that hinder it. In particular, when setting a long delay period, increase the number of innocutors (2a) and (2b) (fifth
), an increase in the number of P-channel type MOSFETs (5P), and N-channel type MOSFETs (5N) (7th
(Fig.) is required, and the area occupied on the semiconductor chip/nob increases as the circuit configuration increases.

Therefore, an object of the present invention is to reduce the circuit configuration of a delay circuit and to enable setting of a longer delay period.

(d) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and the first feature is that the P-channel MOS
A first complementary circuit in which a FET and an N-channel MOSFET are connected in series between a t source and ground, and a P-channel MOSFET and an N-channel MOSFET are connected in series between a power source and the first complementary circuit. a second complementary type circuit connected in series between the series connection point of the first and second complementary type circuits; The purpose is to obtain an output signal at a series connection point of the second complementary circuit.

The second feature is that the first complementary circuit includes a P-channel type MOSFET and an N-channel type MOSFET connected in series between the power supply and the ground;
P-channel MOSFET and N-channel MOSFET
SFET is connected in series between the series connection point of the first complementary circuit and ground, and the gate of each MO3FET of the first and second complementary circuits The purpose is to obtain an output signal whose rise is delayed with respect to an applied input signal at the series connection point of the second complementary circuit.

Furthermore, the third feature is that the P-channel type M
first and second complementary circuits in which an OSFET and an N-channel MOSFET are connected in series between a power supply and a ground, respectively; a third complementary circuit connected in series between a series connection point of the complementary circuit and a series connection point of the second complementary circuit; each MOSFET of the first to third complementary circuits; The object of the present invention is to obtain an output signal whose fall and rise are delayed with respect to an input signal applied to the third complementary circuit at the series connection point of the third complementary circuit.

(*) Effect According to the first means of the present invention, after the N-channel MOSFET of the first complementary circuit is turned on, the drain potential of the N-channel MOSFET of the second complementary circuit slowly increases. Because of this, the turn-on of the N-channel MOSFET of the second complementary circuit is delayed, and the fall of the output signal with respect to the input signal is delayed.

According to the second means, since the potential of the drain of the Pfw channel MOSFET of the first complementary circuit is slowly raised after the P channel MOSFET of the first complementary circuit is turned on, The turn-on of the P-channel MOSFET of the second complementary circuit is delayed, and the rise of the output signal relative to the input signal is delayed.

The combination of the first means and the second means sets the rise and fall of the output signal to be delayed with respect to the input signal.

(to) Example Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, in which the fall of a signal is delayed.

A P-channel type MOSFET (IIP) and an N-channel type MO3FET (IIN) are connected in series between a power source and ground to form a first complementary inversion circuit (11). In this first complementary inverting circuit (11), the mutual fundductance β of the N-channel type MOSFET (IIN) on the ground side is formed small, and the driving capacity is set low, and the P-channel type on the power side Type MO8FE T
The mutual conductance β of (IIP) is formed to be large, and the driving capability is set high. Specifically, mutual conductance β8. β is each MOSFET (11P)
Since it is proportional to the gate width of (11N) and inversely proportional to the gate length, the gate length of N-channel type MOSFET (IIN>) is long, and the gate length of P-channel type MOSFET (
IIP) gate length is set short.

Further, a P-channel type MO3FET (12P) and an N-channel type MOSFET (12N) are connected in series between the power supply and the output of the first complementary type inverting circuit (11). An inverting circuit (12) is configured.

Then, the first and second complementary inverting circuits (11) (12
) MOS FET (IIP) (IIN) (1
Input signal A is supplied to each gate of 2P) (12N) via an inverter (10), and the input signal A is supplied to each gate of the second complementary inverting circuit (12N).
2) output, that is, P channel type MOS FET
(12P) and N-channel type MOS FET (1
Output signal B is obtained from the connection point with 2N).

When the input signal A rises, the output of the inverter (1o) is inverted from rH to "L", and each MO5FET
(IIP>(IIN) (12P) (12N) (7) The gate potential v6 is lowered. When the potential V starts to drop, the P-channel type M, which has been in the off state until then, first
O8F E T (IIP) (IIN) turns on and the first
The output potentials V, , V of the second complementary inverting circuits (11) and (12) begin to rise, and then the N-channel MOSFETs (11N) (12N) have a negative potential V,
, V, is pulled up to the power supply potential. At this time, the potential V, which is the source potential of the N-channel type MOS FET (12N), is the potential of the N-channel type MOS FET (12N).
(11N) P-channel type M with larger driving capacity compared to
Since the voltage is quickly raised by the OS FET (LIP), the N-channel MOSFET (12N) immediately turns off, and the potential Vl rises without much delay from the inversion of the inverter (10).

On the other hand, when the input signal A falls, the inverter (lO)
The output of is inverted from "rL" to "1H", and the potential vG is raised. When the potential v6 starts to rise, the N-channel MOSFET (IIN) (1
2N), the on-site potential V, , V, begins to be lowered.

However, N-channel MOS FET (IIN>
Since the driving capacity is smaller than that of a P-channel MOS FET (IIP), the potential V slowly decreases,
As a result, the fall of the potential V is delayed. Therefore,
When input signal A rises, output signal B rises almost simultaneously, and when input signal A falls, output signal B rises.
falls with a delay of a predetermined period, and only the fall of the signal can be delayed as in FIG.

FIG. 2 is a diagram showing another embodiment of the present invention, in which the rise of a signal is delayed.

A P-channel type MOSFET (13P) and an N-channel type MO3FET (13N) are connected in series between the power source and ground to constitute a first complementary inverting circuit <13>. In this first complementary inverting circuit (13), the mutual fundductance βP of the P-channel MOSFET (13F) on the power supply side is formed small and the drive capability is set low, and the N-channel MOSFET (13F) on the ground side 13N)
The mutual conductance β8 is formed to be large, and the driving capability is set high. In addition, P channel type MOS F
ET (14P) and N-channel type MO3F ET
(14N) are connected in series between the output of the first complementary inverting circuit (13) and the ground, and the second complementary inverting circuit (13) is connected in series between the output of the first complementary inverting circuit (13) and the ground.
14) is configured, and MOSFETs (13P) (13
N) (14P) (14N>) Inverter (1
0), the input signal A is supplied via the second complementary MO
Output signal B is obtained from the output of 5FET (14).

When the input signal A rises, the output of the inverter (10) is inverted from rH, to rL, and each MO5FE T
(13P) (13N) (14P) (14N) (7) The potential vG is lowered. Potential V. When the current starts to drop, the P-channel MO, which was in the off state until then,
S F ET (13F) (14P) is on-site potential V
,,V, starts to be pulled up. However, P-channel type MOSFET (13P) is replaced by N-channel type MO3F.
Since the driving ability is smaller than that of ET (13N>), the potential V
1 is delayed, and accordingly, the rise of the potential V is delayed.

On the other hand, when the input signal A falls, the inverter (10
) is inverted from 1L to rH, and the potential Vc is raised. This potential V. When the is pulled up, the N-channel type MOS FET (which was in the off state until then)
13N) (14N), the on-site potential V,, V, begins to be lowered, and then the P-channel type MO8FE T (1
3P) (14F) is turned off and the potentials V, , V, are lowered to the ground potential VSS. At this time, N channel type M
The driving capacity of O3FET (13N) is P-channel type MO
The potential V is larger than the drive capability of SFET (13P).
, starts up quickly, and immediately turns into a P-channel type MOS.
F E T (13F) (14P) -7L, potential V.

rises without much delay from the inversion of the inverter (10). Therefore, when the input signal A rises, the output signal B rises with a delay of a predetermined period, and when the input signal A falls, the output signal B falls almost simultaneously, similar to FIG. Only the rising edge of the signal can be delayed.

FIG. 3 is a diagram showing a third embodiment of the present invention, in which the rise and fall of a signal are delayed, and FIG. 4 is a waveform diagram of the input signal and output signal.

P channel type MOS FET (15P) (1
6P) and N-channel type MOS FET (15
N) (16N) are connected in series between the power source and ground to form first and second complementary inverting circuits (Is) (16). These first and second complementary inversion circuits (15) (16)
is the first complementary inverting circuit (1) shown in FIGS. 2 and 1.
3) Each has the same configuration as (11), and the P-channel type MOS FET (
15P) and the N-channel type MOS FET (16N) of the second complementary inverting circuit (16) are formed to have small mutual conductance, and the mutual conductance of the first complementary inverting circuit (16) is small.
15) N-channel type MO5FET (15N)
and a second complementary inversion circuit (16〉 P-channel type M
The mutual conductance of OS FET (16P) is formed to be large. In addition, the first complementary inverting circuit (15
A P-channel type MOSFET (17P) and an N-channel type MOSFET (17N) are connected in series between the output of > and the output of the second complementary type inverting circuit (16) to form a third complementary type inverting circuit. (17) is formed.Then, the first to third complementary inversion circuits (15) (16) (17)
MOS FET (15P>(15N)(16
Input signal A is supplied to each gate of F) (16N) (17P) (17N) via an inverter (10), and output signal B is obtained from the output of the third complementary inverting circuit (17).

This delay circuit is configured to delay the rise and fall of a signal by a combination of the delay circuit shown in FIG. 1 and the delay circuit shown in FIG. The third complementary inverting circuit (17) operates according to the output of the first complementary inverting circuit (15), and at the falling edge of the input signal A, the second complementary inverting circuit (16) operates according to the output of the first complementary inverting circuit (15).
operates according to the output of That is, at the rise of the input signal A, the potential v1 on the output side of the first complementary inverting circuit (15) rises slowly, and the P-channel type M of the third complementary inverting circuit (17) OSFET(17
P) is delayed and the third complementary inverting circuit (17
), the rise of the potential V on the output side is delayed. Conversely, at the falling edge of input signal A, the second complementary inverting circuit (1
The fall of the potential V on the output side of 6> becomes gradual, and the third complementary inverting circuit (N-channel type MO3FE of 16>
The turning on of T (16N) is delayed, and the fall of the potential V is delayed. Therefore, as shown in FIG. 4, the output signal B rises and falls for a predetermined period Q, ! with respect to the input signal A, respectively. , I'm late.

According to the above configuration, the rising or falling of the signal,
or both can be delayed by a predetermined period of time. Moreover, the delay period is the P of each complementary inversion circuit.
Chisennel type MOSFET and N-channel type MOSFET
It is determined by the mutual conductance with T, that is, the transistor size. For example, in the delay circuit of FIG. 3, the P-channel MOSFET of the first complementary inverting circuit (15)
By increasing the channel length of the ET (15P) and the N-channel MO3FET (16N) of the second complementary inversion circuit (16), the delay of the output signal B with respect to the input signal A (period ffi, l!, ) can be made longer.

In this embodiment, an inverter is provided on the input side of the delay circuit to make the output signal have the same phase as the input signal, but the output signal has the opposite phase to the input signal. It can also be configured as follows.

(G) Effects of the Invention According to the present invention, a delay circuit capable of delaying the rise or fall of a signal can be configured with a small number of elements, so the circuit scale can be reduced and it can be integrated on a semiconductor chip. This reduces the area occupied when integrated, making it effective for high integration.

In addition, even if the delay period is to be lengthened, it can be achieved by changing the size of the MOSFET that determines the delay period, and since there is no need to increase the number of elements that make up the circuit, specifically the number of MOSFETs, the circuit size can be increased. There is no such thing as an increase in .

[Brief explanation of drawings]

1 to 4 relate to the delay circuit of the present invention; FIG. 1 shows one embodiment, FIG. 2 shows another embodiment, and FIG. 3 shows a third embodiment. , FIG. 4 is a waveform diagram of the input signal and output signal of FIG. 3. FIG. 5 is a diagram showing an example of a conventional delay circuit, FIG. 6 is a waveform diagram of the input signal and output signal of FIG. 5, and FIG. 7 is a diagram showing another example of the conventional delay circuit.
FIG. 8 is a waveform diagram of the input signal and output signal of FIG. 7. (10)...Inverter, (11)-(17)...
・Complementary inversion circuit, (IIP) ~ (17F>...P
f + channel type MO3FET, (IIN) ~ (1
7N>-N f Jannel type MOSFET.

Claims (6)

[Claims] (1) A first complementary circuit in which a P-channel MOSFET and an N-channel MOSFET are connected in series between the power supply and the ground; a P-channel MOSFET and an N-channel MOSFET;
a second complementary circuit in which the SFET is connected in series between the power supply and the series connection point of the first complementary circuit; each MOSFE of the first and second complementary circuits;
A delay circuit characterized in that an output signal whose fall is delayed with respect to an input signal applied to a gate of T is obtained at a series connection point of the second complementary circuit. (2) The first complementary circuit is a P-channel type MO
MO whose SFET transconductance is N-channel type
2. The delay circuit according to claim 1, wherein the delay circuit is set to be larger than the mutual conductance of the SFET. (3) A first complementary circuit in which a P-channel MOSFET and an N-channel MOSFET are connected in series between a power supply and ground; a P-channel MOSFET and an N-channel MOSFET;
a second complementary circuit in which the SFET is connected in series between the series connection point of the first complementary circuit and the ground, each MOSFE of the first and second complementary circuits
A delay circuit characterized in that an output signal whose rise is delayed with respect to an input signal applied to a gate of T is obtained at a series connection point of the second complementary circuit. (4) The first complementary circuit is an N-channel MO
MO whose SFET transconductance is P-channel type
4. The delay circuit according to claim 3, wherein the delay circuit is set to be larger than the mutual conductance of the SFET. (5) First and second complementary circuits in which a P-channel MOSFET and an N-channel MOSFET are connected in series between a power supply and a ground, respectively, and a P-channel MOSFET.
SFET and N-channel MOSFET are the first
a third complementary circuit connected in series between the series connection point of the complementary circuit and the series connection point of the second complementary circuit, each of the first to third complementary circuits MOSFE
A delay circuit characterized in that an output signal whose fall and rise are delayed with respect to an input signal applied to a gate of T is obtained at a series connection point of the third complementary circuit. (6) The first complementary circuit is an N-channel MO
MO whose SFET transconductance is P-channel type
The mutual conductance of the P-channel MOSFET is set to be larger than that of the SFET, and the second complementary circuit also sets the mutual conductance of the P-channel MOSFET to be larger than that of the N-channel MOSFET. 6. The delay circuit according to claim 5.