JPH03220916A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH03220916A JPH03220916A JP1674090A JP1674090A JPH03220916A JP H03220916 A JPH03220916 A JP H03220916A JP 1674090 A JP1674090 A JP 1674090A JP 1674090 A JP1674090 A JP 1674090A JP H03220916 A JPH03220916 A JP H03220916A
- Authority
- JP
- Japan
- Prior art keywords
- converter
- circuit
- signal
- semiconductor integrated
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
[v1要]
相補型MOSデバイスとD/A変換器の動作を制御でき
る半導体集積回路に関し、
相補型MOSデバイスとD/A変換器とを接続している
半導体集積回路において、D/A変換器部分の変換動作
停止とその解除とを制御回路を挿入して簡易確実に制御
できる半導体集積回路を提供することを目的とし、
相補型MOSデバイスに接続されたD/A変換器の動作
を制御する半導体集積回路において、制御信号により電
流通過を制御する回路を、前記トランジスタとD/A変
換器との間、またはD/A変換器内部に挿入したことで
構成する。[Detailed description of the invention] [v1 required] Regarding a semiconductor integrated circuit that can control the operation of a complementary MOS device and a D/A converter, a semiconductor integrated circuit that connects the complementary MOS device and the D/A converter. The purpose of the present invention is to provide a semiconductor integrated circuit that can simply and reliably control the stopping and canceling of the conversion operation of the D/A converter section by inserting a control circuit, In a semiconductor integrated circuit that controls the operation of a converter, a circuit that controls current passage using a control signal is inserted between the transistor and the D/A converter or inside the D/A converter.
[産業上の利用分野コ
本発明は相補型MOSデバイスとD/A変換器の動作を
制御できる半導体集積回路に関する。[Industrial Field of Application] The present invention relates to a semiconductor integrated circuit that can control the operations of complementary MOS devices and D/A converters.
従来、相補型MOSデバイスとD/A変換器とを接続し
ている回路において、D/A変換器の動作を停止させる
ときは、相補型MO3)ランジスタの入力側から動作停
止用信号を印加する必要があった。簡易確実にD/A変
換器を動作させないように回路構成を得ることが要望さ
れた。Conventionally, in a circuit that connects a complementary MOS device and a D/A converter, when stopping the operation of the D/A converter, an operation stop signal is applied from the input side of the complementary MO3) transistor. There was a need. It was desired to obtain a circuit configuration that would simply and reliably prevent the D/A converter from operating.
し従来の技術] 第6図は従来のC−MO3回路を示す図である。[Conventional technology] FIG. 6 is a diagram showing a conventional C-MO3 circuit.
第6図において、1は抵抗値R,2Rの素子をラダー型
(梯子型)に接続した公知のD/A変換器、2−0〜2
−nはディジタル信号D0〜Dnの印加端子、3−0〜
3−nは2段構成のC−MO3型インバータ、4はアナ
ログ信号出力端子を示す。ディジタル信号印加端子2に
nビットのディジタル信号を印加し、インバータ3をデ
ィジタル信号の“H″レベル応して導通状態にすれば、
抵抗素子を流れる電流が変化するというD/A変換器1
により、アナログ値に変換された出力を端子4から取り
出すことが出来る。In FIG. 6, 1 is a known D/A converter in which elements with resistance values R and 2R are connected in a ladder type, and 2-0 to 2
-n is an application terminal for digital signals D0 to Dn, 3-0 to
3-n is a two-stage C-MO3 type inverter, and 4 is an analog signal output terminal. If an n-bit digital signal is applied to the digital signal application terminal 2 and the inverter 3 is made conductive in response to the "H" level of the digital signal,
D/A converter 1 in which the current flowing through the resistance element changes
As a result, the output converted to an analog value can be taken out from the terminal 4.
2−〇〜2−nと示すディジタル信号印加端子D0〜D
nにIt L wまたは“H”の信号を印加させたとき
に限り、変換したアナログ信号の出力が安定化されてい
る。またインバータ3を含みC−MOS製造技術により
、これら回路を他の回路を含めて同一基板上に形成させ
出荷する場合がある。その場合、D/A変換器が通常に
動作している時のインバータ部分の電源VDD+ vs
sからの電流を測定して回路の良否判断の資料としてい
る。Digital signal application terminals D0 to D indicated as 2-〇 to 2-n
The output of the converted analog signal is stabilized only when an It L w or "H" signal is applied to n. Further, these circuits including the inverter 3 may be formed on the same substrate along with other circuits using C-MOS manufacturing technology and shipped. In that case, the power supply VDD+ of the inverter section when the D/A converter is operating normally
The current from s is measured and used as data for determining the quality of the circuit.
今、端子りに“H”が印加され安定状態となったとき、
インバータ3の第2段の上側PチャネルFETが導通し
、VDDから接地への電流が流れる。Now, when "H" is applied to the terminal and the state is stable,
The upper P-channel FET of the second stage of inverter 3 becomes conductive, and current flows from VDD to ground.
次に端子りに“L”が印加され安定状態となったとき、
インバータ3の第2段のNチャネルFETが導通する。Next, when "L" is applied to the terminal and the state becomes stable,
The second stage N-channel FET of inverter 3 becomes conductive.
[発明が解決しようとする課題]
第6図に示す回路では電力低下をさせたときの電流測定
のためには、ディジタル信号印加端子2に“L”信号を
与える必要があるから、端子2の前段に他の回路が存在
すると、端子ピンに“L”信号を与えるのみでは信号が
安定化出来ず、そのままでは測定が出来なかった。[Problems to be Solved by the Invention] In the circuit shown in FIG. 6, it is necessary to apply an "L" signal to the digital signal application terminal 2 in order to measure the current when the power is reduced. If other circuits were present in the preceding stage, the signal could not be stabilized simply by applying an "L" signal to the terminal pin, and measurement could not be performed as it was.
本発明の目的は前述の欠点を改善し、相補型MOSデバ
イスとD/A変換器とを接続している半導体集積回路に
おいて、D/A変換器部分の変換動作停止と解除とを制
御回路を挿入して簡易確実に制御できる半導体集積回路
を提供することにある。An object of the present invention is to improve the above-mentioned drawbacks, and to provide a control circuit for stopping and canceling the conversion operation of the D/A converter in a semiconductor integrated circuit that connects a complementary MOS device and a D/A converter. It is an object of the present invention to provide a semiconductor integrated circuit that can be inserted and controlled simply and reliably.
[課題を解決するための手段]
第1図は本発明の原理構成を示す図である。第1図にお
いて、1はD/A変換器、2−0〜2−nはディジタル
信号D0〜Dnの印加端子、3−0〜3−nは相補型M
OSデバイス、4はアナログ信号出力端子、5は電流通
過を制御する回路、6は制御信号印加端子を示す。[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of the present invention. In FIG. 1, 1 is a D/A converter, 2-0 to 2-n are application terminals for digital signals D0 to Dn, and 3-0 to 3-n are complementary M
In the OS device, 4 is an analog signal output terminal, 5 is a circuit for controlling current passage, and 6 is a control signal application terminal.
相補型MO3型デバイス3に接続されたD/A変換変換
器内作を制御する半導体集積回路において、本発明は下
記の構成とする。即ち、制御信号6により電流通過を制
御する回路5を、前記トランジスタ3とD/A変換変換
器内間、またはD/A変換器1内部に挿入したことで構
成する。The present invention has the following configuration in a semiconductor integrated circuit that controls the internal operation of a D/A converter connected to the complementary MO3 type device 3. That is, a circuit 5 for controlling current passage using a control signal 6 is inserted between the transistor 3 and the D/A converter or inside the D/A converter 1.
第2図は第1図における電流通過を制御する回路5をD
/A変換変換器内部に挿入した場合を示す。FIG. 2 shows the circuit 5 for controlling the passage of current in FIG.
The case where it is inserted inside the /A conversion converter is shown.
[作用]
第1図において、端子6から印加した信号は電流通過を
制御する回路5において制御動作を行う。[Operation] In FIG. 1, a signal applied from the terminal 6 performs a control operation in the circuit 5 that controls the passage of current.
即ち、端子6からの単一の制御信号により、回路5につ
いてインバータとD/A変換器1との導通をオフとすれ
ば、ディジタル信号の印加に関係なく、D/A変換器1
の動作が停止する。そのため所定の電力低下時の状態を
容易に求めることが出来る。That is, if conduction between the inverter and the D/A converter 1 in the circuit 5 is turned off by a single control signal from the terminal 6, the D/A converter 1 is turned off regardless of the application of the digital signal.
operation stops. Therefore, the state at the time of a predetermined power drop can be easily determined.
第2図の動作は第1図の場合と同様である。The operation in FIG. 2 is similar to that in FIG.
[実施例]
第3図・第4図は第1図についての実施例回路図を示し
、第5図は第2図についての実施例回路図を示す。[Embodiment] FIGS. 3 and 4 show an embodiment circuit diagram for FIG. 1, and FIG. 5 shows an embodiment circuit diagram for FIG. 2.
第3図は制御回路5としてアント回路7を使用する場合
で、7−0〜7−nはそのアンド回路を示す。FIG. 3 shows a case where an ant circuit 7 is used as the control circuit 5, and 7-0 to 7-n indicate the AND circuits.
D/A変換器1を通常に動作させるときは、制御信号印
加端子6から“H”レベル信号を印加する。When operating the D/A converter 1 normally, an "H" level signal is applied from the control signal application terminal 6.
その信号は端子2に印加されたディジタル信号がアンド
回路7を経てD/A変換器1へ人力される。The signal is a digital signal applied to the terminal 2 and is inputted to the D/A converter 1 via the AND circuit 7.
そして信号端子6を“L”レベルとすれば、ディジタル
信号端子2からの信号がアンド回路7を通過出来ない。If the signal terminal 6 is set to the "L" level, the signal from the digital signal terminal 2 cannot pass through the AND circuit 7.
そのためD/A変換器1が不作動となるから、電源側の
電流を測定すれば電力低下時の値が得られる。As a result, the D/A converter 1 becomes inactive, and by measuring the current on the power supply side, the value at the time of power reduction can be obtained.
第4図は制御回路5として電子的スイッチ8を使用する
例であって、Pチャネル・NチャネルFETを背中合わ
せに接続して、“L”、H”しヘルの制御信号を印加す
れば、スイッチとして動作する。スイッチオフの状態で
電力低下時の電流測定を行う。FIG. 4 shows an example in which an electronic switch 8 is used as the control circuit 5. If P-channel and N-channel FETs are connected back to back and a control signal of "L" and "H" is applied, the switch can be switched. Operates as a power-down current measurement with the switch off.
第5図は第4図に示すようなスイッチをD/A変換器内
部に挿入した場合を示す図である。スイッチオフの状態
で電流測定を行えば電力低下時の値が得られる。FIG. 5 is a diagram showing a case where a switch as shown in FIG. 4 is inserted inside a D/A converter. If you measure the current with the switch off, you will get the value when the power drops.
[発明の効果]
このようにして本発明によると、D/A変換器に対する
ディジタル信号の設定によらずに、D/A変換器の動作
停止状態を得ることが出来る。しかもその状態設定のた
め必要とする信号も単一のもので良いから、半導体集積
回路を簡易確実に動作させることが出来る。[Effects of the Invention] In this way, according to the present invention, it is possible to obtain a state in which the operation of the D/A converter is stopped without depending on the settings of digital signals for the D/A converter. Moreover, since only a single signal is required for setting the state, the semiconductor integrated circuit can be operated easily and reliably.
第1図は本発明の原理構成を示す図、
第2図は第1図の変形回路を示す図、
第3図〜第5図は本発明の実施例の構成を示す図、第6
図は従来のC−MOS回路を示す図である。
D/A変換器
ディジタル信号印加端子
相補型MOSデバイス
アナログ信号出力端子
電流通過を制御する回路
単一信号印加端子FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing a modified circuit of FIG. 1, FIGS. 3 to 5 are diagrams showing the configuration of an embodiment of the present invention, and FIG.
The figure shows a conventional C-MOS circuit. D/A converter Digital signal application terminal Complementary MOS device Analog signal output terminal Circuit that controls current passage Single signal application terminal
Claims (1)
(1)の動作を制御する半導体集積回路において、制御
信号(6)により電流通過を制御する回路(5)を、前
記相補型MOSデバイス(3)とD/A変換器(1)と
の間、またはD/A変換器(1)内部に挿入したことを
特徴とする半導体集積回路。In a semiconductor integrated circuit that controls the operation of a D/A converter (1) connected to a complementary MOS device (3), a circuit (5) that controls current passage by a control signal (6) is connected to the complementary MOS device (3). A semiconductor integrated circuit characterized by being inserted between a device (3) and a D/A converter (1) or inside the D/A converter (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1674090A JPH03220916A (en) | 1990-01-26 | 1990-01-26 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1674090A JPH03220916A (en) | 1990-01-26 | 1990-01-26 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03220916A true JPH03220916A (en) | 1991-09-30 |
Family
ID=11924665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1674090A Pending JPH03220916A (en) | 1990-01-26 | 1990-01-26 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03220916A (en) |
-
1990
- 1990-01-26 JP JP1674090A patent/JPH03220916A/en active Pending
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