JPH03220919A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To improve the resolution without slowing down the response speed by applying the high-order n-bit of an input data value in a bit number (m) larger than the bit number (n) of the resolution of a pulse width modulation counter as the input digital value of a pulse width modulation counter and setting a digital value fed to a period setting circuit corresponding to the input data value. CONSTITUTION:A rate generator 6 generates a signal representing the period (t) of an output pulse signal of a pulse width modulation counter 2 corresponding to a digital value T given from a control section 8 and applies the signal to the pulse width modulation counter 2 as a reset signal. The control section 8 generates a digital signal X' fed to the pulse width modulation counter 2 by using a high-order 16-bit from the input digital value X, e.g. in 21-bit. Moreover, a digital value T fed to the rate generator 6 is generated corresponding to the input data value. Thus, even when the bit number of the input data value X is increased and the required resolution is high, the response speed is accelerated by decreasing the bit number of the pulse width modulation counter 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital-to-analog (DA) converter that converts a digital signal into an analog signal.

DA converters are used as interfaces between digital devices and analog devices in various fields such as measurement, control, communication, and home appliances. for example.

Suitable for outputting processed data to a recorder in chromatography equipment such as gas chromatographs and liquid chromatographs.

(Prior Art) As a DA converter for a measuring instrument, an R-2R ladder type DA converter using a ladder resistor network is mainly used. It is difficult to obtain high resolution and high accuracy with a ladder-type DA converter, and it is also expensive.

Another type of DA converter is a pulse width modulation (PWM) type DA converter that converts an input digital value into a pulse width and passes the pulse signal through a low-pass filter circuit to create an analog signal. .

In a PWM type DA converter, the output pulse signal has a constant repetition period, and its pulse width is modulated according to the input digital amount.

(Problem to be solved by the invention) A PWM type DA converter has the advantage of being cheaper to construct than a ladder type DA converter, but it is difficult to increase the resolution by increasing the number of bits of the input digital signal. Then, there is a problem that the response speed becomes slow.

An object of the present invention is to take advantage of the advantages of a PWM type DA converter that can be constructed at low cost, while increasing the resolution without slowing down the response speed.

(Means for Solving the Problems) The present invention provides a period setting circuit that outputs a periodic signal corresponding to a given digital value as the period of a pulse width modulation counter, and a period setting circuit that outputs a periodic signal corresponding to a given digital value as the period of a pulse width modulation counter, and a resolution of the pulse width modulation counter whose resolution is larger than n. The control section supplies the upper n bits of an input data value having m bits as an input digital value to a pulse width modulation counter, and also sets a digital value to be supplied to a period setting circuit in accordance with the input data value.

In a preferred embodiment, the control section calculates the value of the pulse width modulation counter 2, where X is a 1m-bit input data value and X' is an n-bit (m>n) digital value supplied to the pulse width modulation counter 2. The digital value supplied to the period setting circuit is set so that the repetition period t of the output pulse becomes t=to.2(t)-'').X'/X (where to is reference synchronization).

(Operation) In the present invention, input data having a large number of bits is used to increase resolution. As a pulse width modulation counter that modulates the pulse width according to input data, a counter with a bit number smaller than the number of bits of the input data is used, and the upper bits of the input data are counted and the lower bits are discarded. Errors caused by reducing the number of bits of input data are corrected by adjusting the repetition period of the output pulse signal by yA in accordance with the input data.

(Example) FIG. 1 represents one embodiment.

2 is a pulse width modulation (PWM) counter, which has a resolution of, for example, ↓6 bits. 8 is a control section, and a 16-bit digital signal X' is supplied from the control section 8 to the pulse width modulation counter 2.

The pulse width modulation counter 2 creates and outputs a signal having a pulse width X' corresponding to the digital signal X'. 6 is a pulse width modulation period setting rate generator, for example 1
It is assumed that the resolution is 6 bits. The rate generator 6 creates a signal representing the repetition period t of the output pulse signal of the pulse width modulation counter 2 in response to the digital value given from the control unit 8, and supplies this as a reset signal for the pulse width modulation counter 2. . The control unit 8 is, for example, 2
From the input data value of 1-bit digital value X, its upper 1
A digital signal X' to be supplied to the pulse width modulation counter 2 is created using 6 bits, and a digital value T is supplied to the rate generator 6 corresponding to the input data value X.
Create.

A common clock signal is supplied to the pulse width modulation counter 2 and the rate generator 6.

The signal to be output, that is, the input data value X to the control unit 8
The resolution is 2 bits, and the pulse width modulation counter 2
Since the resolution of pulse width modulation counter 2 is 16 bits, in order to prevent the output of pulse width modulation counter 2 from being saturated, control section 8 first sets 21
Bit data X is shifted to the right by 5 bits to create 16-bit data X'. Now, the value of X is a binary number r 101010101010101010101 J
Suppose it was.

The digital value X' supplied to the pulse width modulation counter 2 becomes r10IOIOIOIOIOIOIOIOJ, and the lower 5 bits of information are missing. At this time, the output is rlO
lololololololololooooooJ/rl
OlololololololololololJ = Output smaller by Y.

Therefore, in order to correct this reduced output, the digital value T of the repetition period t given from the control unit 8 to the rate generator 6 is calculated by increasing the repetition period t of the output pulse signal of the pulse width modulation counter 2 by the ratio of the above Y. It is calculated to make it smaller.

The operation of the DA converter shown in FIG. 1(A) will be explained with reference to FIG. 1(B).

When a signal with period t is input from the rate generator 6 as a reset signal to the pulse width modulation counter 2, the output pulse signal of the pulse width modulation counter 2 becomes high level due to the input of the reset signal, and the clock of the digital value X' is counted. (pulse width x') is maintained at a high level.

The control unit 8 inputs the input data value X as shown in FIG.
Create X' by right-shifting by 5 bits in binary.

X’=X/32 It is.

Also, as the repetition period t.

It is created using the formula t=(2(m-1)・32X'/X.(2(m-1) is the full scale of the rate generator 6 as the reference period to, and 3
2X'/X is an error correction value.

The pulse width modulation counter 2 outputs a pulse signal having a pulse width x' (corresponding to the duty) with a period t, and this output pulse signal is passed through the low-pass filter 4, so that the input data value The corresponding analog voltage becomes 0.

This analog output voltage 0 is supplied to a recorder or the like.

(Effects of the Invention) According to the present invention, even if the input data value has a large number of bits and a high resolution, the response speed can be increased by reducing the number of bits of the pulse width modulation counter. On the other hand, errors caused by reducing the number of bits of the pulse width modulation counter are corrected by adjusting the repetition period of the output pulse signal in accordance with the input data value.

Thus, according to the present invention, a high-resolution DA converter can be realized at low cost without using special parts.

[Brief explanation of drawings]

FIG. 1(A) is a block diagram showing one embodiment. (B) is a waveform diagram showing the output pulse signal of the pulse width modulation counter, and FIG. 2 is a flowchart showing the operation of the control section in the same embodiment. 2...Pulse width modulation counter, 4...Low pass filter, 6...Pulse width modulation cycle setting rate generator, 8...Control unit.

Claims (2)

[Claims] (1) In a pulse width modulation type digital-to-analog converter equipped with a pulse width modulation counter that converts an input digital value into a pulse width and a conversion circuit that converts the output of the pulse width modulation counter into an analog quantity, a period setting circuit that outputs a periodic signal corresponding to a digital value as the period of the pulse width modulation counter; A control section configured to supply a digital value as an input digital value to a pulse width modulation counter and to set a digital value supplied to the period setting circuit in accordance with an input data value.
analog converter. (2) In the control unit, the m-bit input data value is
and n bits (m
>n) is the digital value of 2. The digital-to-analog converter according to claim 1, wherein the digital value supplied to the period setting circuit is set so as to be synchronous.