JPH0322146A - Microprogram control device - Google Patents

Abstract

PURPOSE:To facilitate the calculation of the inspection ratio of a microprogram and the calculation of the inspection drop-out of the same by delivering information stored in a memory to a service processor every time a trace memory becomes a full state, and tracing all the microprograms during execution. CONSTITUTION:A means to obtain a signal COP showing that the trace memory became the full state in conformity to an instruction from the service processor (SVP), a flip flop for operating clock stop control to be turned into a set state by this signal, and a circuit to set interruption to the service processor by the set output of the flip flop are provided. Then, the device is constituted so that trace data stored in the trace memory 14 is taken in the service processor (SVP) every time the trace memory 14 becomes the full state. Accordingly, all the steps of the microprocessor can be traced. Thus, the calculation of the inspection ratio and the calculation of the inspection drop-out of the microprogram can be facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a microprogram control device having a full trace function of an executed microprogram.

(Prior Art) Conventionally, the trace function of a microprogram in a device controlled by a microprogram has been used to trace a clock at a specified address using a microaddress match function etc. for the purpose of debugging the microprogram or analyzing a problem. This is used to stop the program and trace back the microprogram steps that have been executed up to that point.

At this time, the latest information executed up to that point remains in the trace memory for the memory capacity, but the previous information has been updated.

The information required at this time is about several steps to several tens of steps, but the memory used is often from the capacity of a memory chip to several kilowords or more.

On the other hand, when developing a device, it is necessary to confirm whether thorough inspection can be performed using a system test program or the like.

To do this, by executing the program to be inspected,
It is necessary to check whether all steps of the microprogram are being executed, but there is a limit to the capacity of trace memory, etc., and for such checks, it is necessary to check whether all steps of the microprogram are being executed. It was difficult to use existing tracing methods.

(Problem to be Solved by the Invention) As mentioned above, there has been no effective testing method in the past to check whether all steps of a microprogram are being executed during device development, etc. .

The present invention has been made in view of the above-mentioned circumstances, and in a device controlled by a microprogram, it is possible to effectively utilize a trace memory to check whether all steps of the microprogram have been inspected by a test program or the like. The purpose is to provide a microprogram control device that can be easily verified.

[Configuration of the invention (Means and effects for solving the three problems) The present invention consists of the first
As shown in the figure, a microprogram sequencer 11,
Microprogram memory 12. A trace memory 14 for tracing the microprogram is included in the microprogram control mechanism section consisting of the microinstruction register 13 and the like. Trace memory address counter l
5, and a service processor interface 16 that controls them, No. 13 (in the embodiment, the trace memory Carry-out signal cop of address counter 15
), a flip-flop for operating clock stop control that is set to a set state by the same signal, and a circuit that interrupts the service processor by the set output of the flip-flop, so that the trace memory 14 is in a full state. The trace data stored in the trace memory I4 is loaded into the service processor (SVP) each time the trace memory I4 is used. All steps can be traced and the test can easily and efficiently check whether all steps have been tested.

At this time, if the capacity of the trace memory l4 is extremely small, it will take a long time to trace all the steps of the microprogram, but as mentioned above, the trace memory normally used is It uses more than a kiloword, and therefore, with a simple configuration that makes effective use of trace memory, it is possible to efficiently trace all steps of a microprogram executed in a system test.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, l1 is a microprogram sequencer, which controls the address of the microprogram memory 12. 12 is a microprogram memory, from which data (microinstructions) at an address specified by the microprogram sequencer 11 is read. A microinstruction register 13 sets a microinstruction to be executed read from the microprogram memory l2. The data (microinstructions) output from this microinstruction register 13 are used to control various parts within the device. Reference numeral 14 denotes a trace memory for tracing the microprogram memory address output from the microprogram memory 12, and here it is constructed with a capacity of several kilowords determined by the unit capacity of the semiconductor memory chip. l5 is a counter that controls the address of the trace memory 14-, and when counting when the trace memory 14 is full, it becomes "1".
Outputs level carry-out signal (COP). l
A service processor interface 6 is connected to a service processor (SVP) and performs various controls for diagnosis within the device. Reference numeral 17 denotes a clock stop flip-flop, which inhibits and controls the clock within the device according to the designation of the service processor (SVP). In addition, A is an AND gate, N is a NAND gate, O is an OR gate, and A
(1) is a negative logic AND gate, and ■ is an inverter.

The operation of one embodiment of the present invention will now be described with reference to FIG.

The microprogram memory 12 has its address controlled by the microprogram sequencer 11 and outputs microinstructions to be executed in accordance with the operating clock. The microinstruction read from the microprogram memory l2 is set in the microinstruction register l3 in synchronization with the operating clock. Data (microinstructions) output from the microinstruction register 13 are supplied to predetermined units (not shown) in the device, and the instructions are executed by controlling each unit.

Further, the trace memory l4 is under address update control (usually counted up) by a trace memory address counter l5, and the microprogram address output from the microprogram sequencer 1l is written therein.

Note that when the trace data in the trace memory l4 exceeds the memory capacity, the old data is discarded so that the latest data always remains.

Normally, the trace memory l4 is used when debugging a microprogram or analyzing a problem. In this case, a micro address stop function (not shown) in the service processor interface 1B to which the service processor (SVP) is connected is used to
) is compared with the microprogram address, and when the addresses match,
A flip-flop (not shown) similar to the clock stop flip-flop 17 is set to stop the operating clock in the device, and the service processor interface l6
The trace data in the trace memory 14 is saved in the service processor (SVP) via the service processor (SVP).

In such a case, the trace memory l4 data (microprogram address according to the execution microinstruction) required is from a few steps to several tens of steps, but the memory used is from a memory chip unit capacity to several kilowords or more. There are many.

The present invention focuses on this point, and the trace memory l4
(i.e., a carry-out signal (COP-“1”) from trace memory address counter l5)
Equipped with a function to stop the operating clock of the device (each time a system test program is output), it traces all microprograms executed by a system test program, etc., and checks whether the program tests all steps of the microprogram. It provides a means for testing.

During tracing of all steps, the service processor (SVP) selectively outputs control signals a to d via the service processor interface 16 according to a predetermined sequence to execute this trace control. .

First, before starting the inspection, the service processor (S
Under the control of the service processor interface 16 (VP), the service processor interface 16 performs device processing when the trace memory l4 becomes full (i.e., when the carry-out signal (COP-“1°)” is output from the trace memory address counter 15). In order to enable control to stop the internal operating clock, a control signal a of "1° level" is output in advance.

When a microinstruction read from the microprogram memory l2 is executed at any time according to the operating clock, the trace memory address counter l5 updates the address (
count up), and accordingly the trace memory l4
The data of the microprogram address according to the executed microinstruction is stored.

When the trace memory l4 becomes full, the trace memory address counter l5 outputs a carry-out signal (C O P) at the '1'' level.

This carry-out signal (COP-1#) is ANDed with the control signal a (-1°) issued from the service processor interface l6, and when the condition is met, a signal is output (1°). The clock stop flip-flop 17 is set at the rising edge of the operating clock.When the clock stop flip-flop 17 is set, its reset output (0-“0”) causes the microprogram sequencer 11, microinstruction register 13, trace memory 14, The output of the operation clock and associated control signals to the trace memory address counter l5 is prohibited.Furthermore, at this time, the set output (Q-1) of the clock stop flip-flop l7 is prohibited.
1") is subjected to an AND condition with the control signal b (usually "1")' output from the service processor interface 1B, and when the condition is met, the output (-"1°) causes the clock stop flip-flop l7 holds the set state.

Further, the set output of the clock stop flip-flop l7 is inputted to the service processor interface l6, and when the clock stop flip-flop l7 is in the set state, an interrupt is generated to the service processor (SVP) (not shown). .

When the above interrupt occurs, the service processor (SVP) switches the control signal a output from the service processor interface l6 from "1" to "0" and causes the trace memory address counter 15 to count up (or control signal d( for countdown)
For example, specify "1'" for count-up and "O" for count-down, and turn off the output enable signal e input to the microprogram sequencer 11 ("1"). Furthermore, after that, the control signal C output from the service processor interface l6 is set to "1" in order to read the trace memory l4. Data read from the trace memory 14 (microprogram address according to the executed microinstruction) is taken into the service processor (SVP) via the service processor interface 1B. At this time, the "1" level control signal C output from the service processor interface l6 is assumed to be output for one pulse each time one word is read from the trace memory 14, and the control signal C
It is synchronized with the hitl clock and is manually input to the trace memory address counter l5 to count up (or count down) the trace memory address counter l5.
let

When the service processor (SVP) reads the trace data of the trace memory l4 corresponding to its memory capacity, the service processor (SVP) sets the control signal a output from the service processor interface l6 to "1" in order to set the clock stop flip-flop l7 again. Furthermore, the control signal e is set to "0°" in order to output the microprogram address from the microprogram sequencer 11, and the control signal b is set to "0" to release the stop state of the device.The control signal b"O" is The condition with the set output of the clock stop flip-flop 17 cannot be taken, and the clock stop flip-flop 17 is turned off at the rising edge of the clock.
Clear.

As a result, the microprogram sequencer 11, microinstruction register 13, trace memory 1
4. The operation clock within the device is supplied to the trace memory address counter 15, and the actual execution of the microprogram is resumed.

By repeatedly performing such operations, it is possible to trace all of the microprograms executed in the system test while testing the system, and it becomes possible to examine the inspection status of the microprograms in the test. As a result, during system development, by determining the inspection rate of a microprogram using a test program or the like, it becomes possible to easily identify inspection omissions, and the system development period can be shortened.

[Effects of the Invention] As described in detail above, according to the present invention, a microprogram type device that has a trace memory that realizes a microprogram trace function and can be connected to a service processor during in-device diagnosis can be used. means for controlling an operating clock in the device to stop and saving information stored in the trace memory in the service processor when the trace memory becomes full; and means for controlling the device under the control of the service processor. and a means for releasing the stopped state of the operating clock in the microprogram, and transmits the information stored in the trace memory to the service processor each time the trace memory becomes full, and transfers the information stored in the trace memory to the service processor to release the stopped state of the operating clock in the microprogram. By configuring the configuration to include an inspection function that performs tracing, it is possible to trace all microprograms that are being executed.This makes it possible to determine the inspection rate of microprograms using test programs, etc. during system development. It is now possible to easily identify defects and inspection omissions, and the development period can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1l...Microprogram sequencer, 12...
Micro program memory, l3... Micro instruction register, 14... Trace memory, l
5...Trace memory address counter, 1B...
Service processor interface, l7...Cro-Soxt Sop flip-flop, SvP...Service processor.

Claims (1)

[Claims] In a microprogram type device having a trace memory for realizing a microprogram trace function and to which a service processor can be connected during in-device diagnosis, means for detecting that the trace memory is in a full state. , a means for controlling an operating clock in the device to stop when the trace memory becomes full, and saving information stored in the trace memory in the service processor; and means for releasing the stopped state of the operating clock of the microprogram, and each time the trace memory becomes full, the information stored in the trace memory is transferred to the service processor, and all microprograms being executed are traced. A microprogram control device characterized by having an inspection function.